KR100496145B1 - Test Bench System for Media Access Control Devices - Google Patents

Abstract

A test bench system for a media access control device that implements a virtual media access control device for switching Ethernet packets between a media access control (MAC) interface and media access control. The system includes an Ethernet file read drive that loads a file that replaces packet information coming from a media access control layer into a media access control test bench, and packet information from the Ethernet file read drive on behalf of FIFOs present on each port. Source Ethernet FIFO stored for each port, Quad Ethernet drive that reads packet information stored for each port from source Ethernet FIFO and replaces QUAD media access control, Information expected and transmitted and received when actual transmission and reception occurs in each port And ETH_EXP_FIFO for receiving the output signal from the quad Ethernet drive, a receive bus for receiving the output signal of the quadruple Ethernet drive, and a transmit bus for transmitting the received packet data to the ETH_EXP_FIFO. . In the present system, the Ethernet file read drive reads an .ETH file, which is a test bench stimulus file that replaces packets coming from the Ethernet interface portion, for each port. After the reset signal falls to the active low, the media access control clock reads the information of the .ETH file all at once for every event.

Description

Test Bench System for Media Access Control Devices

The present invention relates to a test bench for Ethernet packet switching between media access control (MAC) layers, and more particularly, to an Ethernet packet between a media access control interface and a media access control device. A test bench system for a media access control device that implements a virtual match access control device for switching.

In general, a test bench is simply a device for testing the implemented hardware. The hardware can usually be implemented in VHSIC Hardware Description Language (VHDL) or Verilog language. However, this is just coded, so you need to run a simulation to verify that it works as you intended. It is also implemented as an ultrafast integrated circuit hardware language or beryllog.

1 is a configuration diagram of a test bench system for implementing a conventional virtual media access control device, Figure 2 is a flow chart of the prior art. The prior art configured as shown in FIG. 1 has the following operation sequence.

First, the Ethernet file read drive 30 reads the Ethernet file 10 each time a media access control clock event occurs (S1), and stores them in each source Ethernet first-in, first-out 40 (S2).

When receiving the received signal from the media access control interface (S3), the packet information is sent to the Ethernet terminal drive 60 in the corresponding quadruple Ethernet drive 50 (S4).

After generating the packet with the packet information received from the Ethernet terminal drive 60, it is loaded on the receiving bus 80 (S5). At this time, the bus 80 used is a transmission / reception common bus.

The destination address information is then stored in the expected Ethernet first-in, first-out 70 corresponding to the destination terminal (S6), which is information to be compared with a packet transmitted later.

In the prior art operating as described above, a virtual access control device developed by LSI Logic Co., Ltd. is virtually implemented for a test bench, and when a switch block and a packet transmission / reception are performed, a bidirectional bus is designed to be sequentially tested instead of simultaneously performed. Use one bidirectional bus.

As a result, the test bench requires a waiting time until one operation is completed in packet transmission / reception, thereby reducing performance during the overall test. Therefore, this phenomenon reduces the reliability of the circuit.

Therefore, the present invention was devised to solve the above problems, and by separating the transmission and reception operations in the media access control test bench, it is possible to use the full bandwidth, and improve the performance during the overall test It is an object of the present invention to provide a test bench system for a media access control device for switching Ethernet packets between media access control layers.

The above and other objects and novel features of the present invention will become more apparent from the following detailed description of the invention and the accompanying drawings.

The test bench system for a media access control device according to the present invention, which was devised to achieve the above object, uses a virtual media access control device to switch Ethernet packets between a media access control (MAC) interface and a media access control. In our test bench,

An Ethernet file read drive for importing a file in place of packet information coming from the media access control layer into the media access control test bench;

A source Ethernet FIFO storing packet information from the Ethernet file read drive for each port in place of the FIFOs present in each port;

A quad ethernet drive that reads packet information stored for each port from the source Ethernet FIFO and replaces QUAD media access control;

ETH_EXP_FIFO receiving an output signal from the quad Ethernet drive to check whether the expected information and the actual packet information match when transmission and reception occur in each port;

A receive bus which receives an output signal of the quad Ethernet drive; And

And a transmission bus for transmitting the received packet data to the ETH_EXP_FIFO.

In the present invention, the media access control layer is included in the switch chip, and the Ethernet file read drive reads the .ETH file, which is a test bench stimulus file substituting packets coming from the Ethernet interface portion, for each port. After the reset signal falls to active low, the media access control clock reads the information of the .ETH file all at once for each event, uses full bandwidth when sending and receiving, and separates sending and receiving operations to improve system performance during the overall test. It is preferable to carry out.

The present invention is a hardware implementation of a virtual media access control apparatus for transmitting / receiving an Ethernet packet to a switch block (switch engine), and provides a high speed packet transfer between a media access control layer block and a switch block. ) To test

This can be achieved by using a separate bus for source / first-in, first-out, and expected Ethernet first-in, first-out, corresponding to each terminal of the media access control device. Test is now possible.

In addition, the media access control test bench (MAC_Tb) used in the present invention is not intended to test the media access control apparatus but performs a function of substituting the media access control block using the characteristics of the media access control apparatus.

In the present invention, after creating a virtual media access control device as a test bench to replace the media access control device in the media access control layer, a media access control test bench is created to implement high-speed packet transmission with the media access control interface. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 3 is a configuration diagram of a test bench system for a media access control device according to the present invention. Referring to FIG. 3, the present invention creates a virtual media access control apparatus for a test bench to replace media access control in a media access control layer, and then implements media access to implement high-speed packet transmission with the media access control interface. Create a control test bench (hereafter MAC_Tb). This MAC_Tb is configured as follows.

Ethernet file read drive block (ETH_READ_FILE_DRV) 120, quad media, which reads the Ethernet file (ETH file) 100, which replaces the information of packets coming into the media access control layer, to the media access control test bench 110 Four Quad Ethernet Drives (ETH_QUAD_DRV) # 0 to Quad Ethernet Drives # 3 Block 140 Replaced by Access Control Unit, 16 Ethernet Terminals Representing Each Terminal and Running Substantial Operations on the Test Bench Drive (ETH_PORT_DRV) # 0 to Ethernet terminal drive # 15 block (one Ethernet terminal drive has four Ethernet terminal drives) 150, first-in first-out at each terminal 16 source Ethernet first-in, first-out (ETH_SRC_FIFO) (0 to 15) block 130 storing information of packets from Ethernet file read drives on behalf of FIFOs. And 16 expected Ethernet first-in, first-out (ETH_EXP_FIFO) (0 to 1) to check whether the expected and identical packet information match when packet transmission / reception (Rx / Tx) occurs at each terminal. 15) The block 160 is composed of a total of five blocks.

The operations of each block are as follows.

1) Ethernet file read drive 120: Reads the Ethernet file 10, which is a test bench stimulus file that replaces packets coming from the Ethernet interface, by segmenting each terminal. Then, packets are stored in each source Ethernet first-in, first-out 40. At this time, when the Ethernet file is read, the media access control clock reads the information of the Ethernet file 100 at the same time whenever the media access control clock occurs after the reset signal falls to active low. Read.

4) Quad Ethernet Drive 140: This block is designed to emulate the LSI Quad Cascade (CASCADE). One quad Ethernet drive 140 has four terminal drivers 150. Include. Accordingly, there are four quadruple Ethernet drives 140 in total for the 16 terminals.

3) Ethernet Terminal Drive 150: This block deals with packet transmission between the source Ethernet first-in, first-out block 130 and the switch engine. This block generates an error such as over_run or under_run when the packet is transmitted / received, or accepts the information of the packet stored in the source Ethernet first-in-first-out 130 packet. Substantial media access control, such as performing packet generation, accepting packets transmitted via switching from the media access control interface to expected Ethernet first-in, first-out 160 to compare and retrieve information that matches the expected packet information. All operations of the test bench 110 are done in this block. Since four Ethernet terminal drives 150 are configured in one quadrature cascade, a total of 16 Ethernet terminal drives 150 exist.

4) Source Ethernet first-in, first-out 130: This is a block that substantially replaces first-in, first-out at each terminal and contains source packets that are received by the switch engine to the media access control interface. Then, the information of all packets of the Ethernet files 100 read in the Ethernet file read drive 120 is stored in this block.

5) Expected Ethernet first-in first-out 160: When a packet of the source Ethernet first-in-first-out 130 is received through the Ethernet terminal drive 150, a packet having a destination port and a destination address information is expected. It is also stored in the Ethernet first-in, first-out 160. When this packet is sent back from the switch engine, it is written to this block to perform a function of comparing and retrieving whether it matches the first expected information and performing a search.

In the present invention, the buses 170 and 180 having separate transmission / reception are used, in which the transmission / reception is transmitted to one single bus unlike the conventional art. In addition, basic operations to be transmitted / received operate in the same process as in the prior art.

In addition, the media access control layer is created as a media access control test bench 110 in the Ethernet switch to perform a test with the media access control interface. Especially, when the media access control layer part is included in the switch chip, packets can be sent and received more efficiently and quickly. do.

While the invention is susceptible to various modifications and alternative forms, the disclosure thereof has been described with reference to specific embodiments only. It is to be understood, however, that the present invention is not limited to the specific forms referred to in the specification, but rather that the invention is intended to cover all modifications, equivalents, and substitutions within the spirit and scope of the invention as defined by the appended claims. It should be understood to include.

In the present application operating as described above, the effects obtained by the representative ones of the disclosed inventions will be briefly described as follows.

The present invention implements a virtual match access control device for switching Ethernet packets between the media access control interface and the media access control device as a test bench, by separating the transmission and reception buses, thereby improving the reliability of the circuit and It is possible to transmit the packet of, and improve the efficiency in the overall test.

1 is a configuration diagram of a test bench system for a conventional media access control device.

2 is a flowchart of operation of the prior art;

3 is a configuration diagram of a test bench system for a media access control device according to the present invention;

<Description of the symbols for the main parts of the drawings>

10, 100: Ethernet file

20, 110: Media Access Control Test Bench

30, 120: Ethernet file read drive

40, 130: Source Ethernet first in, first out

50, 140: Quad Ethernet Drive

60, 150: Ethernet terminal drive

70, 160: Expected first-in, first-out

80: transmit / receive bus

170: receive bus

180: transmit bus

Claims (6)

A test bench that implements a virtual media access control device to switch Ethernet packets between a media access control (MAC) interface and media access control. An Ethernet file read drive for importing a file in place of packet information coming from the media access control layer into the media access control test bench; A source Ethernet FIFO storing packet information from the Ethernet file read drive for each port in place of the FIFOs present in each port; A quad ethernet drive that reads packet information stored for each port from the source Ethernet FIFO and replaces QUAD media access control; ETH_EXP_FIFO receiving an output signal from the quad Ethernet drive to check whether the expected information and the actual packet information match when transmission and reception occur in each port; A receive bus which receives an output signal of the quad Ethernet drive; And A test bench system for a media access control device, comprising a transmission bus for transmitting the received packet data to the ETH_EXP_FIFO. The test bench system of claim 1 wherein the media access control layer is included in a switch chip. 2. The test bench system of claim 1, wherein the Ethernet file read drive reads the .ETH file, which is a test bench stimulus file that replaces packets coming from the Ethernet interface portion, for each port. 4. The test bench system of claim 3 wherein a media access control clock reads the information in the .ETH file all at once for every event after a reset signal falls to active low. 2. The test bench system of claim 1 wherein full bandwidth is used for transmission and reception. The test bench system of claim 1, wherein separate transmission and reception operations are performed to improve system performance during the overall test.