KR100233257B1 - Adsl processing system in atm switching system - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to an asymmetric digital subscriber line processing apparatus.

2. The technical problem to be solved by the invention

According to the present invention, asymmetric digital is provided so that high speed multimedia applications can be remotely serviced by varying up and down data transfer rates in an ATM exchanger, and mounted in the exchanger so as to grasp control and status of an ADSL subscriber in the exchange. To provide a subscriber line processing device.

3. Summary of Solution to Invention

The present invention provides an asymmetric digital subscriber line processing device in an asynchronous delivery mode switch to provide high speed multimedia service to remote ADSL subscribers by providing asymmetrically downlink data of 2Mbps or 6Mbps and uplink data of 64Kbps or 640Kbps. to provide.

4. Important uses of the invention

The present invention is used in an asynchronous delivery mode exchange.

Description

Asymmetric Digital Subscriber Line Processing Unit in Asynchronous Transfer Mode Switch

The present invention is capable of serving high-speed multimedia applications by connecting to an asymmetric digital subscriber line (ADSL) modem with different up and down data rates in an asynchronous transfer mode (ATM) switch. An asymmetric digital subscriber line processing apparatus for an ATM switch.

Conventional low-speed symmetric subscriber line processing devices transmit data at the same speed in both up and down directions, and therefore cannot serve various multimedia applications to higher speed services or remote subscribers. There was a problem that the control or the status of the ADSL subscriber is unknown.

Accordingly, the present invention, which is designed to solve the above problems, services high-speed multimedia applications remotely by varying the up and down data transmission speeds in an ATM exchanger, and is mounted in the exchanger to be implemented in the ADSL. It is an object of the present invention to provide an asymmetric digital subscriber line processing apparatus to understand the control and the status of the subscriber.

1 is an exemplary diagram of an asymmetric digital subscriber line (ADSL) matching device to which the present invention is applied.

2 is an exemplary illustration of an asymmetric digital subscriber line (ADSL) processing apparatus in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

10: asynchronous delivery mode layer processing unit

20: local clock distribution unit

30: asymmetric digital subscriber line processing unit

40: subscriber switching unit

50: alarm collecting unit

The present invention for achieving the above object comprises: a central control means for generating and buffering a data signal line, an address signal line, and a control signal line and receiving and processing control data via a local bus; Transmission cell processing means for converting and temporarily storing the transmission cells received through the local bus, converting the stored transmission cells in series, or forming a frame according to the selected subscriber's speed and transmitting them to the line; Test cell first-in, first-out means for receiving and temporarily storing a test cell for self-loopback test and transmitting it to the central control means through the local bus; Receiving cell processing means for temporarily storing a received cell or a loopback test cell received from the central control means via the local bus, converting the received cell into a predetermined bit, and then temporarily storing the received cell; Transmission / reception cell matching means for forming a loopback path of the transmission / reception cell or matching a transmission / reception cell bus; Control signal matching means for matching with the dual port RAM via the local bus and transmitting a function alarm signal and a hernia alarm signal to the asynchronous transfer mode processing means; And a clock signal matching means for converting a clock received from the local clock distribution means through the clock signal bus and then transmitting the clock signal to the transmission cell processing means and the receiving cell processing means via the local bus.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

1 is a diagram illustrating an asymmetric digital subscriber line (ADSL) matching device to which the present invention is applied.

The asymmetric digital subscriber line (ADSL) matching device includes an ATM processing unit 10, a local clock distribution unit 20, an asymmetric digital subscriber line processing unit 30, a subscriber switching unit 40, and an alarm collecting unit 50. It accommodates 64 ADSL subscriber lines and processes ATM cells to provide high speed ATM data services to ADSL subscribers.

The asynchronous delivery mode layer processing unit 10 transmits and receives 187.79 Mbps differential signal serial data to and from the subscriber switching unit 40 through an internal module connection (IMI) (not shown), and maintains a control unit of the central switching subsystem. Communicate with central control (not shown).

Through the transmit / receive cell bus, the asynchronous delivery mode layer processor 10 transmits the 16-bit transmit cell data TCELL0 to TCELL15 and the transmit cell start signal TSOC * indicating the start of the transmit cell to the asymmetric digital subscriber line processor 30. ), And receives the 16-bit receiving cell data RCELL0 to RCELL15 and the receiving cell start signal RSOC * indicating the start of the receiving cell from the asymmetric digital subscriber line processing unit 30. In addition, after receiving and polling the cell reception request signals CRREQ0 * to CRREQ15 * from the 16 asymmetric digital subscriber line processing units 30, the cell is received by the asymmetric digital subscriber line processing unit 30 that requests the reception of the cells in a predetermined order. Cell reception permission signals CRACK0 * to CRACK15 * are transmitted. At this time, if the received cell is an Operation Administration Maintenance (OAM) cell, it processes the operation maintenance function and transmits the response OAM cell to the ADSL subscriber.

Through the control signal bus, the asynchronous delivery mode layer processing unit 10 indicates the validity of the address signals EA1 to EA11, address signals for accessing the dual port RAM (DPRAM) in the asymmetric digital subscriber line processing unit 30. The valid signal EAS *, the data valid signal EDS * indicating the validity of the data signal, and the read / write signal ER * W specifying reading and writing of the data are transmitted, and the data signals ED0 to ED7 are transmitted. Send and receive). In addition, the sixteen asymmetrical digital subscriber line processing units 30 receive the function alarm signals FUNA0 to FUNA15 and the hernia alarm signals OFFA0 to OFFA15 of the asymmetric digital subscriber line processing unit 30 as logic high signals. At this time, the hernia alarm signal OFFA_A and the function alarm signal FUNA_A are transmitted to the alarm collection unit 50 as a logic high signal.

Through the clock signal bus, the asynchronous transfer mode layer processor 10 receives the main clock (23.4747 MHz) for clock synchronization in the module from the local clock distributor 20 and the cell bus clock (11.7373 MHz) for synchronization of the transmit / receive cell bus. Receive

Through the clock signal bus, the local clock distribution unit 20 receives a 46.9494 MHz local switching subsystem synchronization signal (LTSI) from the subscriber switching unit 40 at an emitter coupled logic (ECL) level and clocks it. Synthesized and divided to provide the main clock (23.4747 MHz) and the cell bus clock (11.7373 MHz) to the asynchronous delivery mode layer processor 10, and the main clock, the cell bus clock, And a frame sync clock (16.386 MHz). Also, the hernia alarm signal and the function alarm signal are transmitted to the alarm collection unit 50 as a logic high signal.

Through the transmit / receive cell bus, the asymmetric digital subscriber line processor 30 receives the 16-bit transmit cell data and the transmit cell start signal from the asynchronous delivery mode layer processor 10, and the 16-bit receive cell data and the receive cell start signal. Is transmitted to the asynchronous delivery mode layer processing unit 10. In addition, if there is a cell to be transmitted to the asynchronous delivery mode layer processing unit 10, the cell reception request signal for requesting the reception of the cell is transmitted to the asynchronous delivery mode layer processing unit 10, and the cell reception is allowed from the asynchronous delivery mode layer processing unit 10. Receiving the signal transmits the receiving cell and the receiving cell start signal to the receiving cell bus.

Through the control signal bus, the asymmetric digital subscriber line processor 30 asynchronously transfers the mode layer processor 10 to the address signal, the address valid signal, the data valid signal, and the read / write signal to match with the dual port RAM (DPRAM). Receives data from and transmits and receives data signals. Also, the function alarm signal and the hernia alarm signal are transmitted to the asynchronous delivery mode layer processing unit 10.

Through the clock signal bus, the asymmetric digital subscriber line processor 30 receives the main clock, the cell bus clock, and the frame synchronization clock from the local clock distributor 20.

FIG. 2 is an exemplary view illustrating an asymmetric digital subscriber line (ADSL) processing apparatus according to the present invention, where “21” is a central control unit, “22” is a transmitting cell processing unit, “23” is a receiving cell processing unit, and “24”. "25" denotes a test cell reception first-in first-out part, "25" denotes a transmission / reception cell matcher, "26" denotes a control signal matcher, and "27" denotes a clock signal matcher.

The transmit cell processor 22 includes a transmit cell controller 221, a virtual path identifier and a virtual channel identifier (VPI / VCI) table unit 222, a transmit cell first-in first-out (FIFO) unit 223, and an asynchronous delivery mode physical layer. A processing unit 224 is provided, and the receiving cell processing unit 23 includes a reception / test cell first-in first-out unit 231, a reception cell control unit 232, and a reception cell first-in first-out unit 233.

The asymmetric digital subscriber line processor 30 according to the present invention interworks with the asynchronous delivery mode layer processor 10 via a transmit / receive cell bus and a control signal bus and with the local clock distributor 20 through a clock signal bus.

The central control unit 21 having a 32-bit processor generates data signal lines, address signal lines, and control signal lines, buffers them, supplies them to the local bus, and combines these signals to devices and registers belonging to each functional unit. The asymmetric digital subscriber line processor 30 is provided with two 64kB ROMs for storing programs and four 128kB RAMs for storing data.

In addition, the central control unit 21 includes clock generators of 24.576 MHz and 6.312 MHz to buffer and divide the generated clocks and provide them to the transmitting cell processing unit 22 and the receiving cell processing unit 23 through a local bus. In the event of a manual reset by a reset or reset switch, a reset signal is generated and provided to the local bus. Also, it has a serial input / output function and receives asynchronous control data of 64 kbps rate or high speed synchronous control data of 640 kbps rate from the ADSL subscriber, converts it into an ATM cell, and transmits it to the test cell receiving first-in-first-out part 24 through a local bus.

Through the RS-232C communication port, the central control unit 21 provides a terminal connection function for debugging to each functional unit.

The transmission cell processing unit 22 receives the 16-bit transmission cell from the transmission / reception cell matching unit 25 through the local bus and converts the data into 8 bits. If the point-to-multipoint transmission is performed, the virtual path identifier (VPI: Virtual Path Identifier) is converted. And after converting the VPI and the VCI with reference to a virtual channel identifier (VCI) table, transmitting the transmitted cell to the first-in first-out unit 223 to temporarily store the inputted transmission cell, and then to the first-in first-out unit 223. In parallel, the transmission cell stored in parallel is converted to serial or 2M or 6M frame is formed according to the speed of the selected subscriber and transmitted to the line.

The transmission cell control unit 221 transmits and receives a control signal through a local bus, and receives a 16-bit transmission cell from the transmission / reception cell matching unit 25 and converts it into an 8-bit transmission cell. In the case of a point-to-multipoint transmission cell, the contents of the VPI / VCI table unit 222 are transmitted to one of the transmission cell first-in-first-outs (FIFO) of the four transmission cell first-in-first-out (FIFO). The VPI is converted to VPI and VCI, and then transmitted to the corresponding multiple subscribers of four FIFOs.

The virtual path identifier and virtual channel identifier (VPI / VCI) table unit 222 stores the VPI and VCI conversion tables for four lines of the point-to-multipoint transmission cell recorded by the central control unit 21 via the local bus. In the case of multi-point transmission, VPI and VCI are converted by referring to the transmission cell control unit 221.

The transmit cell first-in, first-out unit 223 is composed of four transmit cell first-in, first-out (FIFO) for each subscriber, and temporarily stores the transmit cell received from the transmit cell control unit 221 and then consists of four ATM physical layers. It transfers to the physical layer processing unit 224. In this case, four first-in, first-out (FIFO) speeds are used, and three first-in, first-out (FIFO) speeds can be extended to four.

The asynchronous delivery mode physical layer processing unit 224 is composed of four ATM physical layers for each subscriber to convert the parallel transmission cell received from the transmission cell first-in-first-out unit 223 into serial or 2M or 6M depending on the speed of the selected subscriber. After the frame is formed, it is transmitted to the ADSL subscriber. In addition, processing according to the function according to the ATM physical layer standard, and if there is no user cell automatically transmits the idle cell to always be connected to the ADSL subscriber.

The test cell reception first-in-first-out unit 24 receives the temporary loopback test cell from the asynchronous delivery mode physical layer processing unit 224 in the transmission cell processing unit 22 and temporarily stores it, and then transmits it to the central control unit 21 via the local bus. do. At this time, one first-in first-out (FIFO) at 1 kB speed is used, and one first-in first-out (FIFO) at 32 kB speed is expandable to one.

The reception cell processing unit 23 is a reception / test cell first-in-first-out unit 231 for temporarily storing a reception cell or a test cell, a reception cell control unit 232 for analyzing and converting an 8-bit received cell into 16-bit, and the converted A receiving cell first-in, first-out unit 233 for temporarily storing a 16-bit receiving cell is provided.

Through the local bus, the reception / test cell first-in-first-out unit 231 temporarily stores the test cell for the self-loopback test received from the central control unit 21 and then transmits the test cell to the reception cell control unit 232, and then, in the central control unit 21. The processed receiving cell for the received ADSL subscriber is temporarily stored and then transmitted to the receiving cell controller 232. At this time, one first-in first-out (FIFO) at 1 kB speed is used, and one first-in first-out (FIFO) at 32 kB speed is expandable to one.

The receiving cell control unit 232 analyzes the 8-bit receiving cell received from the receiving / test cell first-in-first-out unit 231, adds a board number and a subscriber number, and generates a 28-bit long 16-bit receiving cell to receive the first-in first-out. Transfer to section 233. In addition, when the cell reception request signal CRREQ * indicating that there is a reception cell to be transmitted is transmitted to the asynchronous delivery mode layer processing unit 10 and the cell reception permission signal CRACK * is received from the asynchronous transmission mode processing unit 10, the reception cell is received. The reception cell is transmitted to the reception cell first-in-first-out unit 233 together with the start signal RSOC *.

The receiving cell first-in-first-out unit 233 temporarily stores the 16-bit receiving cell received from the receiving cell control unit 232 and transmits the received 16-bit receiving cell to the transmit / receive cell bus matching unit 25. In this case, two 1kB first-in first-out (FIFO) is used to configure 16-bit first-in, first-out (FIFO) at 2kB speed, and 16bit first-in first-out (FIFO) at 32kB using two first-in first-out (FIFO) at 32kB speed. Expandable).

When the transceiver cell bus matching unit 25 performs its own loopback test under the control of the reception cell control unit 232 in the reception cell processing unit 23, the test cell received from the reception cell first-in-first-out unit 233 is the transmission cell processing unit. A loopback path is formed to be transmitted to the transmission cell control unit 221 within the cell 22. If the loopback test is not performed, the transmission cell is received and buffered from the asynchronous transmission mode layer processing unit 10 through the transmission / reception cell bus, and then transmitted. In step 221, the reception cell is received from the first-in, first-out unit 233, buffered, and then transmitted to the asynchronous delivery mode layer processing unit 10.

The control signal matching unit 26 is interlocked with the asynchronous transfer mode layer processing unit 10 through the control signal bus to provide 11-bit local address signals EA1 to EA11 and various control signals EAS *, EDS *, and ER * W. And transmit and receive the 8-bit data signals ED0 to ED7. In addition, it configures a dual port RAM of 2kB speed and communicates with the asynchronous delivery mode layer processing unit 10, and transmits the functional alarm signal and the hernia alarm signal to the asynchronous delivery mode layer processing unit 10 in a logic high state. .

The clock signal matching unit 27 combines the main clock (23.4747 MHz), the cell bus clock (11.7373 MHz), and the frame synchronization clock (16.384 MHz) from the local clock distributor 20 through the clock signal bus. ECL receives at the Emitter Coupled Logic (ECL) level, converts it to the Transistor Transistor Logic (TTL) level, and transmits the signal to the transmit cell processor 22 and the receive cell processor 23 through the local bus.

The asymmetric digital subscriber line processing apparatus according to the present invention accommodates four ADSL subscribers per board, and asymmetrically provides downlink data at 2 Mbps or 6 Mbps and uplink data at 640 kbps or 64 kbps to remote ADSL subscribers. High speed multimedia service can be provided.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains, and the above-described embodiments and accompanying It is not limited to the drawing.

As described above, the present invention provides a variety of multimedia applications such as faster video on-demand, distance education, remote entertainment, remote gaming, and high-speed Internet access to remote subscribers by varying the up and down data rates at ATM exchanges. It can be serviced and mounted in the exchange, so that the ADSL subscriber can be controlled even in the exchange or the status of the ADSL subscriber can be easily understood.

Claims (7)

Central control means for generating and buffering a data signal line, an address signal line, and a control signal line, and then receiving and processing control data via a local bus; Transmission cell processing means for converting and temporarily storing the transmission cells received through the local bus, converting the stored transmission cells in series, or forming a frame according to the selected subscriber's speed and transmitting them to the line; Test cell first-in, first-out means for receiving and temporarily storing a test cell for self-loopback test and transmitting it to the central control means through the local bus; Receiving cell processing means for temporarily storing a received cell or a loopback test cell received from the central control means via the local bus, converting the received cell into a predetermined bit, and then temporarily storing the received cell; Transmission / reception cell matching means for forming a loopback path of the transmission / reception cell or matching a transmission / reception cell bus; Control signal matching means for matching with the dual port RAM via the local bus and transmitting a function alarm signal and a hernia alarm signal to the asynchronous transfer mode processing means; And A clock signal matching means for converting a clock received from the local clock distribution means through the clock signal bus and then transmitting the clock signal to the transmission cell processing means and the receiving cell processing means via the local bus; Apparatus for processing asymmetric digital subscriber line in an asynchronous delivery mode switch comprising a. The method of claim 1, The transmission cell processing means, Transmission cell control means for transmitting and receiving a control signal through the local bus and converting a transmission cell received from the transmission and reception cell matching means into a transmission cell having a predetermined bit; Virtual path identifier and virtual channel identifier table means for converting the virtual path identifier and the virtual channel identifier read from the central control means via the local bus; Transmission cell first-in, first-out means for temporarily storing a transmission cell received from the transmission cell control means; And Asynchronous transmission mode physical layer processing means for converting a transmission cell received from the transmission cell first-in first-out means or forming a frame according to a selected subscriber's speed and transmitting the same to a subscriber Apparatus for processing asymmetric digital subscriber line in an asynchronous delivery mode switch comprising a. The method according to claim 1 or 2, The receiving cell processing means, Reception / test cell first-in, first-out means for temporarily storing a reception cell or a test cell received from the central control means; Receiving cell control means for analyzing the receiving cell inputted from the receiving / test cell first-in first-out means and converting the received cell into a receiving cell having a predetermined bit; Receive cell first-in first-out means for temporarily storing the received cell received from the receiving cell control means and transmitting the received cell to the transmit / receive cell matching means Apparatus for processing asymmetric digital subscriber line in an asynchronous delivery mode switch comprising a. The method of claim 1, The transmission and reception cell matching means, An asynchronous transfer mode exchanger which connects an address signal, a control signal, and a data signal up and down via the local bus and the control signal bus, and configures a dual port RAM to communicate with the asynchronous transfer mode processing means. Asymmetric Digital Subscriber Line Processing System in. The method of claim 2, The transmission cell converted by the transmission cell control means, An asymmetric digital subscriber line processing device in an asynchronous delivery mode switch, characterized in that it is 8 bits. The method of claim 3, wherein The receiving cell converted by the receiving cell control means, Asymmetric digital subscriber line processing apparatus in an asynchronous delivery mode switch characterized in that the 16-bit. The method of claim 1, The central control means, An asymmetric digital subscriber line processing apparatus in an asynchronous delivery mode switch characterized by comprising a 32-bit processor.

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