GB2293292A - SDH/ATM hybrid cross connect - Google Patents

Abstract

A hybrid cross connect for use in a synchronous digital communications network includes an asynchronous transfer mode (ATM) switch element 21, and ingress 22 and egress 23 means for interfacing the switch element with the synchronous network. The ingress interface 22 incorporates means for recovering data bytes from incoming synchronous frames, for assembling said bytes into ATM cells for presentation to the switch element and for providing each said ATM cell with source and destination addresses. The egress interface incorporates means for recovering the data bytes from the ATM cells and for assembling said bytes into synchronous frames. The arrangement extracts the payloads carried within the incoming STM's (Synchronous Transport Module) and distributes those payloads in a predetermined manner among the appropriate output STM's. <IMAGE>

Description

HYBRID CROSS CONNECT This invention relates to telecommunications systems and in particular to digital systems.

The Synchronous Digital Hierarchy defines a hierarchical set of digital transport structures, standardised for the transport of suitably adapted payloads over physical transmission networks. A Synchronous Transport Module (STM) is the information structure used to support section layer connections in the SDH. It consists of information payload and Section Overhead (SOH) fields organised in a block frame structure which repeats every 125 microseconds.

STM-1 is the basic STM and is defined for operation at 155 520 kbit/s. For a full understanding of the definitions and terms applicable to the SDH, the reader is referred to the ITU-T Recommendations G.707, G.708 and G.709.

A key item in such a system is a cross connect whose function is to extract the payloads carried within the incoming STM-ls and distribute them in a predetermined manner among the appropriate output STM-ls. A number of synchronous switching elements have been designed for this purpose. However, there is now an increasing interest in asynchronous transfer mode (ATM) technology and this has introduced a requirement for the use of an ATM switching element in SDH cross connect equipment. This has resulted in the problem of interfacing synchronous and asynchronous equipment.

The object of the invention is to minimise or to overcome this disadvantage.

According to the invention there is provided a hybrid cross connect for use in a synchronous digital communications network, the cross connect including an asynchronous transfer mode (ATM) switch element, and ingress and egress means for interfacing the switch element with the synchronous network, wherein the ingress interface incorporates means for recovering data bytes from incoming synchronous frames, for assembling said bytes into ATM cells for presentation to the switch element and for providing each said ATM cell with source and destination addresses, and wherein the egress interface incorporates means for recovering the data bytes from the ATM cells and for assembling said bytes into synchronous frames.

The arrangement extracts the payloads carried within the incoming STM's (Synchronous Transport Module) and distributes those payloads in a predetermined manner among the approprate output STM's.

An embodiment of the invention will now be described with reference to the accompanying drawings in which: Figure 1 is a block schematic diagram of a typical ATM switch element Figure 2 is a block schematic diagram of an ATM switch element adapted for use as an SDH hybrid cross connect: Figure 3 shows in schematic form the SDH payload to ATM cell conversion function of the hybrid cross connect of figure 2; and Figure 4 shows in schematic form the ATM cell to SDH frame conversion function of the hybrid cross connect of figure 2; As shown in figure 1,the ATM switch element consists of a number of input (11) and output 113) ports which ports interface with a switch fabric L12. Typically, ATM switches are designed to operate with ATM cells that are somewhat longer than the 53-byte International Standard.In the present example, 64-byte cells are used. Each cell contains a 53-byte information or payload field plus 11 bytes of overhead. The overhead is used internally by the switch and carries Source and Destination switch port addresses, cell type indications, an error checking capability, etc. Each input and output port is capable of servicing e.g. four independent cell streams in such a manner that an ATM cell appearing on any input stream may be switched across the fabric to appear on any desired output stream. Since the links between ports and the switch fabric operate at around 800 Mitts, after allowing for transmission overheads the switch element can handle the equivalent of one STM-1 cell stream per input and output.Thus, in the present example where sixteen input and sixteen output ports are provided, the switch element is capable of handling the equivalent of 64 STM-1 inputs and outputs Referring now to figure 2, the hybrid cross connect comprises an ATM switch element 21 provided at its ingress with input circuits 22 for converting SDH payloads to corresponding ATM cells and at its egress with output circuits 23 for converting ATM cells to corresponding SDH payloads. The arrangement extracts the various payloads carried within the STM-1 frames and converts those payloads to ATM cells for presentation to the switch. After switching, the cells are converted back into the correct format for placement within the desired outgoing STM-1 frames In general, an STM-1 is capable of carrying a variety of payloads within its frame structure.The bytes comprising individual payloads are interleaved throughout the STM-1 frame in a manner that is dependent on the particular payloads. The 'SDH Payload to ATM Cell Conversion' function can thus be refined into the following subfunctions: reception of 125 microsecond STM-1 frames processing of overhead bytes and frequency justification assembly of interleaved bytes of each payload into one or more ATM cells (the number of cells depends on the payload capacity) labelling of each cell with the address of the desired switch output port presentation of cells to ATM switch element input port.

Similarly, the 'ATM Cell to SDH Payload Conversion' function can also be refined, as follows: reception of cells from ATM switch element output port interleaving of individual bytes of received cells throughout the STM-1 frame, according to the payload type to which they belong generation of overhead bytes and correct location in the STM-1 frame assembly of complete STM-1 frame transmission of STM-1 frame.

The input conversion function is shown in detail in figure 3, the individual subfunctions being described below.

Optical Interface The optical interface receives the optical pulses at the STM-1 input and performs an opto-electrical conversion. It recovers clock timing from the resultant bit stream.

Frame Aligner The frame aligner searches for and recovers framing pattern which occurs at the beginning of each 125 psec frame.

Incoming Frame Map The incoming frame map keeps a record of the contents of the incoming STM-1 frame, which is updated as necessary by Management Information from the Hybrid cross-connect management function (not shown). The record includes not only the payload structure and payload location within the incoming frame but also the switch output port address to which the payload is destined.

Overhead Processor The overhead processor performs the appropriate processing of the STM-1 section overhead and the path overheads associated with the various payloads. It also performs pointer processing, to locate the individual payloads within the frame, and frequency justification when necessary.

Cell Assembly Control The cell assembly control decodes information received at its inputs and provides the addressing information necessary to locate individual payload bytes in their correct ATM cells.

Cell Assembly Buffer The cell assembly buffer accepts individual payload bytes from the incoming STM-1 frame and sequences and stores them in their correct locations, along with their 11 overhead bytes, so that correctly formatted 64-byte cells are available for each payload. A maximum of 84 ATM cells can be stored, corresponding to the highest number of individual payloads possible in one STM-1 frame, i.e. 84 x VC1 1. Any other payloads will always fit in less than 84 ATM cells.

Note that the cell assembly buffer actually consists of two sets of buffers, each comprising 84 rows by 64 bytes, operating in a 2phase mode. Thus, whilst one set of buffers is accumulating the current frame's worth of cells, the other set holds the previous frame's worth for transfer to the ATM switch input port.

Ready Queue When a particular cell has been completely assembled and is available for transfer to the ATM switch input port, the location of the cell is stored in the ready queue to await the correct conditions for transfer.

Output Buffer The output buffer stores one complete ATM cell in readiness for its high speed bit serial transfer to the ATM switch port.

The STM-1 input is received by the Optical Interface which performs opto/electrical conversion. The resulting conditioned bit stream is decoded to recover the baseband binary bit stream plus a suitable bit clock for the STM-1 rate at the input to the Frame Aligner (FA).

The FA clocks the incoming bit stream into its buffers and searches for STM-1 framing pattern. Having locked onto the framing pattern, the FA produces a Framing Pulse (FP) per frame (i.e. every 125 lisec) plus a byte stream which is byte aligned and synchronised with the FP.

The Overhead Processor (OP) receives both FP and byte stream from the FA. In conjunction with information obtained from the Incoming Frame Map (IFM), it is able to determine which bytes to process as overhead and which bytes to pass to the Cell Assembly Buffer (CAB). It must also determine the association of individual bytes to cells and where the cells are located in the CAB.

Having made these determinations, at the same time as it passes a byte to the CAB for buffering, the OP also passes information to the Cell Assembly Control. The latter decodes this information in order to address the correct row of the CAB into which the individual byte is to be located.

The CAB consists of two sets of 84 individual buffers, each of which can hold one 64 byte ATM cell. The two sets of buffers operate in two phase mode, so that as the first set is accumulating cells the second set is being emptied. Then, when the second set is empty, it begins to accumulate cells from the next STM-1 frame whilst the first set is emptied, and so on. The OP is responsible for ensuring the correct two phase operation of the CAB. It does this by switching cell assembly from the first set of buffers to the second set and back again in synchronism with the receipt of successive Frame Pulses.

A byte received by the CAB from the OP is located in the cell addressed by the CAC, where it occupies the endmost empty byte position. When a byte is received that is to occupy the first byte position in a cell, the OP informs the IFM of this fact. The IFM then appends the necessary overhead to the cell - including Source and Destination switch port addresses.

When the CAB has accumulated its first complete ATM cell from the incoming STM-1, the OP, which is aware of this fact, informs the Ready Queue (RQ) by means of the 'Cell n Ready' indication. This indication also conveys the location of the cell within the CAB and to which set of CAB buffers the indication refers. If the Output Buffer (OB) is empty, the RQ causes the available cell to be transferred from the CAB by means of the 'Read n' instruction (where 'n' is the location of the cell). If the OB is full, the RQ stores the cell ready indication, and any such subsequent indications, pending an indication from the OB that it has been emptied and can accept a further cell transfer.

The OB informs the ATM switch input port when it has a cell available for transfer by means of the 'Ready' indication. When it is able to accept the cell, the input port returns an 'Enable' instruction following which the OB transfers the cell in bit-serial form at the input port clock rate. (i.e. around 800 Mbit/s). Subsequent cells are transferred in similar manner until the CAB is emptied and becomes available to accept cells from the next STM-1 frame.

The output conversion function is shown in detail in Figure 4 and the individual subfunctions are described below.

Input Buffer The input buffer receives and buffers 64 byte ATM cells from the switch output port.

Outgoing Frame Map The outgoing frame map keeps a record of the contents of the outgoing STM-1 frame, which is updated as necessary by Management Information from the Hybrid cross-connect management function (not shown). The record includes not only the payload structure and payload location, but also details of any overhead not carried across the ATM switch with the payload that is required to be inserted into the outgoing frame and of any overhead carried across the ATM switch that needs to be modified.

Overhead Generator The overhead generator provides the overhead bytes that are to be inserted into the outgoing frame. It also performs pointer calculation to determine the values to be inserted into the pointer overheads.

Frame Assembly Control The frame assembly control decodes information received at its inputs to provide the addressing necessary to locate the individual overhead and payload bytes in their correct locations in the outgoing frame.

Frame Assembly Buffer The frame assembly buffer accepts individual overhead and payload bytes on its inputs and locates them in their correct positions so that a correctly formatted outgoing STM-1 frame is available every 125 lisec. 2430 byte positions are provided, corresponding to an STM-1 frame's worth.

Note that the frame assembly buffer actually consists of two sets of buffers, each capable of holding 2430 bytes, operating in a 2-phase mode. Thus, whilst one set of buffers is accumulating the current frame's worth of bytes, the other set holds the previous frame's worth for transmission at the STM-1 output.

Output Control The output control enables the transmission of the assembled STM1 frame in a cyclic manner every 125 lisec.

Optical Interface The optical interface receives STM-1 frames one byte at a time and transfers these in bit serial form at the line rate (155 520 kbit/s) to its electro/optical conversion capability for transmission to line.

The Input Buffer (IB) receives 64 byte ATM cells in bit serial form from the ATM switch output port, together with a suitable bit clock.

The IB processes the cell overhead bytes to recover the addressing information, which is passed to the Outgoing Frame Map (OFM). It also performs a serial to parallel conversion on the incoming cell stream and presents the results one byte at a time to the Frame Assembly Buffer (FAB).

The OFM receives addressing information from the IB and from this identifies the particular SDH payload (or part-payload) being carried by the input cell. This information is relayed both to the Frame Assembly Control (FAC) and to the Overhead Generator (OG).

The OG generates a Frame Start pulse every 125 lisec, synchronously with the network (SDH) clock, for use by the Output Control (OC). Immediately following this it generates the initial STM1 frame overhead (Section Overhead) which it passes in byte form to the FAB, at the same time passing the associated addressing information to the FAC. The OG also determines, from information that it receives from the OFM, what overheads it needs to generate (including pointers) for the various SDH payloads being assembled.

In particular, the OG determines whether any of the overhead carried across the switch with its associated payload needs modification. In this case, it overwrites the appropriate overhead bytes in the FAB, again by passing the bytes to the FAB at the same time as addressing information is conveyed to the FAC.

The FAC receives addressing information from the OFM, in respect of SDH payload bytes, and from the OG, in respect of overhead bytes. It decodes this information in order to provide the necessary addresses to the FAB for locating the individual bytes in their correct, interleaved positions throughout the STM-1 frame.

The FAB consists of two sets of 2430 buffers with each buffer capable of holding a single byte. The two sets of buffers operate in two phase mode, so that as the first set is accumulating bytes the second set is being emptied. Then, when the second set is empty, it begins to accumulate bytes for the next STM-1 frame whilst the first set is emptied, and so on. A byte received by the FAB is located in the position addressed by the CAC.

When the FAB has accumulated a complete STM-1's worth of bytes, a Frame Start pulse from the OG enables the OC. The OC then addresses the FAB in a cyclic manner to transfer one byte at a time into the Optical Interface (01), starting with the first byte position and working down to the 2430th. When the OC has emptied the first FAB, the next Frame Start pulse causes it to address the second FAB, then back to the first FAB, and so on.

The Ol buffers one byte at a time from the FAB. It clocks each byte at the line rate (155 520 kbit/s) in bit serial form and encodes the baseband binary data into the appropriate format for transmission.

The resulting conditioned bit stream undergoes electro/optical conversion to provide the STM-1 optical line output.

Claims (7)

CLAIMS:

1. A hybrid cross connect for use in a synchronous digital communications network, the cross connect including an asynchronous transfer mode (ATM) switch element, and ingress and egress means for interfacing the switch element with the synchronous network, wherein the ingress interface incorporates means for recovering data bytes from incoming synchronous frames, for assembling said bytes into ATM cells for presentation to the switch element and for providing each said ATM cell with source and destination addresses, and wherein the egress interface incorporates means for recovering the data bytes from the ATM cells and for assembling said bytes into synchronous frames.

2 A hybrid cross connect as claimed in claim 1, wherein said means for assembling said bytes into ATM cells is associated with first and second buffer stores, said stores being arranged such that, in use, one said store accumulates ATM cells in the current frame and the other said store holds the previously completed frame.

3. A hybrid cross connect as claimed in claim 2, and including a third buffer store to which completed frames are transferred from the corresponding first or second buffer store for subsequent transfer to the ATM switch element.

4. A hybrid cross connect as claimed in claim 1, 2 or 3, wherein said egress interface incorporates means for generating overhead bytes for insertion into said outgoing synchronous frames.

5 A hybrid cross connect as claimed in claim 4, wherein said egress interface incorporates first and second frame assembly buffer stores said stores being arranged such that, in use, one said store accumulates a current synchronous frame and the other said store holds the previously assembled synchronous frame for subsequent transmission to the synchronous network..

6. A hybrid cross connect substantially as described herein with reference to and as shown in the accompanying drawings.

7. A communications system incorporating a hybrid cross connect as claimed in any one of the preceding claims.