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CN1299477C - Method for implementing multiplex line speed ATM interface in multi-layer network exchange - Google Patents

Method for implementing multiplex line speed ATM interface in multi-layer network exchange Download PDF

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CN1299477C
CN1299477C CN 01131663 CN01131663A CN1299477C CN 1299477 C CN1299477 C CN 1299477C CN 01131663 CN01131663 CN 01131663 CN 01131663 A CN01131663 A CN 01131663A CN 1299477 C CN1299477 C CN 1299477C
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multi
implementing
multiplex
exchange
line
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CN 01131663
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CN1428978A (en )
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李锦飞
张磊
徐振
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中兴通讯股份有限公司
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Abstract

本发明涉及一种在多层网络交换机中实现多路线速ATM接口的方法,其中,(1)从SONET/SDH流恢复数据和时钟,提取同步负载封装,并成帧ATM负载;(2)以通道描述符连接信元和工作队列,ATM负载以流水线方式完成ATM SAR和信元/包转发;(3)成帧以太网包,根据MAC地址表或路由表进行IP包的交换和路由。 The present invention relates to a multi-speed ATM line interface in the multilayer network switch, wherein (1) and clock recovery data from SONET / SDH stream, to extract the synchronization load package, framing and ATM load; (2) channel descriptor work queue and the cell is connected, ATM load in a pipelined manner ATM SAR and complete cell / packet forwarding; (3) the Ethernet packet framing, for switching and routing IP packets according to the MAC address table or routing table. 采用本发明所述方法,可在多层网络交换机上实现多通道线速ATM接口的效果,大幅度地提高其性能,同时降低了成本和复杂度。 Using the method of the invention, may be implemented on a multi-channel effect of the multilayer network switch line speed ATM interface, greatly improving performance while reducing cost and complexity.

Description

在多层网络交换机中实现多路线速ATM接口的方法 The method of multi-speed ATM line interface in the multilayer network switch

技术领域 FIELD

本发明涉及多层网络交换机的异步传输模式(以下简称ATM)接口,尤其涉及在多层网络交换机中实现多路线速ATM接口的方法。 The present invention relates to multi-layer network ATM switch (hereinafter referred to as ATM) interfaces, particularly to a multi-speed ATM line interface implemented in a multi-layer network switch.

背景技术 Background technique

网络交换机是因特网从接入层到核心层的连接点和控制点,是整个因特网的重要组成部分,负责IP(互联网协议)包的分组转发。 Network switch is connected to the Internet access point and the control point from the layer to the core layer, is an important part of the Internet, a packet is responsible for IP (Internet Protocol) packet transfer. 正是网络交换机的广泛应用,使因特网具有良好的可扩展性。 It is widely used in network switches, the Internet has good scalability. 而目前大量存在的ATM网,又要求网络交换机必须有ATM接口,以实现ATM网和以太网的互联。 At present, there are a lot of ATM network, but also requires ATM network switch must have an interface to enable ATM network and Ethernet connectivity.

如图1所示,在现有的网络交换机ATM接口卡技术中,ATM物理层器件101通过UTOPIA接口105连接到ATM SAR 102,可高效地完成ATM信元的分拆重装,其中的UTOPIA接口105是ATM通用测试和操作物理接口;之后由通用CPU 104通过软件完成信元/包转发。 1, the conventional network interface card art ATM switches, ATM physical layer device 101 is connected via UTOPIA interface 105 to ATM SAR 102, the ATM cell can be accomplished efficiently split reload, wherein the UTOPIA interface 105 is an ATM universal test and operations physical Interface; by a general purpose CPU 104 after the completion of the software cell / packet forwarding. CPU 104通过PCI总线106与ATM SAR102和交换处理器103连接,从ATM端口接收的信元经PCI总线进入CPU,由CPU处理后再经PCI总线将包送入交换处理器,这样数据包需两次经过PCI总线,同时CPU还要通过微处理器接口107来执行器件读写、网管等多个实时任务,显然这种实现方法的性能在很大程度上取决于PCI总线和CPU的性能。 CPU 104 is connected via a PCI bus 106 and the ATM SAR102 switching processor 103, the received cell from the ATM port into the CPU via the PCI bus, and then processed by the CPU via the PCI bus into packet switching processor, so that packets need two pass of the PCI bus, but also microprocessor CPU interface 107 to perform a plurality of tasks in real-time reading and writing devices, through the network management, performance of the method to achieve this is obviously depends largely on the performance of the PCI bus and the CPU. 目前采用66M的PCI总线和高性能CPU,可实现1路155M ATM的线速接口;如果要实现多路155M ATM线速接口,就要复制多套相同的电路,使用多个独立的PCI总线和高性能CPU。 66M currently used high performance PCI bus and the CPU, channel 1 may be implemented 155M ATM line speed of the interface; if you want to achieve multi-channel line speed 155M ATM interfaces, it is necessary to copy the same circuit sets, a plurality of independent PCI buses and High-performance CPU. 显然现有方法在实现多路线速155M ATM接口时,必将大幅度增加器件数量,增加线卡的复杂度、功耗和成本。 Clearly the conventional method when implementing the multi-speed 155M ATM line interfaces, will dramatically increase the number of devices, increase the complexity, cost and power consumption of the line card.

发明内容 SUMMARY

本发明所解决的技术问题在于,针对现有技术中多层网络交换机技术中ATM信元转发速度慢,在实现多路线速ATM接口时技术复杂、成本高等缺陷,提供一种复杂度及成本都较低的方法,在多层网络交换机中实现多路线速ATM接口。 The technical problem solved by the invention in that, for the prior art multi-layer slow network switch art ATM cell forwarding speed, when the multi-speed ATM line interface technology complex, and high costs, there is provided a complexity and cost are lower method, multi-speed ATM line interfaces in the multilayer network switch.

本发明的基本思想是在ATM接口卡中使用一片或多片网络处理器,利用网络处理器的并行硬件处理引擎和网络优化的处理器,以流水线方式完成ATM SAR和全双工的信元/包转发,在多层网络交换机上实现多路线速ATM接口。 The basic idea of ​​the invention is the use of the ATM interface in one or more pieces of network card processor, a network processor using parallel processing hardware and network optimization engine processor in a pipelined manner to complete cell ATM SAR and the full duplex / packet forwarding, multi-speed ATM line interfaces on the multilayer network switch.

本发明的技术方案主要包括以下步骤:(1)、从SONET(同步光网络)/SDH(同步数字系列)流恢复数据和时钟,提取同步负载封装,并成帧ATM负载;(2)、以通道描述符连接信元和工作队列,ATM负载以流水线方式完成ATM SAR和信元/包转发;(3)成帧以太网包,根据MAC地址表或路由表进行IP包的交换和路由。 Aspect of the present invention includes the following steps: (1), / SDH (Synchronous Digital Hierarchy) stream recovered from SONET (Synchronous Optical Network) and the clock data extracted synchronization load package, framing and ATM load; (2) to channel descriptor work queue and the cell is connected, ATM load in a pipelined manner ATM SAR and complete cell / packet forwarding; (3) the Ethernet packet framing, for switching and routing IP packets according to the MAC address table or routing table.

其中的第(1)步中包括以下3个小步骤:(1-1)、由物理层器件通过串行接口接收SONET/SDH流,恢复数据和时钟;(1-2)、提取携带ATM信元的同步负载封装;(1-3)、利用信元结构成帧ATM负载,由物理层器件的Utopia Level2接口送出。 Wherein (1) comprises the step 3 in small steps of: (1-1), by the physical layer device through the serial interface to receive SONET / SDH stream, data and clock recovery; (1-2), to extract ATM cells carrying membered synchronization load packages; (1-3), using a framing structure of ATM cell load, by the physical layer of the device interfaces Utopia Level2 out.

其中的第(2)步中包括以下8个小步骤:(2-1)、由网络处理器通过Utopia Level 2接口接收信元,建立输入流水线;(2-2)、抽取信元头部,生成通道描述符并通过指针连接信元;(2-3)、把输入事件放入输入事件工作队列,启动输入事件处理线程;(2-4)、输入事件处理线程根据通道描述符建立包头,通过ATM SARDMA(直接存储器存取)将信元转入包队列,并修改通道描述符连接表的尾指针;(2-5)当通道描述符到达通道描述符连接表头部时,处理器建立输出流水线;(2-6)、把输出事件放入输出事件工作队列,激活输出事件处理线程;(2-7)、输出事件处理线程通过包DMA将包输出到SATURN Level 2接口(一种标准的POS-PHY接口,由一个有几十个厂家联合的论坛定义),并更新通道描述符连接表头指针;(2-8)、TSS(The Traffic Scheduling System,业务计划模块)硬件引擎通过当前通道描述符中的参数 Wherein (2) comprises the step 8 small steps: (2-1), by the network processor by Utopia Level 2 interface to receive the cell, establishing an input line; (2-2), extracting the cell header, generation channel descriptor and through a pointer connected to the cell; (2-3), the input event in the input work queue event, start input event processing thread; (2-4), input event processing thread descriptor header according to established channel, when the channel to reach channel descriptor table descriptor header connector, to establish a processor (2-5); by ATM SARDMA (direct memory access) transferred to the cell queue of packets, and modifies the tail pointer descriptor channel connection table output lines; (2-6), the output of the event into the output work queue event, output activation event processing thread; (2-7), an output event is output to the packet processing thread SATURN Level 2 Interface (through a standard packet DMA the POS-PHY interface defined by the forum a combined dozens of manufacturers), and updates the connection path descriptor table pointer; (2-8), TSS (the traffic Scheduling System, service program module) through the current hardware engines channel descriptor parameters ,安排下一信元的传输时间,以保证多通道、多线程的线速处理。 , Arranged next cell transmission time to ensure that the multi-channel, multi-threaded wire-speed processing.

其中的第(3)步中包括以下5个小步骤: Wherein (3) comprises the step 5 small steps:

(3-1)、由交换处理器通过SATURN Level 2接口接收包,识别其所携带的协议类型;(3-2)、加上/去除一些帧头组成一个符合Ethernet(以太网)V.2的包;(3-3)、包被送到2层交换模块,同时将包的MAC(介质存取层)DA(Destination Address,目的地址)与路由表中的MAC DA比较,判断包的MAC DA与路由表中的MAC DA是否相同;(3-4)、如果相同,则将包送到3层路由模块的队列等候路由,路由模块抽取/解析包头,进行必要的处理,根据路由表送到相应的端口和设备;(3-5)、如果不相同,则根据MAC地址表将包送到相应的端口和设备。 (3-1), by the switch processor through the interface to receive packets SATURN Level 2, the protocol type identified it carries; (3-2), plus / removing some of the header line with a composition Ethernet (Ethernet) V.2 packets; MAC DA is compared with the routing table (3-3), the packet is sent to the layer 2 switch module, the packet while MAC (media access layer) DA (Destination address, the destination address), determines the MAC packet the MAC DA DA routing table are the same; (3-4), if the same, then the layer 3 routing packets to be queued routing module, the routing module to extract / parse header, necessary processing, send the routing table to the respective ports and devices; (3-5), if not identical, the MAC address table and the packet to the appropriate port of the device.

采用本发明所述方法,可集成多路ATM接口,同时由于采用了网络处理器,利用网络处理器的并行硬件处理引擎和网络优化的处理器,实现信元/包的流水线处理,可在多层网络交换机上实现多通道线速ATM接口的效果,大幅度地提高其性能。 Using the method of the invention, multiple ATM interface can be integrated, because the use of the network processor, the hardware processing engine and the parallel processor network using the network processor optimized to achieve pipeline processing cell / packet can be a multi- wire-speed multi-channel ATM switch network interface layer effect, greatly improve performance. 本发明与现有技术相比,在实现低速ATM接口时,如155M ATM接口,大幅度的降低了成本和复杂度;在实现高速ATM接口时,如622M ATM接口时,解决了现有技术无法实现的问题。 Compared with the prior art, when low speed ATM interfaces, such as 155M ATM interface, greatly reducing the cost and complexity; in the high-speed ATM interface, such as when 622M ATM interface, the prior art can not solve the implementation issues.

下面将结合附图及实施例对本发明作进一步说明。 The accompanying drawings and the following embodiments of the present invention will be further described.

附图说明 BRIEF DESCRIPTION

图1是现有网络交换机技术中ATM线卡的原理框图;图2是本发明实施例一中ATM线卡的原理框图; FIG 1 is a schematic block diagram of the prior art ATM network switch line card; FIG. 2 is a block diagram of an embodiment of the present invention in the ATM line cards;

图3是本发明实施例二中ATM线卡的原理框图;图4是本发明方法的流程图。 FIG 3 is a block diagram of the ATM line cards according to a second embodiment of the present invention; FIG. 4 is a flowchart of a method of the present invention.

具体实施方式 detailed description

为了实施本发明的方法,需要对图1中所示现有技术中ATM线卡的原理框图作一些改动,主要是在数据通路上使用网络处理器实现ATM SAR和信元/包转发,以网络处理器的Utopia Level 2接口和SATURN Level 2接口取代PCI总线,避免了数据需两次经过PCI总线所形成的瓶颈;以网络处理器的硬件引擎和网络优化的处理器取代高性能CPU,避免了CPU以纯软件方式转发信元/包所形成的瓶颈。 For the method of the present invention, it is necessary to make some changes in the functional block diagram of ATM line card in the prior art shown in FIG. 1 pair, is mainly implemented using a network processor SAR and ATM cell / packet transfer on the data path to network processing Utopia Level 2 and the mouthpiece substituted SATURN Level 2 Interface PCI bus, to avoid a bottleneck of data to be passed twice by the PCI bus is formed; network processor hardware to network optimization engine and a high-performance CPU processor substituted avoided CPU pure software bottlenecks forward the cell / packet is formed. 网络处理器的多通道硬件流水线,可并行处理多个信元/包;其内嵌的网络优化的RISC(精简指令集计算机)处理器,可并行执行多个线程,同时通过智能算法,预先安排下一信元/包的处理时间,分配处理器执行时间,保证多通道、多线程的线速处理。 Multi-channel network processor hardware pipeline, a plurality of parallel processing cells / packets; network optimization of its embedded RISC (reduced instruction set computer) processor, parallel execution of multiple threads, through intelligent algorithm prearranged the processing time of the next cell / packet distribution processor execution time, to ensure multi-channel, multi-threaded wire-speed processing. 如果使用多片网络处理器,可在线卡上同时实现较多的线速ATM接口,如16路155M线速ATM接口、4路622M线速ATM接口,而只需一片CPU对所有器件进行管理。 If a multi-chip network processor on a line card while achieving more wire-speed ATM interfaces, such as line speed 155M ATM interface 16, four wire-speed 622M ATM interface, but only a CPU to manage all devices.

本发明实施例一中ATM线卡的原理框图如图2所示,它可以实现4路155M线速ATM接口。 In a principle embodiment of the ATM line card embodiment of the present invention diagram shown in Figure 2, it can achieve four wire-speed ATM interface 155M. 线路端为单片4路155M ATM物理层器件201,它可进行数据和时钟合成/恢复,以及SONET/SDH处理。 End of the line as a monolithic four 155M ATM physical layer devices 201, which may be data and clock synthesizer / recovery, and SONET / SDH processing. 它通过标准的UTOPIALevel 2接口205连接具有622M全双工处理能力的网络处理器202,UTOPIALevel 2接口提供50M双向16bit位宽且最大为800Mbps的数据流量,可以满足4路155M ATM的要求。 It is connected by a standard UTOPIALevel network interface 205 having two full duplex 622M processor processing capability 202, UTOPIALevel 2 interface provides bidirectional 16bit 50M-bits wide and a maximum of 800Mbps data traffic, to meet the requirements of four 155M ATM. 网络处理器实现ATM SAR,进行信元/包的线速转发,并通过SATURN Level 2接口206连接交换处理器203,实现IP包的交换和路由;SATURN Level 2接口也提供50M双向16bit位宽且最大为800Mbps的数据流量,可以满足4路155M ATM的要求。 Network processors ATM SAR, for cell / wire-speed packet forwarding, and connected by SATURN Level 2 interface 206 switching processor 203, implement switching and routing IP packets; SATURN Level 2 interface is also provided and 50M-bit wide bidirectional 16bit up to 800Mbps of data traffic to meet the 4-way 155M ATM requirements.

同时在ATM接口卡上使用一片CPU 204,连接以上各器件的微处理器接口207,实现器件配置、网管等功能。 Use in an ATM interface card CPU 204, the above device connected to the microprocessor interface 207, while the device configuration, and other network management functions. 由于CPU不需要执行实时转发任务,负担不大,可以选择中低性能CPU。 Since the CPU does not need to perform real-time gateway, the burden is not, you can choose low-performance CPU. 图2中这种基于网络处理器的实现方法,可实现4路155M线速ATM接口。 In this FIG. 2 network processor-based implementation, we can achieve four wire-speed ATM interface 155M.

本发明实施例二中ATM线卡的原理框图如图3所示,它可以实现2路622M线速ATM接口。 In principle ATM line cards according to a second embodiment of the present invention, the diagram shown in Figure 3, it can achieve two-way wire-speed ATM interface 622M. 线路端采用2片单路622M ATM物理层器件301、302,进行数据和时钟合成/恢复,SONET/SDH处理。 End of the line using two single 622M ATM physical layer devices 301 and 302, data and clock synthesizer / recovery, SONET / SDH processing. 它通过标准的UTOPIALevel 2接口308、309分别连接2片具有622M全双工处理能力的网络处理器303、304,UTOPIA Level 2接口提供50M、双向16bit位宽、最大为800Mbps的数据流量,可以满足1路622M ATM的要求;网络处理器实现ATMSAR,进行信元/包的线速转发,并通过SATURN Level 2接口310、311分别连接2片交换处理器305、306,实现IP包的交换和路由;SATURN Level2接口也提供50M、双向16bit位宽、最大为800Mbps的数据流量,可以满足1路622M ATM的要求。 It is connected via standard interfaces 308, 309 UTOPIALevel 2 2 622M full-duplex network processor having processing capability 303,304, UTOPIA Level 2 interface provides 50M, 16bit bit wide bi-directional, up to 800Mbps data traffic, to meet 622M ATM path in claim 1; a network processor to achieve ATMSAR, for cell / wire-speed packet forwarding, and are connected two by switching processor 305, 306, 310, 311 SATURN Level 2 interface to achieve switching and routing IP packets ; SATURN Level2 interface is also provided 50M, two-way 16bit bits wide and up to 800Mbps of data traffic, 622M ATM meet the requirements of a road. 交换处理器之间通过专用的交换结构接口313连接。 Connected by a dedicated switch fabric interface 313 between the switch processor.

同时在ATM接口卡上使用一片CPU307,连接以上各器件的微处理器接口312,实现器件配置、网管等功能,由于CPU不需要执行实时转发任务,负担不大,可以选择中低性能CPU。 While using a card in the ATM interface the CPU 307, the above device connected to the microprocessor interface 312, while the device configuration, network management and other functions, because the CPU does not need to perform real-time forwarding tasks, not burden may be selected low performance CPU. 这种基于网络处理器的实现方法,可实现2路622M线速ATM接口。 Such a network processor-based implementation can be realized two-way wire-speed ATM interface 622M.

本发明的方法的处理流程如图4所示:步骤401、ATM物理层器件通过串行接口接收SONET/SDH流,恢复时钟和数据;步骤402、提取携带ATM信元的同步负载封装;步骤403、利用信元结构成帧ATM负载,由物理层器件的Utopia Level2接口送出;步骤404、网络处理器通过Utopia Level 2接口接收信元,建立输入流水线;步骤405、抽取信元头部,生成通道描述符并通过指针连接信元;步骤406、把输入事件放入输入事件工作队列,启动输入事件处理线程;步骤407、输入事件处理线程根据通道描述符建立包头,通过ATM SARDMA(直接存储器存取)将信元转入包队列,并修改通道描述符连接表的尾指针;步骤408、当通道描述符到达通道描述符连接表头部时,处理器建立输出流水线;步骤409、把输出事件放入输出事件工作队列,激活输出事件处理线程;步骤410、输出事件处理线程通过包DMA将 The processing flow of the method of the present invention shown in Figure 4: Step 401, ATM physical layer devices through the serial interface receives the SONET / SDH stream, clock and data recovery; step 402, extracts the ATM cells carrying synchronous load package; step 403 using a load cell structures framed ATM interface sent by the physical layer of the device Utopia Level2; step 404, the network processor by Utopia Level 2 interface to receive the cell, establishing an input line; step 405, the cell header extraction, generation channels and connected by a pointer descriptor cell; step 406, the event input event in the input work queue, input event processing thread starts; step 407, input event processing thread descriptors established depending on the channel header, the ATM SARDMA (direct memory access ) packet queue into the cell, and the tail pointer modify connection channel descriptor tables; step 408, when the channel reaches the channel descriptor table descriptor connector head, to create output processor pipeline; step 409, the output of the discharge events the work output event queue, an output activation event processing thread; step 410, the thread event handling by the packet DMA 包输出到SATURN Level 2接口,并更新通道描述符连接表头指针;步骤411、TSS硬件引擎通过当前通道描述符中的参数,安排下一信元的传输时间,以保证多通道、多线程的线速处理; SATURN Level 2 packet is output to the interface, and updates the connection path descriptor table pointer; step 411, TSS hardware engines the current channel descriptor parameters, arranged next cell transmission time to ensure that the multi-channel, multi-threaded wire-speed processing;

步骤412、交换处理器通过SATURN Level 2接口接收包,识别其所携带的协议类型;步骤413、加上/去除一些帧头组成一个符合Ethernet V.2的包;步骤414、包被送到2层交换模块,同时将包的MAC DA与路由表中的MAC DA比较,判断包的MAC DA与路由表中的MAC DA是否相同;步骤415、如果相同,则将包送到3层路由模块的队列等候路由,路由模块抽取/解析包头,进行必要的处理,根据路由表送到相应的端口和设备;步骤416、如果不相同,则根据MAC地址表将包送到相应的端口和设备。 Step 412, switch processor through the interface to receive packets SATURN Level 2, the protocol type identified carries; step 413, plus / removing some of the header line with a composition Ethernet V.2 packet; step 414, the packet is sent to 2 layer switching module while the packet MAC DA and MAC DA in the routing table, and determines the packet MAC DA MAC DA in the routing table are the same; step 415, if the same, then the packet is sent to the layer 3 routing module be queued routing, routing module to extract / parse header, the necessary processing apparatus and to the corresponding port according to the routing table; step 416, if not identical, the MAC address table and the packet to the appropriate port of the device.

从上述实施例中可以看出,本发明可集成多路ATM接口,同时由于采用了网络处理器,利用网络处理器的并行硬件处理引擎和网络优化的处理器,在多层网络交换机上实现了多路线速ATM接口。 As can be seen from the above examples, the present invention may be integrated multiple ATM interface, because the use of the network processor, a network processor using parallel processing hardware and network optimization engine processor, implemented in a multi-layer network switch multi-speed ATM line interface. 本发明的方法实施简单,成本低,可大幅度地提高ATM接口的性能。 Method of the present invention is simple, low cost, can greatly improve the performance of the ATM interface.

Claims (2)

1.一种在多层网络交换机中实现多路线速ATM接口的方法,其特征在于,包括以下步骤:(1)、从SONET/SDH流恢复数据和时钟,提取同步负载封装,并成帧ATM负载,由ATM物理层器件的Utopia Level 2接口输出;(2)、以通道描述符连接信元和工作队列,ATM负载以流水线方式完成ATM SAR和信元/包转发,具体过程为:由网络处理器通过Utopia Level 2接口接收由所述ATM物理层所输出的信元,建立输入流水线;抽取信元头部,生成通道描述符并通过指针连接信元;把输入事件放入输入事件工作队列,启动输入事件处理线程;输入事件处理线程根据通道描述符建立包头,通过ATM SAR DMA将信元转入包队列,并修改通道描述符连接表的尾指针;当通道描述符到达通道描述符连接表头部时,处理器建立输出流水线;把输出事件放入输出事件工作队列,激活输出事件处理线程;输出事件 1. A method implemented in a multi-layer network switch multi-speed ATM line interface, characterized by comprising the steps of: (1), and clock recovery data from SONET / SDH stream, to extract the synchronization load package, framing and ATM load, the ATM physical layer devices Utopia Level 2 interface output; (2) to the channel descriptors connected cells and work queues, ATM load pipelining complete ATM SAR and cell / packet forwarding, the specific process is: a network processing by Utopia Level 2 interface receives the ATM cell from the physical layer output, establishing the input lines; extraction cell header, and generates the channel descriptor pointer is connected via the cell; an input event in the input work queue event, start input event processing thread; channel according to an input event processing thread descriptor header established by the ATM SAR DMA packet queue into the cell, and the tail pointer modify connection channel descriptor tables; when the channel to reach channel descriptor table descriptor connector the head, the output processor build a pipeline; the output events into work output event queue, activate the output event processing thread; output event 处理线程通过包DMA将包输出到SATURN Level 2接口,并更新通道描述符连接表头指针;TSS硬件引擎通过当前通道描述符中的参数,安排下一信元的传输时间,以保证多通道、多线程的线速处理;(3)、成帧以太网包,根据MAC地址表或路由表进行IP包的交换和路由。 Processing thread to the packet output by the packet DMA interfaces SATURN Level 2, and updates the connection path descriptor table pointer; hardware engine through the TSS descriptor parameter of the current channel, the scheduled transmission time of the next cell, to ensure multi-channel, wire-speed multi-threaded process; (3), an Ethernet packet framing, for switching and routing IP packets according to the MAC address table or routing table.
2.根据权利要求1所述的在多层网络交换机中实现多路线速ATM接口的方法,其特征在于,在所述第(3)步中:由交换处理器通过SATURN Level 2接口接收包,识别其所携带的协议类型;加上/去除一些帧头组成一个符合以太网V.2的包;包被送到2层交换模块,同时将包的MAC DA与路由表中的MAC DA比较,判断包的MAC DA与路由表中的MAC DA是否相同;如果相同,则将包送到3层路由模块的队列等候路由,路由模块抽取/解析包头,进行必要的处理,根据路由表送到相应的端口和设备;如果不相同则根据MAC地址表将包送到相应的端口和设备。 2. Multi-speed ATM line interface implemented in a multi-layer network switch according to claim 1, wherein, in the (3) step: by the switching processor SATURN Level 2 interface to receive packets through, identifying the protocol type which it is carried; add / remove some of the Ethernet header consisting of a line with V.2 packet; packet is sent to the layer 2 switching module while the MAC DA of the packet is compared with the MAC DA in the routing table, MAC DA is the same as the MAC DA determines packet routing table; if the same, then the layer 3 routing packets to be queued routing module, the routing module to extract / parse header, necessary processing, according to the corresponding routing table ports and devices; if not identical to the MAC address table and the packet to the appropriate port of the device.
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