KR960001058B1 - Interface unit of atm cell assembler and 32bit unit communication - Google Patents

Abstract

a pre-input/output buffer operated by the 9 bit for a connection between an ATM cell assembly and a module, the ATM cell assembly being used for performing an operation process of the bit unit; an ATM cell read signal generator for outputting a signal for reading an ATM cell to the pre-input/output buffer under provision with an output value from the counter; a unit converter for outputting a 32-bit data write signal, a unit conversion output signal, and a 32-bit output signal through inputs of the programmable almost empty signal from the pre-input/output buffer and the ATM cell read signal from the ATM cell read signal generator; first to fourth D flip-flops for outputting output data by 8 bit through inputs of the unit conversion output signal and the reset signal; a fifth D flip-flop for outputting data of 32 bit through inputs of the output data of 32 bit and the reset signal from outside; and a sixth flip-flop for outputting a start signal of 32 bit under input of an ATM cell output start signal from the pre-input/output buffer.

Description

Interface device between AT cell assembler and 32-bit unit communication module

1 is a block diagram of an interface device between an ATM cell assembler and a 32-unit communication module to which the present invention is applied.

2 is a block diagram of an interface device according to the present invention.

3 is an operation timing diagram of an interface device according to the present invention.

* Explanation of symbols for main parts of the drawings

21: first-in, first-out part 22: counter circuit

23 unit conversion circuit 24 ATM cell read signal generation circuit

25 to 30: D flip-flop

The present invention provides a connection between an ATM cell assembler performing byte-based operation processing based on a 53 octet ATM (Asynchronous Transfer Mode) cell and a module performing 32-bit unit operation based on a 56-octet module communication cell. It relates to an interface device for.

The conventional technology has a problem that the transmission rate is limited to about 250 Mpps by processing the data transmission clock at about 30 MHz and processing in 8 bit units.

In order to solve the problems of the prior art, the present invention, the data transmission clock operates at 31.25MHz, but the processing speed is improved to 1Gbps by processing in 32-bit units instead of 8-bit units, the data transfer rate is increased by 4 times compared to the prior art. It provides an interface device for accessing an ATM cell assembler that performs byte-based operation processing based on 53-octet ATM cells and a module that performs 32-bit unit operation processing based on a 56-octet module communication cell. Its purpose is.

In order to achieve the above object, the present invention relates to an ATM cell assembler performing a byte-based operation process based on a 53-octet ATM cell and a module performing a 32-bit unit operation based on a 56-octet module communication cell. First-in, first-out means operating in 9-bit units for connection, Counting means for receiving a programmable maximum empty signal from the first-in, first-out means, receiving a system clock and a reset signal externally, and outputting a 53-definition counter value, The system clock A signal for reading an ATM cell in 53 octets in response to a count output value from the counting means and outputting to the first-in, first-out means; Receives the ATM cell read signal from the ATM cell read signal generator; A unit conversion means for receiving a 32-bit data write signal, a unit conversion output signal and a 32-bit output signal, and a unit conversion output signal from the unit conversion means, and receiving ATM cell output data from the first-in first-out means (7 to 7). 0 to 4D flip-flops for receiving 8-bit output data 31 to 0 and receiving reset signals from the outside, respectively, and 32-bit output data from the first to 4D flip-flops. A 5D flip-flop that receives a 32-bit output signal from the unit converting means, receives a reset signal from the outside, and outputs 32-bit data; and 32-bit data receiving an ATM cell output start signal from the first-in, first-out means. And a sixth flip flop for outputting a start signal.

The upper three octets of the module communication cell are used for frame synchronization associated with physical medium access of the physical layer, and the remaining 53 octets are mapped to the ATM cell. In addition, this interface device generates 32-bit data start signal and 32-bit data write signal together with 32-bit data to accurately transfer 53-octet ATM cell to 32-bit unit communication module.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a system connection diagram to which the present invention is applied, in which 1 represents an ATM cell assembler, 2 represents an interface device of the present invention, and 3 represents a 32-bit unit module.

As shown in the figure, in the system configuration to which the present invention is applied, the ATM cell assembler 1 provides an ATM cell start signal, an ATM cell input data 7 to 0 in bytes, and an ATM cell write signal according to the present invention. (2), the interface device (2) between the ATM cell assembler and the 32-bit unit communication module (3) receives these signals and converts the ATM cell start signal into a 32-bit data start signal, and converts the ATM cell into bytes. The input data 7 to 0 are converted into 32-bit data 31 to 0, and the ATM cell write signal is converted into a 32-bit data write signal and transmitted to the 32-bit unit communication module 3.

2 is a configuration diagram of an interface device according to the present invention, and FIG. 3 is an operation timing diagram of the interface device according to the present invention. In FIG. 23 represents a unit conversion circuit, 24 represents an ATM cell weather signal generation circuit, and 25 to 30 represent D flip-flops, respectively.

As shown in the figure, the interface apparatus of the present invention synchronizes the ATM cell clock with the ATM cell clock while the ATM cell write signal is TTL level 0, making the ATM cell start signal the most significant bit, and assigns the ATM cell input data 7 to 0 to the lower eight. The N-bit unit is stored in the 9-bit parallel sync FIFO 21, and the 9-bit parallel sync FIFO 21 also includes a programmable Almost Empty signal to store ATM cell input data. If more than one octet is stored, it is output as TTL level 0 to 1 (as shown in FIG. 3 (a)). If the programmable maximum empty signal is TTL level 1, the counter circuit 22 starts counting in synchronization with the system clock (FIG. 3 (b)) as shown in FIG. 3 (c), and the counter output value is 1 to 58. Incremented to 0 and reinitialized to zero.

The ATM cell read signal generation circuit 24 continuously generates an ATM cell read signal (Fig. 3 (d)) to TTL level 0 while the counter output value is increased from 1 to 53. By this signal, the ATM cell output start signal (FIG. 3 (e)) and ATM cell output data (7 to 0) stored in the 9-bit unit synchronous FIFO 21 are synchronized to the system clock to a size of 53 octets. Read it.

The unit conversion circuit 23 starts operation when the programmable maximum empty signal is TTL level 1, and then output signal 3 (g), output signal 2 (h), output signal 1 (i), and output signal o as shown in FIG. (j) Generates a 32-bit output signal and a 32-bit data write signal and initializes the generated signals by detecting that the ATM cell read signal is converted from TTL level 0 to 1 (the counter output value becomes 54).

The D flip flop 25 is composed of eight D flip flops, and the output data 3 (g) is used to output the D flip flop output data 31 to 24 (k). … Latches the 50th (increment of 4) octets sequentially.

The D flip flop 26 is composed of eight D flip flops, and the output of the D flip flop output data 23 to 16 (l) using the output signal 2 (h) is 3, of the ATM cell output data (7 to 0). 7,... The 51th (increment of 4) octets are latched sequentially.

The D flip-flop 28 is composed of eight D flip-flops, and the output of the D-flop flop output data (7 to 0) (n) using the output signal o (j) is 1, 1 of the ATM cell output data (7 to 0). 5,… The 53th (increment of 4) octets are latched sequentially.

The D flip-flop 30 is composed of 32 D flip-flops, and the 32-bit output signal o of the unit conversion circuit 23 is input by inputting the D flip-flop output data 31 to 0 latched as shown in FIG. After outputting 32-bit data (31 ~ 0), add the most significant 3 octets to 53-octet ATM cell input data (7 ~ 0) in bytes, and 56-octet 32-bit in 32-bit units. The first three octets are converted to data 31 to 0, and are used for frame synchronization associated with the physical layer connection of the physical layer. The data values are irrelevant.

The D flip-flop 29 is composed of one D flip-flop and receives an ATM cell output start signal as an input as shown in FIG. 3 (e), and uses a 32-bit output signal (o) as a 32-bit data start signal ( generates p). This signal indicates the start of 32-bit data 31 to 0 and is a signal for correctly transmitting a 53-octet ATM cell to a 32-bit unit of communication module. The unit conversion circuit 23 generates a 23-bit data write signal r so that the 32-bit unit communication module 3 uses this signal to form the 32-bit data start signal p and the 32-bit data. Make sure to read (31 ~ 0) (q) correctly.

In Figure 3, 0 through 58 of note 1 are decimal numbers, and 1 through 53 of note 2 represent the first to 53th octet data.

As described above, the present invention relates to a cell assembler corresponding to an ATM layer transmission function processing unit in a subscriber access network of an ATM based broadband integrated telecommunication network, and a high speed physical medium access unit and shared medium access unit of 155 Mbps, 622 Mbps, or Gbps. Can be used as an interface device.

Claims (1)

Preemptive operation of 9-bit unit for connection between ATM cell assembler performing byte-based operation processing based on 53-octet ATM cell and module performing 32-bit operation processing based on 56-octet module communication cell Counting means 22 for receiving a programmable maximum empty signal from the first-in first-out buffer means 21 and the first-in first-out buffer means 21 and receiving a system clock and a reset signal from the outside, and outputting a 53-degree counter value. ATM cell read signal generation means 24 for receiving the count output value from the count means 22 and outputting the signal to the first-in, first-out buffer means 21 in synchronization with a clock to read an ATM cell with a size of 53 octets. The ATM cell read signal from the ATM cell read signal generator 24 receives the programmable maximum empty signal from the selection buffer means 21. A unit conversion means 23 for receiving a 32-bit data write signal, a unit conversion output signal and a 32-bit output signal, and a unit conversion output signal from the unit conversion means 23 and receiving the first-in, first-out buffer means 21. First to fourth 4D flip-flops 25 to 28 that receive ATM cell output data 7 to 0, respectively, and receive a reset signal from the outside, and output 8 bits of output data 31 to 0; 32-bit output data from the first to fourth 4D flip-flops 25 to 28, 32-bit output signal from the unit converting means 23 and a reset signal from the outside to output 32-bit data And a 6D flip flop (29) for receiving the ATM cell output start signal from the first-in, first-out buffer means (21) and outputting a 32-bit data start signal. Cell Interface device between the assembler and the 32-bit unit of the communication module.