KR960002688B1 - Module communication transmitter of dual-ring structure - Google Patents

Abstract

a self cell transmitting unit for storing a 8-bit unit of self cell input data in its own first-in first-out to read the data in 53 octet unit, for adding 3 octet header to the read data to convert the data in 32-bit unit, for outputting a self cell transmitting data starting signal with the converted data, and for checking whether the data is transmitted to any of first and second rings to thereby generate first and second rings self cell transmitting data writing signal; an alternate cell transmitting unit for storing a 32-bit unit of alternate cell input data in its own first-in first-out to read the data in 14 longword unit, for outputting an alternate cell transmitting data starting signal with the read data, and for checking whether the data is transmitted to any of the first and second rings to thereby generate first and second rings alternate cell transmitting data writing signal; and a signal arbitrating unit for arbitrating output signals from the self cell transmitting unit and output signals from the alternate cell transmitting unit, for outputting the first ring transmitting data starting signal, the first ring transmitting data writing signal to the first ring, if the output signals correspond to the first ring, and for outputting the second ring transmitting data starting signal, the second ring transmitting data writing signal to the second ring, if the output signals correspond to the second ring.

Description

Transmission device for module communication under double ring structure

1 is an overall block diagram of a transmission device for module communication under a double ring structure according to the present invention.

2 is a block diagram of a magnetic cell transmitter according to the present invention.

3 is a block diagram of a bypass cell transmitter according to the present invention.

* Explanation of symbols for main parts of the drawings

1-1: magnetic cell transmitter 1-2: bypass cell transmitter

1-3: Signal Arbitration Unit

The present invention relates to a transmission device for connecting the same functional modules by two rings according to the dead-network interface standard of the broadband integrated telecommunications network recommended by CCITT, an international standard organization.

The present invention operates in 56-octet module communication cell units defined by 4-octet headers and 52-octet payloads for inter-module communication, and internally processes 32-bit units internally. Such a module communication function is performed under the ATM (Asynchronous Transfer Mode) layer of the protocol reference model of the broadband integrated information network user-network interface. Basically, it consists of a transmitter and a receiver, each connected to two physical transmission media. The transmission directions of the two transmission media are opposite to each other and form a ring.

The transmitter corresponding to the present invention receives 8-bit unit cells of various characteristics and 32-bit unit bypass cells of different destinations received from two rings, and selects one of two rings using different FIFOs. Transmit data on two rings.

However, the transmission device for such module communication reduces the data processing time for processing the input magnetic cell and the bypass cell independently and the waiting time in the FIFO to a minimum, and in particular, the transmission of the bypass cell is preferentially processed over the magnetic cell. It is desired to keep the cell propagation delay to a minimum.

Accordingly, the present invention reduces the data processing time for processing the inputted self cell and the bypass cell independently and the waiting time in the FIFO to a minimum, and in particular, prioritizes the transmission of the bypass cell over the magnetic cell to reduce the cell propagation delay on the ring. It is an object of the present invention to provide a transmission apparatus that is kept to a minimum.

In order to achieve the above object, the present invention stores 8-bit magnetic cell input data in its own FIFO, reads it in 53 octets, adds 8 octets of headers, and converts it into 32-bit units. The magnetism generating the first and second ring magnetic cell transmission data write signals by outputting the transmission data start signal and confirming which of the first and second rings is the transmission data in the two rings opposite to each other. Save the 32-bit bypass cell input data from the cell transmitter and the receiver in its FIFO, read it in 14 long words (56 octets), and start the bypass cell transmission data with 32-bit data. Bypass cell transmission means for outputting a signal and checking which of the first and second rings is transmission data in two rings and generating first and second ring bypass cell transmission data write signals; And receiving and arbitrating the output signals of the magnetic cell transmitter and the output signals of the bypass cell transmitter, the first ring transmission data start signal, the first ring transmission data, and the first ring to the first ring if the signal is related to the first ring. And a signal mediation means for outputting a transmission data write signal and transmitting a ring transmission data start signal, a ring 2 transmission data, and a ring 2 transmission data write signal to the second ring if the signal relates to the second ring.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is an overall block diagram of the present invention, in which 1-1 represents a magnetic cell transmitter, 1-2 represents a bypass cell transmitter, and 1-3 represents a signal arbitration unit, respectively.

Referring to the drawings, the operation of the transmitter according to the present invention will be described in detail. The magnetic cell transmitter 1-1 may include a magnetic cell start signal synchronized with the magnetic cell clock (19.44 MHz) while the magnetic cell write signal is TTL level 0. FIG. Stores 8-bit magnetic cell input data in its own FIFO. If the magnetic cell stored in the FIFO is 53 or more octets and the empty signal from the bypass cell transmitter 1-2 is an empty state and the bypass cell transmitter 1-2 is not in operation, the magnetic field is 53 octets. After reading the cell in synchronization with the system clock (62.5MHz), convert the unit into 32-bit units by attaching the top 3 octets of headers for frame synchronization related to physical media connection of the physical layer, and then convert it into 14 long words (56 octets). The magnetic cell transmission data is output together with the magnetic cell transmission data start signal.

Then, it checks whether the specific data bit of the first octet of the 8-bit unit 53 octets is 0 or 1, and if it is 0, outputs the ring 1 magnetic cell transmission data write signal, and if 1, the ring 2 magnetic cell transmission data write signal Outputs In addition, the self-cell transmitting unit in operation signal is output to the bypass cell transmitting unit 1-2 as a status signal. The self-cell transmitting unit outputs the signal to the TTL level 0 when it is in operation and to the TTL level 1 when it is not in operation.

The bypass cell transmitter 1-2 transmits the bypass cell start signal synchronized with the 4th clock of the system clock (15.62MHz) and the bypass cell input data in 32-bit units while the bypass cell write signal is TTL level 0. Store in

If the bypass cell stored in the FIFO is longer than 1 long word and the self-cell transmitter 1-1 is not in operation, it is read in 14 long words (56 octets) in synchronization with the 4 division clock of the system clock. The bypass cell transmission data in bit units is outputted with the bypass cell transmission data start signal. Then, it checks whether a specific data bit of the first long word is 0 or 1 out of the 14 long words of the bypass cell, and if it is 0, outputs a ring 1 bypass cell transmission data write signal, and if 1, outputs a ring 2 backward cell transmission data write signal. .

In addition, the self-cell transmitting unit 1-1 outputs a bypass cell transmitting unit operation signal as a state signal, and outputs the signal to the TTL level 0 when the internal cell is in operation, and to the TTL level 1 when the internal cell is in operation. In addition, an empty signal is output to the magnetic cell transmitter 1-1. If the bypass cell signal in the FIFO is empty, the signal is output at TTL level 0, and at least one long word is output at TTL level 1.

The signal mediator 1-3 has output signals and the bypass cell transmitter 1 of the magnetic cell transmitter 1-1 because only one of the magnetic cell transmitter 1-1 and the bypass cell transmitter 1-2 is always in operation. -2) outputs the signal of ring 1 to the ring 1 and outputs the ring 1 transmission data start signal and the ring 1 transmission data and the ring 1 transmission data writing signal to the ring 1 side, and the signal to the ring 2 side of the ring 2 signal. 2 Outputs the transmission data start signal, ring 2 transmission data, and ring 2 transmission data writing signal.

The self-cell transmitter 1-1 outputs an in-operation signal and the bypass cell transmitter 1-2 outputs an empty signal and an in-operation signal as status signals. Is operated, and the data stored in the FIFO of the bypass cell transmitter 1-2 is preferentially transmitted over the data stored in the FIFO of the magnetic cell transmitter 1-1.

2 is a detailed configuration diagram of the magnetic cell transmitter 1-1 according to the present invention, in which 2-1 is a 9-bit parallel synchronous FIFO, 2-2 is a counter circuit, and 2-3 is a unit conversion and magnetic cell. The control signal generating circuit, 2-4 denotes a magnetic cell read signal generating circuit, 2-5 denotes a D flip-flop unit, and 2-6 denotes a ring select circuit.

The 9-bit unit synchronous FIFO 2-1 receives a system clock and a reset signal, and receives a magnetic cell start signal and magnetic cell input data in synchronization with the magnetic cell clock according to the magnetic cell write signal. In addition, when the magnetic cell read signal is applied, the magnetic cell output start signal and the magnetic cell output data are output, and a programmable Almost Empty signal is separately embedded. The signal stores more than 53 octets of the magnetic cell input data. Is output from TTL level 0 to 1.

The counter circuit 2-2 receives a system clock and a reset signal, receives an empty signal and a bypass cell transmitter operation signal from the bypass cell transmitter 1-2, and the 9-bit unit synchronous FIFO 2-1. The programmable maximum empty signal is inputted from the TEL level 1, the empty signal of the bypass cell transmitter 1-2 is empty, and the bypass cell transmitter operation signal is in operation. If not, the counter starts synchronizing with the system clock, and the counter output value is increased from 1 to 58 and then reset to zero.

The magnetic cell read signal generation circuit 2-4 receives a reset signal and the counter output value of the counter signal 2-2. The magnetic cell read signal generation signal is continuously applied to the TTL level 0 while the counter output value is increased from 1 to 53. Occurs as By this signal, the magnetic cell start signal and the magnetic cell input data stored in the 9-bit unit synchronous FIFO 2-1 are read in 53 octets in synchronization with the system clock.

The unit conversion and magnetic cell control signal generation circuit 2-3 receives the system clock and the reset signal, the empty signal from the bypass cell transmitter 1-2, and the bypass cell transmitter operating signal. A programmable maximum empty signal is received from the unit parallel synchronization FIFO 2-1, and a magnetic cell read signal is received from the magnetic cell read signal generation circuit 2-4. If the programmable maximum empty signal is TTL level 1 (53 octets or more) and the empty signal of the bypass cell transmitting unit 1-2 is empty and the busy signal is not active, the operation is started. Output signal 0 to output signal 3 and 32-bit output signal for bit unit conversion are generated and transmitted to DF / F (2-5). Then, the self-cell transmitter transmits the operation signal to the bypass cell transmitter 1-2, indicating that it is in operation, and outputs a 32-bit data write signal, a ring select signal, and an interval signal.

The D flip-flop unit 2-5 is composed of 65 D flip-flops, and includes a reset signal, a 9-bit unit parallel synchronous FIFO 2-1, a unit conversion and magnetic cell control signal generation circuit 2-3. A frame related to the connection of a physical medium of a physical layer to a magnetic cell by receiving 53 octets of data (magnetic cell output start signal, magnetic cell output data) and signals (output signals 0 to 3 and 32-bit output signals) from the For synchronization, the uppermost three octets of headers are attached to 56 octets in 32-bit units, irrespective of the data value, and 32-bit magnetic cell transmission data and magnetic cell transmission data start signal are output. Here, the self-cell transmission data start signal is a signal in which the self-cell transmission data is maintained at the TTL level 1 only during the first long word period and at the TTL level 0 during the other period.

The ring select circuit 2-6 is a unit conversion and magnetic cell control signal generation circuit 2-3 and the 9-bit unit parallel synchronous FIFO (2-) together with the 32-bit data write signal, ring select signal, and section signal. 1) Input the magnetic cell output data from 1) and check if the characteristic data bit of the first octet of the 53 octets of magnetic cell output data is 0 or 1, and if it is 0, it outputs the ring 1 magnetic cell transmission data write signal, and if it is 1, the ring 2 magnetic Outputs the cell transmit data write signal.

3 is a detailed configuration diagram of the bypass cell transmitter 1-2, in which 3-1 is a four-dividing circuit, 3-2 is a 33-bit unit parallel synchronization FIFO, 3-3 is a counter circuit, and 3-4 is a bypass. Cell control signal generation circuits, 3-5 denote bypass cell read signal generation circuits, 3-6 denote D flip-flop units, and 3-7 denote ring selection circuits, respectively.

The four division circuit 3-1 receives the system clock and the reset circuit and divides the system clock (62.5 MHz) into four to generate a four division clock (15.625 MHz).

The 33-bit unit synchronous FIFO 3-2 receives the bypass cell start signal and the bypass cell output data according to the input of the bypass cell write signal, and inputs the 4 division clock which is the output of the 4 division circuit 3-1. If the empty cell signal is embedded and the bypass cell input data is stored more than one long word, it is output as TTL level 0 to 1.

The counter circuit 3-3 includes a reset signal, a signal in operation of the magnetic cell transmitter, a quadrature clock attached to the quadrature circuit 3-1, and an amplifier from the 33-bit unit parallel synchronous FIFO 3-2. When the empty signal is received and indicates that the empty signal is TTL level 1 and the signal during operation of the magnetic cell transmitter is not in operation, the counter operation is started in synchronization with the input four-division clock and the counter output value is increased from 1 to 14. It is reinitialized to zero.

The bypass cell read signal generation circuit 3-5 receives the counter output value as an input and continuously generates the bypass cell read signal to the TTL level 0 while the counter output value is increased from 1 to 14. By this signal, the bypass cell input data stored in the 33-bit unit parallel sync FIFO (3-2) is read in 14 long words (56 octets) in synchronization with the 4th division clock and is used as the bypass cell output start number and bypass cell output data. Is output.

The bypass cell control signal generation circuit 3-4 receives a four-division clock and a reset circuit, receives an empty signal from the 33-bit unit synchronous FIFO 3-2, and transmits a magnetic cell transmitter 1-1. Receives the active signal from the magnetic cell transmitter. If the empty signal is TTL level 1 and the signal in operation of the magnetic cell transmitter indicates that the magnetic cell transmitter 1-1 is not in operation, a 32-bit output signal is generated and transmitted to the D flip-flop unit. In addition, the bypass cell transmitter transmits a signal in operation to the magnetic cell transmitter 1-1, indicating that the operation is in progress, and outputs a 32-bit data write signal, a ring select signal, and an interval signal to the ring select circuit 3-7.

The D flip-flop section 3-6 includes 33 D flip-flops and contains 14 long words of data from the 33-bit unit parallel synchronous FIFO 3-2 and the bypass cell control signal generation circuit 3-4. It receives the (bypass cell output start signal, bypass cell output data) and signals (32-bit output signal, reset signal) and outputs bypass cell transmission data and bypass cell transmission data start signal in 32-bit units. The bypass cell transmission data start signal is a signal that maintains the TTL level 1 only while the bypass cell transmission data is the first long word period and maintains the TTL level 0 during the other period.

The ring select circuit 3-7 receives the 32-bit data write signal, the ring select signal, and the interval signal, and receives the bypass cell output data to determine whether a specific data bit of the first long word of the bypass cell output data is 0 or 1. If 0 is checked, the ring 1 bypass cell transmission data write signal is output, and if 1, the ring 2 bypass cell transmission data write signal is output.

Accordingly, the present invention constructed and operated as described above provides high-speed communication between unit modules constituting a large capacity subscriber access node located at a user-network interface of a broadband integrated information communication network or between subscriber access nodes distributed within a large distance. It can be used to provide high-speed communication service in the public network or private network area based on ATM, and can be applied to transmission apparatus such as centralized subscriber access node, ATM local area network or ATM-Gigabit LAN.

Claims (3)

After storing 8-bit self-cell input data in its own FIFO, read it in 53-octet unit, convert it into 32-bit unit by attaching 3-octet header, and output the self-cell transmission data start signal together with the data, and vice versa. Magnetic cell transmission means (2-1) for generating the first and second ring magnetic cell transmission data write signals by checking which of the first and first rings is the transmission data in the two rings in the direction; After saving the 32-bit bypass cell input data from the receiver in its own FIFO, read it in 14 long words (53 octets) and output the bypass cell transmission data start signal together with the data in 32-bit units. Bypass cell transmitting means (2-2) for generating a first ring and second ring bypass cell transmission data write signal by checking which of the first ring and the second ring is transmitted to two rings, and the magnetic field. Outgoing Cell Transmitter 2-1 Receives the signals and output signals of the bypass cell transmitter 2-2 as input and mediates the first ring transmission data and the first ring transmission data and the first ring transmission data to the first ring if the signal is related to the first ring. And a signal mediation means (2-3) for outputting a write signal and transmitting a ring transmission data start signal, a ring 2 transmission data, and a ring 2 transmission data write signal to the second ring if the signal is related to the second ring. A transmitter for performing module communication. The magnetic cell transmitting means (1-1) receives a system clock and a reset signal, and the magnetic cell start signal and the magnetic cell input data are synchronized with the magnetic cell clock according to the input of the magnetic cell write signal. Programmable Almost Empty is received and outputs the magnetic cell output start signal and the magnetic cell output data as the magnetic cell read signal is applied. A 9-bit unit synchronous FIFO (2-1) having a built-in signal, a system clock and a reset signal are input, and an empty signal and a bypass cell transmitter operation signal are input from the bypass cell transmitter (1-2). The programmable maximum empty signal is received from the bit-wise parallel synchronization FIFO (2-1), and the programmable empty empty signal is TTL level 1, and the empty signal of the bypass cell transmitter is empty. When the detour cell transmitter operation signal is not in operation, the counter circuit (2-2) and the reset signal and the counter output value of the counter circuit (2-2) are started in synchronization with the system clock. While the counter output value is increased, the self-cell read signal is continuously output to the 9-bit unit parallel sync FIFO (2-2), and the stored read signal is output to the 9-bit unit parallel sync FIFO (2-1). The magnetic cell read signal generation circuit 2-4 which causes the stored magnetic cell start signal and the magnetic cell input data to be read in synchronization with the system clock, the system clock and reset signal, and empty from the bypass cell transmitter 1-2. A signal and a bypass cell transmitter operation signal are input, a programmable maximum empty signal is input from the 9-bit unit synchronous FIFO 2-1, and the magnetic cell is read from the magnetic cell read signal generation circuit 2-4. Read signal is input If the logramable maximum empty signal is TTL level 1 (53 octets) and the empty signal of the bypass cell transmitting unit 1-2 is empty and the busy signal is not in operation, the operation is started. Generates output signal and 32-bit output signal for bit unit conversion, and transmits the signal of the self-cell transmitter to the bypass cell transmitter (1-2) to indicate that it is in operation. 32-bit data write signal, ring selection Unit conversion and magnetic cell control signal generation circuits 2-3 for outputting signals and section signals, reset signals, 9-bit unit parallel synchronous FIFOs 2-1, unit conversion and magnetic cell control signal generation circuits ( From 2-3) magnetic cell output data of 53 octets, magnetic cell output start signal and output signal for 32-bit unit conversion are inputted, and it is suitable for frame synchronization related to physical media connection of physical layer to magnetic cell. 3 octets of headers regardless of data value And a ring selection circuit (2-6) for converting the data into a 56-octet size in bits and outputting 32-bit units of magnetic cell transmission data and a magnetic cell transmission data start signal. Device. The quadrature divider circuit (3) according to claim 1, wherein the receiving means (1-2) receives a system clock and a reset circuit and divides the system clock (62.5 MHz) into four to generate a four-division clock (15.625 MHz). 1), the bypass cell start signal and the bypass cell output data are input according to the input of the bypass cell write signal, and the 4 division clock, which is the output of the 4 divide circuit 3-1, is input, and an empty signal is separately installed. When the bypass cell input data is stored in one or more long words, a 33-bit unit parallel synchronous FIFO (3-2) outputs from TTL level 0 to 1, a reset signal, a signal in operation of the magnetic cell transmitter, and the four divider circuit ( 4-1) and the empty signal from the 33-bit unit synchronous FIFO (3-2), the empty signal is TTL level 1, and the self-cell transmitter is in operation. If not, the counter circuit (3-3) for performing the count in synchronization with the input divided clock; Bypass cell read signal generation circuit 3 which receives the output value of the counter circuit 3-3 as an input and continuously outputs the bypass cell read signal to the 33-bit unit parallel synchronous FIFO 3-2 while the counter output value is increased. -5), a 4-division clock and a reset circuit are input, an empty signal is input from the 33-bit unit synchronous FIFO 3-2, and the magnetic cell transmitter from the magnetic cell transmitter 1-1 is operated. When the signal is received and the empty signal is TTL level 1 and the signal in operation of the magnetic cell transmitter indicates that the magnetic cell transmitter 1-1 is not in operation, a 32-bit output signal is generated. And a bypass cell control signal generation circuit 3-4 that outputs a 32-bit data write signal, a ring selection signal, and an interval signal to the self-cell transmitter 1-1, indicating that it is in operation, and 33-bit unit parallel. 14 long words from the synchronous FIFO 3-2 and the bypass cell control signal generation circuit 3-4. A D flip-flop unit (3-6) for receiving bypass cell output data, bypass cell output start signal, 32-bit output signal, and reset signal and outputting bypass cell transmission data and bypass cell transmission data start signal in 32-bit units; Receives bypass cell output data while receiving 32-bit data write signal, ring select signal, and interval signal and checks whether a specific data bit of the first long word of bypass cell output data is 0 or 1, and if it is 0, bypasses ring 1 And a ring selection circuit (3-7) for outputting a cell transmission data write signal and outputting a ring 2 bypass cell transmission data write signal if it is 1.