JP2519329B2 - Subscriber switch subscriber circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a subscriber circuit of a subscriber exchange in packet communication.

[Prior Art] In order to realize multimedia communication in which different media such as voice, data, and images are integrated, packet communication that centrally exchanges different speeds and protocols for each media is effective. Due to the nature of voice and image signals, the amount of information changes from moment to moment, and communication can be performed efficiently by dynamically changing the amount of transmission according to the behavior of the signal.

FIG. 2 shows the flow of voice signals in the packet communication network. The voice analog signal generated by the analog telephone 1 is transmitted to the subscriber line 2 and given to the subscriber exchange 3 composed of the subscriber circuit 3a and the switching circuit 3b, assembled into packets by the subscriber circuit 3a, and then switched. Output from 3b to high-speed digital line 4. This packet is
It is transmitted to the destination subscriber exchange 3 via a plurality of relay exchanges 5, where the packet is decomposed to reproduce a voice analog signal, which is given to the destination analog telephone set 1.

The format of the packet transmitted in this way is
Shown in the figure. The packet PAC has a header HEA as shown in FIG.
The header HEA is composed of information such as the destination address of the packet and the attribute of the packet.
INF is voice data encoded by PCM (for example, CCITT Recommendation G71
1, according to G721).

FIG. 4 shows a conventional basic configuration of a subscriber circuit in the above-mentioned subscriber exchange 3.

In the subscriber circuit 6, the analog voice signal given from the terminal side is given to the analog / digital converter (A / D) 8 through the 2-wire 4-wire converter (H) 7, and this converter 8
After being converted into a digital signal by, the digital signal processor (DSP) 9 performs various kinds of audio signal processing, and thereafter is stored in a buffer memory (BUF) 10.
When one packet of data is accumulated in the buffer memory 10, the digital signal processor 9 adds a header to the packet and activates the buffer memory control circuit (CTL) 11 to activate the switching circuit of the subscriber exchange 3 ( The packet is transferred at high speed (see FIG. 2).

On the contrary, the received packet sent from the switching circuit of the subscriber exchange 3 is stored in the buffer memory 10. After that, the buffer memory control circuit 11 notifies the digital signal processor 9 that the packet has arrived,
The digital signal processor 9 extracts the received packet from the buffer memory 10, performs header analysis, performs various audio signal processing on the data, and then applies the data to the digital / analog exchange (D / A) 12. Then, after being converted into an analog audio signal by the converter 12, it is transmitted to the terminal side through the 2-wire / 4-wire converter 7.

FIG. 5 shows a packet generation process performed by the subscriber circuit 6 together with its transmission process. FIG. 5 (A) shows an analog voice signal generated by the terminal on the transmission side, and as is clear from this waveform diagram, the voiced section and the silent section are mixed. The digital signal processor 9 on the subscriber line of the transmitting side performs voice / silent discrimination of the analog voice signal, and
As shown in FIG. 3B, only the signal in the voiced section is packetized. The transmission packet Pn is converted for each signal of the voiced unit section Tn (n is 1, 2, ... 5, ...). Generally, it is estimated that about 50% of the call time between subscribers is in a non-call state, and by compressing the silent section, the usage efficiency of the line and switching circuit of the packet switching network (asynchronous communication network) is improved.

By the way, at least 1 should be used when distinguishing between voiced and silence.
A buffer memory for voice data for packets is required. This is because the presence / absence of a sound is determined after accumulating one packet of voice data, and the accumulated packet is discarded when there is no sound. In addition, in order to improve the accuracy of voiced / unvoiced discrimination, the near-end echo generated by the 2-wire to 4-wire converter 7 may be echo canceled by the digital signal processor 9. Furthermore, in encoding the audio signal to reduce the information amount of the audio signal, the adaptive difference
Audio band compression signal processing such as PCM may be performed.

As is clear from the comparison of FIGS. 5 (B) and (C),
Even if the transmission packets P1, P2 ... Are transmitted at a constant cycle, the reception packets P1r, P2r ... Have a delay fluctuation and do not arrive at constant intervals. This is because each packet undergoes queuing control when passing through the switching circuit of the packet switching network, and this waiting time changes every moment according to the traffic of the network. Also, each packet does not necessarily pass through the same relay route when relayed from the subscriber circuit on the transmission side to the subscriber circuit on the reception side. In order to absorb this delay fluctuation, it is effective to accumulate packets in the buffer memory and absorb the fluctuation.

The subscriber circuit 6 for one line is shown in FIG. 4 described above.
However, in practice, the subscriber circuit portion is configured as a package capable of processing a plurality of lines. FIG. 6 shows the structure of a conventional subscriber circuit package.

In FIG. 6, a subscriber circuit package 15 accommodating m lines is a microprocessor 16 and a buffer memory 17.
And a direct memory access controller (DMAC) 18
A switch interface circuit (SWINF) 19, a bus arbitration circuit (BUSARB) 20, an internal common bus 21, a clock generator 22, and m circuit termination circuits (so-called BORSCHT) 2
31 to 23 m and m digital signal processors 241-24
m and.

Each line terminating circuit 231 to 23m is a terminating circuit of the subscriber line 251 to 25m, and specifically, a power feeding circuit, an overvoltage protection circuit, a ringing transmission circuit, a line monitoring circuit, a code / decoding circuit, 2
It consists of a 4-wire converter and a test circuit.
Converts the analog audio signal sent from the terminal to a PCM audio signal and transfers it to the digital signal processor 241-24m, and also converts the PCM audio signal sent from the digital signal processor 241-24m to an analog audio signal. Then, the process of sending it to the terminal is performed. In addition,
The built-in power supply circuit, ringing transmission circuit, and circuit monitoring circuit operate according to the call processing control of the microprocessor 16.

Each of the digital signal processors 241 to 24m performs various kinds of signal processing on a voice signal in addition to packet assembling / disassembling processing. The digital signal processors 241 to 24m supply the packets assembled inside to the buffer memory 17 via the bus 21 to store the packets therein, and at the same time, the microprocessor 16
Notify that to. On the contrary, when a packet is received, the digital signal processors 241-24m are notified from the microprocessor 16 that the received packet has arrived. In response to this, the digital signal processor 24
The received packets of 1 to 24 m are extracted from the buffer memory 17.

The buffer memory 17 is a digital signal processor 16
This is a temporary storage memory when packet data is transferred between the switch interface circuit 19 and the switch interface circuit 19. The switch interface circuit 19 is an interface circuit between the switching circuit of the exchange and the buffer memory 17.

The direct memory access controller 18 is a data transfer control circuit between the buffer memory 17 and the switch interface circuit 19, and follows the instruction of the microprocessor 16. The bus arbitration circuit 20 is an arbitration circuit for performing data transfer via the bus 21 in the subscriber circuit package 15.

The microprocessor (central processing unit) 16 includes digital signal processors 241-24m and line termination circuits 231-2.
Various call processes are performed on 3 m, and transfer control of packet data between the switch interface circuit 19, the buffer memory 17, and the digital signal processors 241 to 24 m is performed.

[Problems to be Solved by the Invention] However, the subscriber circuit (package) having the above configuration
No. 15 had the following problems.

For the data transfer in the subscriber circuit package 15, the buffer memory 17, the direct memory access controller 18, and the bus arbitration circuit 20 are required, and the circuit scale is large.

Since the transfer to the buffer memory 17 and the transfer from the buffer memory 17 and the two-stage transfer are necessary and a complicated procedure is required for the transfer in the subscriber circuit package 15, the digital signal processor 241-224 m The effective ability of was reduced.

The microprocessor 16 controls the line termination circuits 231 to 23 m.
Therefore, a register for holding the control signal sent from the microprocessor 16 is required, and the scale of such a circuit portion is large.

Practically, in the coding circuits of the line terminating circuits 231 to 23m, analog signals are converted to μ-law or A-law PCM data (CCI
Digital signal processor 24 converted to TT recommendation G711)
Within 1 to 24 m, the logarithmic compression code is converted into a linear code for signal processing. In this way, the analog signal is not directly converted into a linear code, which causes deterioration of the SN ratio.
Further, the linear audio signal subjected to the signal processing in the digital signal processor 241 to 24m is a μ-law or A-law PCM.
Since it is converted into data and sent to the decoding circuits of the line termination circuits 231 to 23m, the S / N ratio is deteriorated also in this respect.

Since the sampling clock signal used in the encoding / decoding circuits of the line termination circuits 231 to 23m is asynchronous with the oscillation frequency of the clock generator 22 that supplies the system lock signal to each digital signal processor 241 to 24m, analog / The S / N ratio was degraded in the conversion between digital and digital.

The present invention has been made in consideration of the above points,
S / N through conversion between input signal analog and digital
It is an object of the present invention to provide a subscriber circuit of a subscriber exchange having a simple structure with less deterioration of the ratio and having an improved processing capability of a portion for performing packet assembly / disassembly processing.

[Means for Solving the Problem] In order to solve the problem, in the present invention, the subscriber circuit of the subscriber exchange is configured by the following elements.

That is, a voice signal is exchanged in the form of an analog signal between a plurality of circuit termination circuits that perform termination processing for a subscriber line and a corresponding subscriber termination circuit,
Multiple packet communication signal processing circuits that perform packet assembly / disassembly, voice signal processing, line termination circuit control operations, and competition control between packet transmission operations and reception operations in synchronization with the network, and multiple packet communication signals It is commonly provided to the signal processing circuits, receives serial packet data directly given from any one of the signal processing circuits for packet communication, performs interface processing, and outputs to the switching circuit in the subscriber exchange. , A switch interface circuit for serially outputting the packet data given from the switching circuit to a packet communication signal processing circuit associated with the destination, and for controlling the competition between the packet receiving operation and the packet transmitting operation, and for each packet communication It is composed of a central processing unit that controls the signal processing circuit.

[Operation] Each line terminating circuit performs terminating processing on the subscriber line in an analog manner, and gives an analog voice signal to the corresponding packet communication signal processing circuit. At this time, each line termination circuit is controlled by the signal processing circuit for packet communication via a bus different from the system bus so that the system bus is not occupied. That is, the central processing unit can control the line termination circuit only through the signal processing circuit for packet communication.

Each packet communication signal processing circuit digitally encodes the input analog voice signal in synchronization with the network, performs voice processing, and assembles a packet. At this time, competition control with the packet reception operation and competition control with the transmission operation of another processing circuit are performed. The competition control with the packet receiving operation is also performed in the switch interface circuit.

The assembled packet data is directly provided to the switch interface circuit serially. The switch interface circuit outputs this to the switching circuit.

In this way, it is possible to transmit a packet without providing a buffer memory or a bus contention circuit.

Since the processing upon receiving the packet is the reverse processing described above, the description thereof is omitted here.

[Embodiment] Hereinafter, the configuration and operation of one embodiment of the present invention will be described in the order of a subscriber circuit package, a signal processing integrated circuit for packet communication, a phase locked loop, a serial reception interface, a serial transmission interface, and a parallel port interface. .

Subscriber Circuit Package FIG. 1 is a block diagram showing a subscriber circuit package 30 of this embodiment, which is to be compared with FIG. 6 showing a conventional subscriber circuit package 15.

The subscriber circuit package 30 of this embodiment includes a microprocessor (central processing unit) 31 for controlling the entire subscriber circuit, a switch interface circuit 32 for interfacing with the switching circuit of the subscriber exchange, and each subscriber. A line terminating circuit (so-called BORSCH) for terminating the subscriber line provided for each main line 331 to 33 m.
T) 341 to 34m, and packet communication signal processing integrated circuits 351 to 35m provided for each subscriber line 331 to 33m for assembling / disassembling packets and performing voice signal processing.

Since each of the signal processing integrated circuits 351 to 35m for packet communication is configured as shown in FIG. 7 and the serial reception interface and the serial transmission interface are configured as shown in FIGS. 10 and 12, shown in FIG. Unlike the conventional circuit, the buffer memory 17, the direct memory access controller 18, the bus arbitration circuit 20, the clock generator 22 and the like are not provided.

The switch interface circuit 32 is not connected to the system bus 36. In this embodiment, without using the bus 36, the signal processing integrated circuits 351 to 35 m for packet communication are provided.
And the switch interface circuit 32 directly exchange data serially. The input / output lines for serial data of the signal processing integrated circuits 351 to 35m for packet communication are multi-connected (wired or connected).

Furthermore, the line termination circuits 341 to 34m are not connected to the system bus 36 either. Each line terminating circuit 341-34m is connected to the corresponding packet communication signal processing integrated circuit 351-35m via a local bus 371-37m. That is,
The signal processing integrated circuits 351 to 35m for packet communication finally control the line terminating circuits 341 to 34m.
Signal control integrated circuit 351 for each packet communication for call control processing
~ 35m will do.

Also, in this embodiment, the voice signals are transmitted and received as analog signals between the signal processing integrated circuits 351 to 35m for packet communication and the corresponding line termination circuits 341 to 34m. Therefore, as the line termination circuits 341 to 34m, analog processing configurations are used.

Signal processing integrated circuit for packet communication FIG. 7 shows a signal processing integrated circuit for packet communication 39 (35) of the embodiment which is composed of one large-scale integrated circuit (LSI).
FIG. 1 is a block diagram showing 1 to 35 m).

In FIG. 7, the signal processing integrated circuit 39 for packet communication includes an analog / digital converter and a digital / analog converter (hereinafter referred to as AD
DA converter) 40 and digital signal processor (DSP) 4
1 and a phase locked loop (PLL) circuit 42.

The synchronization signal SYN and the clock signal CLK are signals synchronized with the communication network, and are given to the phase locked loop circuit 42 from outside the subscriber circuit package 30. Phase locked loop circuit
42 is a new synchronization signal SYNCP synchronized with the synchronization signal SYN and the clock signal CLK, and two types of clock signals CLK.
CP and CLKSMP are created, the created synchronization signal SYNCP and the created clock signal CLKCP are supplied to the digital signal processor 41, and the clock signal CLKSMP is supplied to the AD / DA converter 40.

The analog audio signal AIN input from the line termination circuit (341 to 34m) is input to the AD / DA converter 40 as the clock signal CLK.
It is sampled at high speed based on SMP, converted into a digital signal DC, and supplied to the digital signal processor 41. On the contrary, the digital signal DI output from the digital signal processor 41 is converted into the analog signal AOUT in the AD / DA converter 40 based on the clock signal CLKSMP and supplied to the line terminating circuit.

The digital signal processor 41 provides the microprocessor with an address bus AB, a bidirectional data bus DB, and a signal line for the write enable signal WE so that the microprocessor (31) can perform control. , And the signal line for the read enable signal OE and the signal line for the chip enable signal CE.

The digital signal processor 41 is also connected to parallel data input PI and a porter for parallel data output PO, and the line termination circuit is connected via these ports.
It is connected to 341-34m and can input and output the data required for call control processing, testing, maintenance and monitoring.

Further, the digital signal processor 41 receives serial output data SO, a busy signal BSY, and a serial input from the switch interface circuit (32) and other integrated circuits (351 to 35m) for transmitting and receiving packets. Data S
I, a signal line for transmitting the reception request signal RREQ is connected.

The signal processing integrated circuit 39 for packet communication is
It is possible to send and receive packet data with a simple procedure,
The S / N ratio does not deteriorate even through analog / digital conversion or digital / analog conversion, and the line termination circuit can be controlled.

Then, the signal processing integrated circuit 39 for packet communication is
A serial port for transmitting and receiving packet data, an AD / DA converter 30 according to the oversampling method, a phase lock loop circuit 42 for generating a clock signal synchronized with a clock signal supplied from a communication network, and a line termination circuit ( 341 to 34 m) is provided with a parallel port for controlling.

The features will be described separately for the reception configuration and the transmission configuration. The serial interface configuration of the switch interface circuit 32 has a configuration conforming to the interface of the processing integrated circuit 39. Since the AD / DA converter 40 according to the oversampling method regarding the characteristics does not have a structure unique to the structure itself, the structure will not be described in detail. Phase locked loop circuit with features
42 will be described in detail below. The interface section of the parallel port relating to the characteristics may have a unique configuration, but a temporary explanation will be given below.

Phase Lock Loop Circuit FIG. 8 is a block diagram showing a detailed configuration example of the phase lock loop circuit 42 shown in FIG. 7, and FIG. 9 is a timing chart of each part thereof.

As is well known, the phase locked loop circuit 42 includes a phase difference detector 45, a low pass filter (LPF) 46, a voltage controlled oscillator (VCO) 47, and a frequency divider 48. In addition to this, a shift register circuit 49, two invert gates 50 and 51, and an AND gate 52 are provided.

The voltage controlled oscillator 47 is a digital signal processor.
The clock signal CLKCP (FIG. 9 (D)) output to 41 is formed by oscillation. This clock signal CLKCP is divided by a frequency divider 48 into a predetermined fraction, and the AD / DA converter 40
A clock signal CLKSMP (FIG. 9 (E)) is generated and output, and is also supplied to the phase difference detector 45.
The phase difference detector 45 has a clock signal CLK synchronized with the network.
(Fig. 9 (B)) is also given, and the phase difference detector 45
Generates a pulse according to the phase difference between these clock signals CLKSMP and CLK. This phase difference pulse is converted into a DC signal by the low-pass filter 46, and then given to the voltage controlled oscillator 47 as a control signal of the oscillation frequency. Thus, the high-speed oscillation clock signal CLKCP is synchronized with the network to the clock signal. I am trying to synchronize with CLK.

The synchronization signal SYN (Fig. 9 (A)) is 1 of the clock signal CLK.
It has a pulse width corresponding to a clock and has a frequency twice that of the band of the analog audio signal. The phase locked loop circuit 42 forms a synchronization signal SYNCP (FIG. 9C) for the digital signal processor 41, which is a synchronization of the synchronization signal SYN. The synchronization signal SYN is input as data to the shift register circuit 49, and a clock signal obtained by inverting the clock signal CLKCP via the inversion gate 50, that is, a reverse phase clock signal of the clock signal CLKCP is input to the shift register circuit 49 as a shift clock signal. Given. The output of a certain stage of the shift register circuit 49 (in the case of the second stage in FIG. 9) is directly applied to the AND gate 52, and the output shifted by one stage more than that is inverted through the invert gate 51 and is output to the AND gate 52. Given to. Thus, the output synchronization signal SYNCP having a pulse width of one clock of the clock signal CLKCP is obtained from the AND gate 52.

Note that FIG. 9 (F) shows the data timing for the digital signal processor 41 at that time.

The reason why the phase locked loop circuit 42 is included in the integrated circuit 39 is that the output of the generator of the synchronization signal synchronized with the network is used to simplify the configuration and achieve synchronization. This is because if this circuit is provided outside the integrated circuit, the problem of crosstalk will occur greatly due to the processing of high frequency signals.

Serial Reception Interface Next, the serial reception interface of the serial interface configuration of the digital signal processor 41, which is one of the features of this embodiment, will be described.

Here, FIG. 10 is a block diagram showing the configuration of the serial reception interface, and FIG. 11 is a timing chart of each part thereof.

The serial reception interface 55 includes a D-type flip-flop circuit 56, AND gates 57 and 58, a shift register circuit 59, a latch circuit 60, a three-state buffer circuit.
61 and an RS flip-flop circuit 62, which converts a serial reception packet into parallel data and supplies it to the internal data bus 63 to supply it to the original processing unit as the digital signal processor 41.

The digital signal processor 41 (see FIG. 7) is provided with a reception request signal which becomes active when packet data is to be input to the digital signal processor 41.
RRERQ (Fig. 11 (B)) is the switch interface circuit 3
Given from 2. The reception request signal RREQ is given to the data terminal of the D-type flip-flop circuit 56. The clock terminal of the D-type flip-flop circuit 56 has a clock pulse signal CKSC having the same period (hereinafter, referred to as a frame) to the synchronization signal SYN (FIG. 11A) shown in FIG.
N (Fig. 11 (C)) is given. Thus, the reception request signal RREQ is sampled by the clock pulse signal CKSCN in the D-type flip-flop circuit 56, and the reception request flag RRFG (FIG. 11 (D)) is transmitted to the original processing unit of the digital signal processor 41 from the outside of the packet. Notifying that there is a reception request, the flag RRFG is given to the AND gates 57 and 58 as a passage control signal.

The shift clock pulse signal SCKR (the
FIG. 11 (F): For example, the clock signal CLKCP described above has the same number of pulses as the number of bits forming a packet in one frame, and passes to the latch circuit 60 when the AND gate 58 is opened. Latch pulse signal LP
(FIG. 11 (G)) is generated for each predetermined number of bits for which serial data makes sense and in synchronization with the shift clock pulse signal SCKR.

The shift register circuit 59 converts serial input into parallel output, and shifts serial received data SI (FIG. 11 (E); see FIG. 7) through the AND gate 57 during packet receiving operation. Clock pulse signal SCKR
It is taken in by. The data thus captured by the shift register circuit 59 and converted into parallel output is provided to the data terminal of the latch circuit 60. The latch circuit 60 outputs the output of the shift register circuit 59 to
It latches based on the latch pulse signal LP output from the AND gate 58 and supplies the latch output LAT (FIG. 11 (H)) to the three-state buffer circuit 61.

The output (LP) of the AND gate 58 is given to the set terminal of the RS flip-flop circuit 62, and the latch circuit 60 latches the output of the shift register circuit 59 and the RS flip-flop circuit 62 is set at the same time. There is. The Q output of the RS flip-flop circuit 62 is output as a reception completion flag RAKFG (FIG. 11 (J)) and notifies the central processing unit of the digital signal processor 31 that the reception of a part of the packet is completed.

When the flag RAKFG becomes active, the central processing unit of the digital signal processor 41 activates the source enable signal SRCEN (FIG. 11 (I)) that indicates to the signal source side that the signal can be taken in. . The source enable signal SRCEN is given to the control terminal of the three-state buffer circuit 61 and the reset terminal of the RS flip-flop circuit 62. When the source enable signal SRCEN becomes active, the output data of the latch circuit 60 is supplied to the internal data bus 63, the RS flip-flop circuit 62 is reset and the reception completion flag RAKFG becomes inactive, and the data of the next predetermined bit. Is ready to be captured.

Such an operation is repeated until one packet of data is received.

Serial Transmission Interface Next, the serial transmission interface of the serial interface configuration of the digital signal processor 41, which is one of the features of this embodiment, will be described.

Here, FIG. 12 is a block diagram showing the configuration of the serial transmission interface, and FIG. 13 is a timing chart of each part thereof.

This serial transmission interface 65 includes inverter gates 66 and 71, AND gates 67, 70, 73, 74 and 78, D
Type flip-flop circuit 68, open collector (or drain) invert gate 69, RS flip-flop circuit
72 and 77, a latch circuit 75, a shift register circuit 76, and an open collector (or drain) NAND gate 79. The parallel data from the internal data bus 80 (53) is converted into serial data and the switch interface circuit 32 is used as a transmission packet. It is intended for output.

The reception request signal RREQ (FIG. 13 (B)) described for the serial reception interface 55 is also given to the serial transmission interface 65. This is to stop the serial transmission operation during the serial reception operation.
This is a kind of competitive control. The reception request signal RREQ is inverted via the inversion gate 66 and the AND gate 67.
Given to.

The transmission request flag SREQF (FIG. 13 (C)) is activated by the main processing unit of the digital signal processor 41 when one packet of the transmission packet of the memory in the digital signal processor 41 is accumulated. , Is made inactive when packet transmission is completed. This transmission request flag SREQF is AND gate 6
7 and 70, given to Invert Gate 71.

The busy signal BSY (FIG. 13 (D)) output from the Q output terminal of the RS flip-flop circuit 72 is because the integrated circuit parts 351 to 35m are used in the multi-connection configuration as shown in FIG. Required competing control signal, active low signal via open collector invert gate 69.
It is converted into BSY * (* represents active low) and provided to another integrated circuit and AND gate 67. As described above, when the integrated circuit portion is used in the multi-configuration, it is necessary to perform the competition control. Therefore, it is necessary to connect the busy terminals of each integrated circuit in multi (wired-or) and pull up with an external resistor (not shown). And
When transmitting the packet data, the digital signal processor 41 first scans the busy signal BSY * to check that the busy signal BSY * has not been executed by any integrated circuit.
If * is "H", set the busy signal BSY * to "L" so that other integrated circuits do not activate the transmission operation, then transmit the packet, and when the transmission is completed, set the busy signal BSY * to "H".
Return to.

The clock pulse signal CKSCN (FIG. 13 (E)) has the same frame as the above-mentioned synchronization signal SYNC (FIG. 13 (A)), and is supplied to the clock terminal of the D-type flip-flop circuit 68. D-type flip-flop circuit 68
Samples the output from the AND gate 67 and supplies its Q output Q68 to the AND gates 70, 73, 74 and 78 and the invert gate 71, and at the same time, the transmission enable flag DACFG
As shown in FIG. 13 (F), the digital signal processor 41
The central processing unit is notified that the packet can be transmitted. According to the logical condition of the AND gate 67, the condition that the transmission permission flag DACFG becomes active is that there is a packet transmission request, there is no packet transmission request, and another integrated circuit is not transmitting a packet.

The AND output of the transmission request flag SRQFG and the transmission permission flag SAKFG (Q68) is given from the AND gate 70 to the set terminal of the RS flip-flop circuit 72, and the transmission request flag SRQFG is inverted to the reset terminal of the flip-flop circuit 72. The signal is given from the invert gate 71. As described above, the Q output of the RS flip-flop circuit 72 is inverted via the open collector inversion gate 69 and output as the above-mentioned busy signal BSY *.

That is, when the transmission permission flag SAKFG becomes active, the RS flip-flop circuit 72 is set and the busy signal BSY * becomes the “L” state, which notifies the other integrated circuits that the packet data is currently being transmitted, When the transmission of the data is completed and the transmission request flag SRQFG becomes inactive, the flip-flop circuit 72 is reset and the busy signal BSY * is returned to “H”.

The destination enable signal DSTEN (FIG. 13 (G)) is given from the digital signal processor 41 to the latch circuit 75 and the RS flip-flop circuit 77. The central processing unit of the digital signal processor 41 has a destination latch circuit 75 when executing a transfer instruction.
, The destination enable signal DS
TEN becomes active and the RS flip-flop circuit 77 is reset at the same time. At this time, the Q output of the RS flip-flop circuit 77 is output as the transfer permission flag COACFG (FIG. 13 (l)). This transfer enable flag COACFG
Becomes inactive until the data latched in the latch circuit 75 is loaded in the shift register circuit 76, and notifies the central processing unit of the digital signal processor 41 that the latch circuit 75 is currently in use.

The shift lock pulse signal SCKS (Fig. 13 (J)) is 1
It is a signal having the same number of pulses as the number of bits forming a packet in a frame, and is given to the AND gate 74 which is opened by the transmission permission flag SAKFG. The load pulse signal LDP (FIG. 13 (I)) is given to the AND gate 73 which is opened by the transmission permission flag SAKFG. The shift register circuit 76 is used for parallel input and serial output. During the packet data transmission operation, the load pulse signal is sent from the AND gate 73 at the specified timing.
LDP is given and the latch data of the latch circuit 75 is loaded (see FIG. 13 (H)). Simultaneously with this load operation, the RS flip-flop circuit 77 is set and the transfer permission flag COACFG becomes active to notify the central processing unit of the digital signal processor 41 that the latch circuit 75 has become empty. Further, the shift clock signal SCKS is given from the AND gate 74 at a specified timing, and the data in the shift register circuit 76 is serially output to the open collector NAND gate 79 (see FIG. 13 (K)).

The transmission enable signal SEN (FIG. 13 (M)) is given from the central processing unit to the AND gate 78. The transmission enable signal SEN has a cycle of one frame and is active while the shift register circuit 76 outputs packet data. Therefore, when the transmission permission flag SAKFG becomes active, the output of the AND gate 78 opens the open collector NAND gate 79 at the specified timing. Thus, the serial-converted packet data is output to the switch interface circuit 32. Since the serial transmission data SO is the output of the open collector NAND gate 79, it needs to be pulled up by an external resistor (not shown).

Such an operation is repeated until one packet of data is transmitted.

Parallel Port Interface FIG. 14 shows a parallel port interface in the digital signal processor 41.

The interface 85 comprises a latch circuit 86 and a three-state buffer circuit 87. The data from the internal data bus 88 (same as 53, 80) of the digital signal processor 41 is latched at the timing of the latch pulse signal LP1 and output to the line terminating circuit, and the parallel data from the line terminating circuit is converted to the source enable signal. The data is taken into the data bus 88 via the buffer circuit 87 which is opened by SRCEN1.

Effects of the Embodiment (1) Since the AD / DA converter 40 of the oversampling system is installed, the following effects can be obtained.

(1-1) Since it is mounted only on the integrated circuit portion, the circuit scale of the subscriber circuit is reduced.

(1-2) Oversampling AD / DA converter 40
Since the analog circuit scale is small and the processing precision required for analog elements is not high, it is suitable for analog and digital mixed integrated circuits (LSI). Therefore, the adjustment work becomes easier than before.

(1) Since the phase locked loop circuit 42 is mounted, the following effects can be obtained.

(2-1) Oversampling AD / DA converter 40
Since the sampling clock phase of and the clock phase of the digital signal processor 41 are synchronized and the edges do not overlap, the S / N of the AD / DA converter 40 is
Can be improved. In integrated circuits, especially in CMOS configuration, a large current flows at the edge of the clock, and the sampling of the AD / DA converter 40 may be adversely affected by the large change in this current. It is an effect that occurs because of being.

(2-2) Since it is not necessary to mount an oscillator for the clock of the digital signal processor 41, the circuit scale of the subscriber circuit can be reduced.

(3) Since the digital signal processor 41 is equipped with the serial transmission / reception interface and the parallel interface having the competition control configuration (the switch interface circuit is also configured to have the serial transmission / reception interface corresponding thereto), the following effects Can be obtained.

(3-1) Call processing information is transferred to and from the microprocessor 31, and the digital signal processor 41 controls the line terminating circuit from the parallel output port based on the call processing information, and the information of the line terminating circuit from the parallel input port. By collecting, the microprocessor 31 does not need to directly control the line terminating circuit, so the interface between the microprocessor 31 and the line terminating circuit can be removed as described above, the configuration can be simplified, and the communication control can be performed. You can simplify the procedure.

(3-2) Since the integrated circuit 39 can be used in a multi-connection configuration because it has a serial transmission / reception interface having a contention control configuration, a separate external contention circuit is provided for packet transmission / reception. No need.

(3-3) Oversampling AD / DA converter 40
Normally performs the sampling rate conversion in several steps, but when the sampling rate is close to the Nyquist frequency of the voice band, the digital signal processor 41
Can be used. By doing so, the circuit scale of the AD / DA converter 40 can be reduced.

(3-4) Packets can be exchanged with the switch interface circuit 32 using a small amount of memory built in the digital signal processor 41.
An external buffer memory for temporarily storing packets is not required, and as a result, a direct memory access controller is not required, which simplifies the configuration and makes transfer control easier than before. Become.

Other Embodiments In the above embodiments, the busy signal for controlling the competition between the transmitting operation and the receiving operation is changed to the digital signal processor 41.
However, a signal similar to this may be output to the switch interface circuit 32 for control.

[Effects of the Invention] As described above, according to the present invention, the S / N ratio is less likely to deteriorate due to the conversion between the analog and the digital of the input signal, and the packet assembling / disassembling process is performed with a simple configuration. It is possible to obtain a subscriber circuit of a subscriber exchange in which the processing capacity of a part is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a subscriber circuit of a subscriber exchange according to the present invention, FIG. 2 is an explanatory view showing a flow of a voice signal in a packet communication network, and FIG. 3 is an explanation showing a packet format. 4 and 5 are block diagrams showing a conventional basic configuration of a subscriber circuit, FIG. 5 is a signal waveform diagram showing a packet generation process performed by the subscriber circuit together with a transmission process, and FIG. 6 is a conventional subscriber circuit. FIG. 7 is a block diagram showing a package, FIG. 7 is a block diagram showing a configuration of a signal processing integrated circuit for packet communication of the above-mentioned embodiment, FIG. 8 is a block diagram showing a detailed configuration of a phase locked loop circuit thereof, and FIG. Timing chart of each part, FIG. 10 is a block diagram showing the configuration of the serial reception interface in the digital signal processor of the signal processing integrated circuit for packet communication, and FIG. FIG. 12 is a block diagram showing the configuration of the serial transmission interface of the digital signal processor, FIG. 13 is a timing chart of each part thereof, and FIG. 14 is a block diagram showing the configuration of the parallel port interface of the digital signal processor. is there. 30 …… Subscriber circuit package, 31 …… Microprocessor, 32 …… Switch interface circuit, 331-33m ……
Subscriber line, 341-34m ... Line termination circuit, 351-35m, 39 ...
Signal processing integrated circuit for packet communication, 40 AD / DA converter, 41 Digital signal processor, 42 Phase lock loop circuit.

Claims (2)

(57) [Claims] 1. A circuit for exchanging a voice signal in the form of an analog signal between a plurality of circuit terminating circuits for terminating a subscriber line and corresponding subscriber terminating circuits.
A plurality of packet communication signal processing circuits for performing disassembly, voice signal processing, control operation of the above-mentioned line termination circuit, and competition control between packet transmission operation and reception operation in synchronization with the network, and a plurality of above-mentioned packet communication signal processing circuits. It is provided in common to the circuit, receives serial packet data directly given from any of the packet communication signal processing circuits, performs interface processing, and outputs to the switching circuit. A switch interface circuit that serially outputs the given packet data to the packet communication signal processing circuit associated with the destination, and that controls the competition between the packet receiving operation and the packet transmitting operation, and the packet communication signal processing described above. A central office unit for controlling the circuit, and 'S circuit. 2. A signal processing circuit for each packet communication is formed of an integrated circuit of one chip, and an oversampling type analog / digital converter, an oversampling type digital / analog converter, and a network. The phase-locked loop circuit for generating a synchronized synchronizing signal and clock signal, and a digital circuit processor for executing the processing assigned to the packet communication signal processing circuit. Subscriber circuit of the subscriber exchange.