JPH03160840A - Subscriber circuit for subscriber exchange - Google Patents

Abstract

PURPOSE:To reduce the deterioration in the S/N through digital coding of an input signal or the like and to improve the processing capability of sections applying packet composing/decomposing processing with simple constitution by providing a signal processing integrated circuit for packet communication or the like. CONSTITUTION:Line termination circuits 341-34m apply termination processing to subscriber lines 331-33m analogically and give an analog voice signal to relevant packet communication signal processing integrated circuits 351-35m. The circuits 351-35m encode the inputted analog voice signal digitally synchronously with the packet exchange, apply voice processing to recompose the packet. Then the composed packet data is given directly serially to a switching interface circuit 32 and the circuit 32 outputs it to a switching circuit. In the processing above, a microcomputer 31 controls the circuits 341-34m via the circuits 351-35m only, the contention control is applied in the circuit 32, the deterioration in the S/N is decreased and the packet composing/decomposing processing capability 5 is improved with simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a subscriber circuit of a subscriber exchange in packet communications.

[Prior Art] In order to realize multimedia communication that integrates different media such as voice, data, and images, packet communication that centrally exchanges and processes different speeds and blocks for each media is effective. . Due to their nature, the amount of information in audio and image signals changes from time to time, and highly efficient communication can be achieved by dynamically changing the amount of transmission depending on the behavior of the signal.

FIG. 2 shows the flow of voice signals in the Packet I communication network. A voice analog signal generated by an analog telephone 1 is transmitted through a subscriber line 2 and given to a subscriber exchange 3 consisting of a subscriber circuit 3a and a switching circuit 3b, and after being assembled into packets in the subscriber circuit 3a, it is sent to a switching circuit. 3b is output to the high-speed digital line 4. This packet is transmitted to the destination subscriber exchange 3 via a plurality of relay exchanges 5, where the packet is disassembled and an audio analog signal is reproduced, which is then given to the destination analog lightning talk machine (2).

The format of the packet transmitted in this way is shown in FIG. As shown in Figure 3, the bucket t-PAC consists of a header HEA and an information part INF, and the bucket TEA
The information part INF is composed of PCM-encoded audio data (for example, according to CCITT recommendations G7tl and G721).

FIG. 4 shows a conventional basic configuration of a subscriber circuit in the subscriber exchange 3 described above.

In the subscriber circuit 6, the analog voice signal given from the terminal side is converted into an analog/
is applied to a digital converter (A/D) 8, and this converter 8
After being converted into a digital signal by a digital signal processing processor (DSP>9), it is subjected to various types of audio signal processing, and then stored in a buffer memory (BUF) 10. One packet worth of data is stored in the buffer memory 10. Once stored, the digital signal processor 9 adds a header to the packet, and buffer memory control circuit i?8 (
CTL) 1 1 and transfers the packet j to the switching circuit #I of the subscriber exchange 3 (see FIG. 2) at high speed.

Conversely, received packets sent from the switching circuit of the subscriber exchange 3 are stored in the buffer memory 10. After that, the buffer memory control circuit 11 notifies the digital signal processing processor 9 that the packet has arrived,
The digital signal processor 9 extracts the received packet from the buffer memory 10, analyzes the header, performs various audio signal processing on the data, and then supplies the data to the digital/analog converter (D/A) 12. And this converter 1
After the signal is converted into an analog audio signal at step 2, it is transmitted to the terminal side via a 2-wire/4-wire converter 7.

FIG. 5 shows the packet generation process carried out by the subscriber circuit 6 together with its transmission process. FIG. 5(A) shows an analog audio signal generated by the transmitting terminal, and as is clear from this waveform diagram, there are both sound sections and silent sections. The digital signal processing processor 9 of the transmitting subscriber circuit performs voice/silence discrimination of the analog audio signal and
As shown in Figure (B), only the signal in the sound section is packetized. Voiced position interval 'l'n (n is 1, 2, ... 5,
...) is converted into a transmission packet l-Prl.

Generally, it is estimated that about 50% of the call time between subscribers is in a non-call state, and by compressing the silent period, the efficiency of using the lines and switching circuits of the packet switching network (asynchronous communication $12J) can be improved. There is.

By the way, when identifying speech/silence, a buffer memory for at least one packet of audio data is required.

This is because, after accumulating audio data for packet 1·, it is determined whether there is sound or no sound, and if there is no sound, the accumulated packet t· is discarded. Further, in order to improve the accuracy of sound/silence discrimination, near-end echoes generated by the 2-wire/4-wire converter 7 may be echo-cancelled by a digital signal processing processor. Furthermore, in order to reduce the amount of information in the audio signal, audio band compression signal processing such as adaptive differential PCM may be applied when encoding the audio signal.

As is clear from the comparison of FIG. 5(B) and (C), even if the transmission packets P1, P2, etc. are transmitted at a constant cycle,
Receive {3 packets P1r. P2r... has delay fluctuations and does not arrive at regular intervals. each packet is packet 1
・This is because the waiting time is subject to waiting control when passing through the switching circuit of the AC network, and this waiting time changes from moment to moment depending on the traffic density of the network. Further, when each packet is relayed from a sending subscriber circuit to a receiving subscriber circuit, it does not necessarily pass through the same relay route. In order to absorb this delay fluctuation, an effective method is to accumulate packets in a buffer memory to absorb the fluctuation.

Although the above-mentioned Figure 4 shows a basic example of the subscriber circuit 6 for one line, His Majesty has shown that the subscriber circuit section can be used as a package that can handle multiple lines. ing. FIG. 6 shows the configuration of a conventional subscriber circuit package.

In FIG. 6, a subscriber circuit package 15 accommodating m lines includes a microprocessor 16, a buffer memory 17, and a direct memory access controller (DM).
AC) 18 and switch interface circuit (SWIN
F) 19, a bus arbitration circuit (BUSARB) 20, an internal common bus 2l, a clock generator 22, m line termination circuits (so-called BORSCHT) 231 to 23m, and m digital signal processing processors 241 to It is equipped with 24m.

Each line termination circuit 231 to 23m is connected to subscriber line 251 to 25m.
m termination circuit, and in detail, it is controlled in the power supply circuit, overvoltage protection circuit, ringing output path, line monitoring circuit, encoding/decoding circuit, 2-wire 4-wire converter, and test circuit.
Mainly, the analog audio signals sent from the terminals are converted into PCM audio signals and delivered to the digital signal processing processors 241 to 24m, and the PCM audio signals sent from the digital signal processing processors 241 to 24m are converted into analog audio signals. It performs the process of converting the data into a file and sending it to the terminal. The built-in power supply circuit, ringing output path, and line monitoring circuit operate according to the call processing control of the microprocessor (6).

Each of the digital signal processors 241 to 24m performs various types of signal processing on the audio signal in addition to processing for assembling and disassembling the packet t. Digital signal processing processor 241~
24m supplies the internally assembled packet to the buffer memory 7 via the bus 21 for storage, and also notifies the microprocessor 16 of this fact. Conversely, when a packet is received, the digital signal processing processors 241 to 24m are notified by the microprocessor 16 that the received packet has arrived. In response to this, the digital signal processors 241-24m extract the received packet l. from the buffer memory l7.

The buffer memory 17 includes a digital signal processing processor l.
This is a temporary storage memory when transferring packet data between the switch interface circuit 6 and the switch interface circuit 19. The switch interface circuit 2819 is an interface circuit between the switching circuit of the exchange and the buffer memory 7.

The direct memory access controller 18 is a data transfer control circuit between the buffer memory 17 and the switch interface circuit 19, and follows instructions from the microprocessor 16. The bus arbitration circuit 20 is an arbitration circuit for performing data transfer via the bus 22 within the subscriber circuit package 15.

The microprocessor (central processing unit>16 performs various call processing on the digital signal processing processors 241 to 24m and the line termination circuits 231 to 23m, and also controls the switch interface circuit 19, buffer memory 7,
It controls the transfer of packet data between the digital signal processors 241 to 24m.

[Problem M to be solved by the invention] However, the above elliptical subscriber circuit (package>1
5 had the following problems.

■For data transfer within the subscriber circuit package 15,
A buffer memory 17, a direct memory access controller 18, and a bus arbitration circuit 20 are required, resulting in a large circuit size.

■Transfer to the buffer memory 17 and transfer from the buffer memory 17 are required, and the transfer within the subscriber circuit package ■5 requires a complicated procedure.
The effective capability of the digital signal processing processors 24↓~24m was decreasing.

(2) Since the line termination circuits 231 to 23m are controlled by the microprocessor 16, a register for holding control signals sent from the microprocessor 16 is required, which increases the scale of the circuit portion.

■Actually, in the line termination circuits 231 to 23 TTI encoding circuits, analog signals are
1awPCM data (CCITT Recommendation G711), and the digital signal processing processors 241 to 24m convert this logarithm compression code to a linear code for signal processing.In this way, analog signals are not directly converted to linear codes. In addition, the linear audio signal processed within the digital signal processing processors 241 to 24m is μ-law or A-1awP.
Converted to CM data and sent to line termination circuits 231-23
Since the signal is sent to m decoding circuits, the S/N ratio deteriorates in this respect.

■Since the sampling clock signal used in the encoding/decoding circuit of the line termination circuits 231 to 23m is asynchronous with the oscillation frequency of the clock generator 22 that supplies the system clock signal to each digital signal processing processor 241 to 24m, The S/N ratio deteriorated in mutual conversion between analog and digital.

The present invention has been made in consideration of the above points, and it is possible to achieve S/N through conversion between analog and digital input signals.
It is an object of the present invention to provide a subscriber circuit for a subscriber exchange, which has a simple structure with little deterioration in ratio, and which has an improved processing capacity in a part that performs packet assembly and disassembly processing.

[Means for Solving the Problem] In order to solve the problem, in the present invention, the subscriber circuit of the subscriber exchange is constructed with the following elements.

In other words, voice signals are exchanged in the form of analog signals between a plurality of line termination circuits that perform termination processing for subscriber lines and the corresponding subscriber termination circuits. A plurality of signal processing circuits for packet communication that perform signal processing, control operation of the line termination circuit, and competition control between bucket 1 transmission operation and reception operation in synchronization with the network, and a plurality of signal processing channels for communication bucket 1 Commonly provided in circuits, it receives serial packet data directly applied from any packet communication signal processing circuit, processes the interface, and outputs it to the switching circuit in the subscriber exchange. A switch interface circuit that serially outputs the packet data given from the circuit to the bucket 1 and communication signal processing circuit related to its destination, and also performs competition control between the packet reception operation and the transmission operation, and the switch interface circuit for each packet. A central processing unit that controls communication signal processing circuits.

[Operation] Each line termination circuit performs termination processing for each subscriber line in an analog manner, and supplies an analog audio signal to the corresponding packet 1/communication signal processing circuit. At this time, each line termination circuit is
It is controlled by a packet communication signal processing circuit via a bus different from the system bus. That is, the central processing unit can control the line termination circuit only via the packet communication signal processing circuit.

Each packet communication signal processing circuit digitally encodes the input analog audio signal in synchronization with the network, performs audio processing, and assembles a packet. Note that at this time, competition control with the packet reception operation and competition control with the transmission operation of other processing circuits is performed. Contention control with the packet reception operation is also performed in the switch interface circuit.

The assembled packet data is provided serially directly to the switch interface circuit.

The switch interface circuit outputs this to the switching circuit.

In this way, packets can be transmitted without special provision of buffer memory or bus contention circuit.

The process when receiving a packet is the reverse process as described above, so the explanation will be omitted here.

[Embodiment] The structure and operation of an embodiment of the present invention will be explained below in the order of a subscriber circuit package, a signal processing integrated circuit for packet communication, a phase-locked loop, a serial reception interface, a serial transmission interface, and a parallel boat interface. do.

m Package FIG. 1 is a block diagram showing a subscriber circuit package 30 of this embodiment, and is compared with FIG. 6, which shows a conventional subscriber circuit package 15.

The subscriber circuit package 30 of this embodiment includes a microprocessor (central processing unit) 31 that controls the entire subscriber circuit, a switch interface circuit #132 that interfaces with the switching circuit of the subscriber exchange, and each Assembly of line termination circuits (so-called BORSCHT) 34 1 to 34m provided for each subscriber line 331 to 33m for terminating the subscriber line, and packet circuits provided for each subscriber line 33l to 33m.・Packet 1 for disassembling and audio signal processing ・Communication signal processing integrated circuits 351-35m are installed horizontally.

The communication signal processing integrated circuits 351 to 35m for each bucket 1 to 35m are arranged horizontally as shown in Fig. 7, and the serial receiving interface and serial transmitting interface are arranged as shown in Figs.
Since it is constructed laterally as shown in FIG. 2, unlike the conventional circuit shown in FIG. 6, the buffer memory 17, direct memory access controller 18, bus arbitration circuit 20, clock generator 22, etc. are not provided.

Further, the switch interface circuit 32 is not connected to the system bus 36. In this example, bus 3
6, each packet communication river signal processing integrated circuit 35
1-35. m and the switch interface circuit 32 directly exchange data serially. The serial data input/output lines of each of the packet communication signal processing integrated circuits 351 to 35m are multi-connected (wired-OR connection).

Further, each line termination circuit 341 to 34m is not connected to the system bus 36 either. Each line termination circuit 341-3
4m is the corresponding packet communication signal processing integrated circuit 35
1 to 35m are connected via local buses 371 to 37m. That is, each packet communication signal processing integrated circuit 351 to 35m is ultimately connected to each line termination circuit 34.
The distance is controlled from 1 to 34 m. Call control processing is also performed by each packet communication signal processing integrated circuit 351-35m.

In addition, in this embodiment, each packet communication signal processing integrated circuit 351 to 35m and the corresponding line termination circuit 341 to
Audio signals are sent and received as analog signals over a distance of 34 meters. Therefore, analog processing circuits are used as the line termination circuits 341 to 34m.

Packet communication;;1 FIG. 7 shows a packet communication signal processing integrated circuit 39 (
351-35m).

In FIG. 7, the three packet communication signal processing integrated circuits include an analog/digital converter and a digital/analog converter (hereinafter referred to as AD) that follow the oversampling method.
- separated from a DA converter > 40, a digital signal processor (DSP) 41 and a phase locked loop (PLL) circuit 42;

The synchronization signal SYN and the clock signal CLK are signals synchronized with the communication network, and are applied to the phase-locked loop circuit 42 from outside the subscriber circuit package 30. The phase-locked loop circuit 42 generates a new synchronization signal SYNCP synchronized with these synchronization signals SYN and clock signal CLK;
The generated synchronization signal SYNCP and clock signal CLKCP are supplied to the digital signal processing processor 41, and the clock signal CLKSHP is supplied to the AD-D.
A converter 40 is supplied.

The analog audio signal AIN input from the line termination circuit (341 to 34m) is sampled at high speed in the AD-DA converter 40 based on the clock signal CLKSMP, converted to a digital signal DC, and sent to the digital signal processing processor 4■. Supplied. Conversely, the digital signal DI output from the digital signal processor 41 is converted to the clock signal CL in the AD-DA converter 40.
It is converted into an analog signal AOLIT based on KSMP and supplied to the line termination circuit.

The digital signal processing processor 41 provides an address bus AB, a bidirectional data path D B, and a signal line for a write enable signal WE to the microprocessor so that it can be controlled by a microprocessor (31) not shown. , a signal line for a continuous output enable signal OE, and a signal line for a chip enable signal CE.

Further, ports related to parallel data input PI and parallel data output PO are connected to the digital signal processing processor 41, and the ports related to parallel data input PI and parallel data output PO are connected to the digital signal processing processor 41. ! It is connected to the termination circuits 341 to 34m, and is configured to input and output data necessary for call control processing, testing, maintenance, monitoring, etc.

Furthermore, the digital signal processor 41 has serial output data SO, busy signal BSY, Signal lines for transmitting serial input data SI and reception request signal RREQ are connected.

In addition, these three signal processing integrated circuits for packet communication are ■
It is possible to send and receive packet data with simple steps, ■
It is designed to ensure that the S/N ratio does not deteriorate even through analog/digital conversion and digital/analog conversion, and (2) to be able to control the line termination circuit.

This packet communication signal processing integrated circuit 39 is
■A serial port for transmitting and receiving packet data; ■An AD/DA converter 30 that follows the oversampling method;
■A phase-locked lube circuit 42 that generates a clock signal etc. that is synchronized with a clock signal etc. supplied from a communication network;
It is characterized by the provision of a parallel port for controlling the line termination circuits {341 to 34m}.

Regarding feature (2), the reception configuration and transmission configuration will be explained separately. Note that the serial interface in the switch interface circuit 32 also has a configuration similar to that of the interface with three processing integrated circuits. AD-DA converter 40 according to oversampling method regarding feature ■
does not have a unique structure, so I will not discuss the horizontal precepts in detail. The phase lock loop circuit 42 regarding feature (2) will be described in detail below. The interface section of the parallel boat with respect to feature (2) also does not have any particular characteristics, but a tentative explanation will be provided below.

8 is a block diagram showing a detailed example of the phase-locked loop circuit 42 shown in FIG. 7, and FIG. 9 is a timing chart of each part thereof.

As is well known, this phase filter circuit 42 includes a phase difference detector 45, a low pass filter (LPF) 46,
It includes a voltage controlled oscillator (VCO) 47 and a frequency divider 48. In addition, a shift register circuit 49, two invert gates 50 and 51, and an AND gate 52
It is equipped with

The voltage controlled oscillator 47 outputs a clock signal CLKCP (FIG. 9(D)) to the digital signal processing processor 41.
) is formed by oscillation. This clock signal CLKC
P is divided by a predetermined number by the frequency divider 48 to obtain A
Clock signal CLKS for D-DA converter 40
}IP (FIG. 9(E)) is formed and output, and is also provided to the phase difference detector 45. Phase difference detector 4
5 is a clock signal CLK synchronized with the network (Fig. 9 (B)).
〉〉 is also given, and the phase difference detector 45 generates a pulse according to the phase difference between these clock signals CLKS}4P and CLK. This phase difference pulse is converted into a DC signal by a low-pass filter 46, and then given to a voltage-controlled oscillator 47 as an oscillation frequency control signal. I am trying to synchronize it with the signal CLK. The synchronization signal SYN (Figure 9(A)) is the clock signal CL.
It has a pulse width equivalent to one evening lock of K, and a frequency twice the band of the analog audio signal. The phase-locked loop circuit 42 outputs a synchronization signal SYN to the digital signal processing processor 4l in synchronization with this synchronization signal SYN.
The synchronizing signal SYN is input as data to the shift register circuit 49, and the clock signal CLKCP is inverted via the invert gate 50, thus forming the clock signal CLKCP.
The opposite-phase clock signal is applied to the shift register circuit 49 as a shift clock signal. The output of a certain stage of the four shift register circuits (FIG. 9 shows the second stage) is directly given to the AND gate 52, and the output shifted by one stage more is inverted via the invert gate 51. The output synchronization signal SYNCP is applied to the AND gate 52. Thus, the output synchronization signal SYNCP having a pulse width of one clock of the clock signal CLKCP is obtained from the AND gate 52.

Note that FIG. 9(F) shows the data timing for the digital signal processing processor 41 at that time.

The reason why the phase-locked loop circuit 42 is included in the integrated circuit 39 is to use the output of the synchronization signal generator synchronized with the network to achieve some simplification and synchronization. This is because, if this circuit is provided outside the integrated circuit, a serious problem of crosstalk will arise due to the processing of high frequency signals.

Serial P-2 Interface Next, the serial reception interface of the serial interface configuration of the digital signal processor 4l, which is one of the features of this embodiment, will be explained.

Here, FIG. 10 is a block diagram showing the configuration of the serial reception interface, and FIG. 11 is a timing chart of each part thereof.

This serial reception interface 55 is composed of a D-type flip-flop circuit 56, AND gates 57 and 58, a shift register circuit #I 59, a latch circuit 860, a three-state buffer 7 circuit 61, and an RS flip-flop circuit 62. The received packets are converted into parallel data and supplied to the internal data bus 63 and then supplied to the original processing section as the digital signal processing processor 41.

This digital signal processing processor 41 (see FIG. 7) has a switch interface circuit that includes a reception request compensation signal RREQ (FIG. 11 (B)) that becomes active when it is desired to input baguette data to this digital signal processing processor 41. 32. This reception request signal RRE
Q is applied to the data terminal of D-type flip-flop circuit #156.

The clock terminal of the D-type flip-flop 1 circuit 56 is connected to a clock pulse signal CKSCN (FIG. 11) having the same period (hereinafter referred to as frame) as the synchronizing signal SYN (FIG. 11 (A)) shown in FIG. (C〉〉) is given.Thus, the reception request signal RREQ is supplied to the clock pulse signal CKSC in the D-type flip-flop circuit #156.
N, and the digital signal processing processor 41 as the reception request flag RRFG (FIG. 11 (D)).
The original processing unit of the processor is notified of the fact that there is a request to receive a packet from the outside, and the flag RRFG is given to the AND gates 57 and 58 as a passage control signal.

Shifted clock pulse signal SCK that passes through when the AND gate 57 opens and is applied to the shift register circuit 59
R (FIG. 11(F): For example, the above clock signal C
The latch pulse signal LP (see FIG. 11 (G )> is generated every predetermined number of bits that make the serial data meaningful and in synchronization with the shift clock pulse signal SCKR.

The shift register circuit 59 converts serial input into parallel output, and during packet reception operation, converts the serial reception data SI (see Fig. 11 (E:: Fig. 7)) into
It is accommodated inside by the shift clock pulse signal SCKR passed by the ANDG-1.57. The data thus taken into the five shift register circuits and converted into parallel outputs is applied to the data terminal of the latch circuit 60. The latch circuit 60 latches the outputs of the five shift 1 register circuits based on the latch pulse signal LP output from the AND gate 58, and outputs a latch output L.
AT (Fig. 1 (H)) is supplied to the three-state buffer circuit 61.

Further, the output (LP) of the AND gate 58 is given to the set terminal of the RS flip-flop circuit 62, and at the same time as the latch circuit 60 latches the output of the shift 1 register circuit #159, the RS flip-flop circuit 62 is set to the set terminal. It is designed so that RS flip-flop circuit 62
The Q output of is the reception completion flag RAKFG (Fig.
J〉〉, and the digital signal processing processor 3
Notify the central processing unit 1 that reception of a part of the packet has been completed.

When the flag RAKFG becomes active, the central processing unit of the digital signal processor 41 sends a source enable signal SRCEN (Fig. 11 (■)) indicating that the signal source measurement is ready for acquisition. Activate.The source enable signal SRCEN connects the control terminal of the three-state buffer circuit 6■ and the RS
It is applied to the reset terminal of the flip-flop circuit 62. When the source enable signal SRCEN becomes active, the output data of the latch circuit 60 is transferred to the internal data bus 63.
At the same time, the RS flip-flop 1 circuit 62 is reset, the reception completion flag RAKFG becomes inactive, and the next predetermined bit of data can be stored.

This operation is repeated until l packets worth of data are received.

Serial Line Interface Next, the serial transmission interface of the serial interface configuration of the digital signal processing processor 4, which is one of the features of this embodiment, will be described.

Here, FIG. 2 is a block diagram showing the outline of the serial transmission interface, and FIG. 13 is a timing chart of each part thereof.

This serial transmission interface 65 includes invert gates 66 and 71, and gates 67, 70, 73, 7
4 and 78, D-type flip-flop circuit 68, oven collector (or train) in-heart gate 69, RS
flip-flop circuits 72 and 77, latch circuit 75,
It consists of a shift register circuit 76, an oven collector (or drain) NAND gate 79, and an internal data bus 8.
0 (53) is converted into serial data and output as a transmission packet to the switch interface circuit 32.

The reception request signal "RREQ" (FIG. 3 (B)) described in connection with the serial reception interface 55 is also applied to the serial transmission interface 65. This is to stop the serial transmission operation during the serial reception operation. This is a kind of competition control. This reception request signal RREQ is inverted via an invert gate 1.66 and applied to an AND gate 67.

The transmission request flag SREQF (FIG. 13(C)) is activated by the main processing unit of the digital signal processing processor 4 when t packets of transmission packets have been accumulated in the memory within the digital signal processing processor 41. The transmission request flag SREQF is made inactive when the transmission of the packet is completed.
is and game l 67 and 70, invert gate 7
1 is given.

The busy signal BSY (Fig. 13 (D)) output from the Q output terminal of the RS flip-flop 1 circuit 72 is generated because the integrated circuit portions 351 to 35m are used in a multi-connection configuration as shown in Fig. 1. This is a necessary contention control signal, which is converted to an active low signal BSY* (* represents active port) via the open collector in-heart gate 1.69 and sent to other integrated circuits and the AND gate 67.
given to. In this way, when the integrated circuit portion is used in multiple configurations, it is necessary to perform competition control. For this reason, it is necessary to connect the bus terminals of each integrated circuit in a multi-wired-OR manner and pull them up using an external resistor (not shown).
1 scans the busy signal BSY* when transmitting baguette data, and if no integrated circuit is executing a transmission operation and the busy signal BSY* is "H", the busy signal BSY* is set to "°L". '° to prevent other integrated circuits from starting transmission operations, then transmit the packet,
When the transmission is completed, the busy signal BSY* is returned to "H II".

Clock pulse signal CKSCN (Figure 13(E))
has the same frame as the synchronizing signal SYNC (FIG. 13(A)) described above, and is applied to the clock terminal of the D-type flip-flop circuit B68. The output from 7 is sampled, and the Q output Q68 is connected to AND gates 70, 73, 74, and 78, and invert gates 1 and 7.
In addition, the digital signal processing processor 41 is given a transmission permission flag DACFG (FIG. 13 (F)).
Notifies the central processing unit of that the packet can be sent. According to the logical conditions of ANDG-1.67, the conditions for the transmission permission flag DACFG to become active are that there is a request to transmit a packet, there is no request to receive packet 1.
In addition, no other integrated circuits are transmitting packets.

The set terminal of the RS flip-flop circuit 72 has a transmission request flag SRQFG and a transmission permission flag SAKFG (
An AND output with Q68) is given from the AND gate 70, and an inverted signal of the transmission request flag SRQFG is given to the reset terminal of the flip-flop circuit 72 from the inverter gate 7l. As described above, the Q output of the RS flip-flop 1 circuit 72 is inverted via the oven collector invert gate 69 to generate the above-mentioned busy signal BS.
Output as Y*.

That is, when the transmission permission flag SAKFG becomes active, the RS flip-flop circuit 72 is set and the busy signal BSY* goes into the "LI1" state, notifying other integrated circuits that packet data is currently being transmitted.
When the transmission of packet data is completed, the transmission request flag SRQ is
When FG becomes inactive, the flip-flop 1 circuit 72 is reset and returns the busy signal BSY* to "H".

Destination enable signal DSTEN (Part ■
FIG. 3 (G>) shows what is provided from the digital signal processor 41 to the latch circuit 75 and the RS flip-flop circuit 77. Digital signal processing processor 41
When the central processing unit specifies the latch circuit 75 as the destination when executing a transfer command, the destination enable signal DSTEN becomes active, and at the same time, the RS flip-flop IIJ477 is reset. At this time, the Q output of the RS flip-flop 1 circuit 77 is output as a transfer permission flag COACFG (FIG. It remains inactive until loaded, and notifies the central processing section of the digital signal processor 41 that the latch circuit 75 is currently in use.

Shift clock pulse signal SCKS (Fig. 13 (J
)> is a signal that has the same number of pulses as the number of bits that make up a packet in one frame, and is a signal that has the same number of pulses as the number of bits that make up a packet, and the transmission permission flag SA
The signal is applied to the AND gate 74 which is opened by the KFG. The load pulse signal LDP (FIG. 13(I)) is applied to the AND gate 73 which is opened by the transmission permission flag SAKFG. The shift register circuit 76 is used for parallel input and serial output. During the packet data transmission operation, the load pulse signal LDP is applied from the AND game 1 73 at a specified timing, and the latch data of the latch circuit 75 is loaded (13th
See figure (H)>. Note that at the same time as this loading operation, the RS
The flip-flop circuit 77 is set, the transfer permission flag COACFG becomes active, and the central processing section of the digital signal processor 4l is notified that the latch circuit 75 has become empty. Furthermore, a shift clock signal SCI (S) is applied from the AND gate 74 at a specified timing, and the data in the shift register circuit 76 is serially output to the open collector AND gate 1.79.
(See Figure ■3 (K)).

A transmission enable signal SEN (FIG. 13(M)) is applied to the AND gate 78 from the central processing section.

The transmission enable signal SEN has a period of one frame and is active while the shift register circuit 76 is outputting packet data.

Therefore, when the transmission permission flag SAKFG becomes active, the output of the AND gate 78 opens the oven collector AND gate 79 at a prescribed timing. The serially converted bucket r-data is thus output to the switch interface circuit 32. In addition,
Serial transmission data soc. i Oven collector and game - 1. Since there are 7 outputs, an external resistor (not shown) is required.
It is necessary to pull it up.

This operation is repeated until data for buckets 1 to 1 are transmitted.

Parallel port interface FIG. 14 shows the parallel port interface in the digital signal processor 41-.

This interface 85 includes a latch circuit 86 and a three-state buffer circuit B87. Internal data bus 88 of digital signal processor 4■ (
53, 80) as the latch pulse signal L
It is latched at the timing of P↑ and output to the line termination circuit,
Parallel data from the line termination circuit is taken into the data bus 88 via the buffer circuit 87 which is opened in response to the source enable signal SRCENI.

(1) Since it is equipped with an oversampling AD-DA converter 40, the following effects can be obtained.

(1-1) Since it is installed only in the integrated circuit portion, the circuit scale of the subscriber circuit is reduced.

(1-2) Oversampling AD-DA
The converter 40 has a small analog circuit scale, and the processing precision required for analog elements is not high, so it is suitable for an analog/digital mixed integrated circuit (LSI).

Therefore, adjustment work becomes easier than before.

(2) Since it is equipped with a phase-locked lube circuit 42,
You can obtain the following effects.

(2-1) Oversampling AD-DA
Since the sampling clock phase of the converter 40 and the clock phase of the digital signal processing processor 4l are synchronized and the edges do not overlap, AD -
The S/N of the DA converter 40 can be changed. Integrated circuits, especially those with a CMOS configuration, have a large current flowing at the edge of the clock, and the sampling of the AD/DA converter 40 may be adversely affected by the influence of large changes in this current, but this can be prevented. This is an effect that occurs because of the

(2-2) Since there is no need to mount an oscillator for the clock of the digital signal processor 41-, the circuit scale of the subscriber circuit can be reduced.

(3) Since the digital signal processing processor 4l is equipped with a serial transmitting/receiving interface and a parallel interface having a contention control mechanism (the switch interface circuit is also configured to have a corresponding serial transmitting/receiving interface), the following effects can be achieved. can be obtained.

(3-1) Exchanges call processing information with the microprocessor 3l, and digital signal processor 41 controls the line termination circuit from the parallel output port based on the call processing information, and receives information on the line termination circuit from the parallel input port. By collecting data, the microprocessor 3L does not need to directly control the line termination circuit, so the interface between the microprocessor 31 and the line termination circuit can be removed as described above, simplifying the configuration and improving communication control. Easy steps.

(3-2) Since it has a serial transmission/reception interface with a contention control configuration, it is possible to use the three integrated circuits in a multi-connection configuration, and one bucket
・There is no need to provide a separate external competition circuit for transmission and reception.

(3-3) The oversampling AD-DA converter 40 normally performs the transformation of the sampling rate in several stages, but when the sampling rate is close to the Nyquis t frequency in the audio band, the digital A signal processing processor 41 can be utilized. In this way, the circuit scale of the AD-DA converter 40 can be reduced.

(3-4) The digital signal processing processor 41 can send and receive packets to and from the switch interface circuit 32 using a small amount of built-in memory, and temporarily store the packets. This eliminates the need for an external buffer memory, and as a result, eliminates the need for a direct memory access controller, which simplifies the configuration and makes transfer control easier than in the past.

Embodiment In the embodiment described above, the digital signal processing processor 41 sends a busy signal to control the conflict between the transmission operation and the reception operation.
Although the output of the switch interface 32 has been shown, a signal similar to this may be outputted by the switch interface group 32 for control.

[Effects of the Invention] As described above, according to the present invention, it is possible to perform simple, horizontal, and packet assembly/disassembly processing in which the S/N ratio is less likely to deteriorate through conversion between analog and digital input signals. Accordingly, it is possible to obtain a subscriber circuit of a subscriber exchange with improved processing capacity.

[Brief explanation of the drawing]

Fig. 3 is a block diagram showing an embodiment of the subscriber circuit of the subscriber exchange according to the present invention, Fig. 2 is an explanatory diagram showing the flow of voice signals in a packet communication network, and Fig. 3 is an explanatory diagram showing the packet format. 4 is a block diagram showing the conventional basic configuration of the subscriber circuit, FIG. 5 is a signal waveform diagram showing the process of generating packet 1 carried out by the subscriber circuit together with the transmission process, and FIG. FIG. 7 is a block diagram showing the side view of the packet communication signal processing integrated circuit of the above embodiment; FIG. 8 is a block diagram showing the detailed configuration of the phase loop circuit; FIG. 9 is a timing chart of each part, FIG. 10 is a block diagram showing the configuration of a serial reception interface in a digital signal processing processor of a signal processing integrated circuit for packet communication, FIG. 11 is a timing chart of each part, and FIG. FIG. 13 is a block diagram showing the configuration of the serial transmission interface of the digital signal processing processor, FIG. 13 is a timing chart of each part thereof, and FIG. 14 is a block diagram showing the structure of the parallel board 1 interface of the digital signal processing processor. 30...Subscriber circuit package, 3...Microprocessor, 32...Switch interface circuit, 3
31-33m...Subscriber line, 341-34m...Line termination circuit, 351-35m, 39...Packet 1/Communication signal processing integrated circuit, 40...AD-DA converter, 4 pieces ...Digital signal processing processor, 42...
・Phase-locked loop circuit.

Claims (2)

[Claims] (1) Voice signals are sent and received in the form of analog signals between multiple line termination circuits that perform termination processing for subscriber lines and corresponding subscriber termination circuits, and are used to assemble and receive packets.
a plurality of signal processing circuits for packet communication that perform disassembly, audio signal processing, control operation of the line termination circuit, and competition control between packet transmission operation and reception operation in synchronization with the network; It is provided in common to the circuits, and receives serial packet data directly given from any of the above packet communication signal processing circuits, performs interface processing, and outputs it to the switching circuit, and also outputs it from the above switching circuit. a switch interface circuit that serially outputs given packet data to the packet communication signal processing circuit related to its destination, and also performs competition control between packet reception and transmission operations; and each of the packet communication signal processing circuits described above. A subscriber circuit of a subscriber exchange, comprising: a central processing unit that controls the circuit. (2) Each of the above packet communication signal processing circuits has one
an oversampling analog/digital converter, an oversampling digital/analog converter, and a phase-locked loop circuit that generates a synchronization signal and a clock signal synchronized with a network; 2. The subscriber circuit of a subscriber exchange according to claim 1, further comprising a digital signal processing processor that executes processing assigned to the packet communication signal processing circuit.