KR950013113A - Transmitter for module communication under double ring structure - Google Patents

Abstract

The present invention relates to a transceiver for connecting the same functional modules according to the death-network interface standard of the broadband integrated telecommunications network recommended by the International Standards Organization (CCITT) by two rings. It is an object of the present invention to reduce the data processing time and the waiting time in the FIFO to be processed to a minimum, and in particular, to provide a transmission apparatus that minimizes cell transmission delay on the ring by preferentially processing the transmission of bypass cells over the self-cell.

In order to achieve the above object, the present invention provides a magnetic cell transmitter (1-1) for receiving and processing magnetic cell input data, a bypass cell transmitter (1-2) for bypass cell input data, and a signal arbitration unit (1-3). It is provided.

Description

Transmission device for module communication under double ring structure

Since this is an open matter, no full text was included.

1 is an overall block diagram of a transmission device for module communication under a double ring structure according to the present invention.

2 is a block diagram of a magnetic cell transmitter according to the present invention.

3 is a block diagram of a bypass cell transmitter according to the present invention.

* Explanation of symbols for main parts of the drawings

1-1: magnetic cell transmitter 1-2: bypass cell transmitter

1-3: Signal Arbitration Unit

Claims (3)

After storing 8-bit self-cell input data in its own FIFO, read it in 53-octet unit, convert it into 32-bit unit by attaching 3-octet header, and output the self-cell transmission data start signal together with the data. Magnetic cell transmission means (2-1) for generating the first and second ring magnetic cell transmission data write signals by checking which of the first and first rings is the transmission data in the two rings in the direction; After saving the 32-bit bypass cell input data from the receiver in its own FIFO, read it in 14 long words (53 octets) and output the bypass cell transmission data start signal together with the data in 32-bit units. Bypass cell transmitting means (2-2) for generating a first ring and second ring bypass cell transmission data write signal by checking which of the first ring and the second ring is transmitted to two rings, and the magnetic field. Outgoing Cell Transmitter 2-1 Receives the signals and output signals of the bypass cell transmitter 2-2 as input and mediates the first ring transmission data and the first ring transmission data and the first ring transmission data to the first ring if the signal is related to the first ring. And a signal mediation means (2-3) for outputting a write signal and transmitting a ring transmission data start signal, a ring 2 transmission data, and a ring 2 transmission data write signal to the second ring if the signal is related to the second ring. A transmitter for performing module communication. The magnetic cell transmitting means (1-1) receives a system clock and a reset signal, and the magnetic cell start signal and the magnetic cell input data are synchronized with the magnetic cell clock according to the input of the magnetic cell write signal. Programmable Almost Empty is received and outputs the magnetic cell output start signal and the magnetic cell output data as the magnetic cell read signal is applied. A 9-bit unit synchronous FIFO (2-1) having a built-in signal, a system clock and a reset signal are input, and an empty signal and a bypass cell transmitter operation signal are input from the bypass cell transmitter (1-2). The programmable maximum empty signal is received from the bit unit parallel synchronization FIFO (2-1), and the programmable maximum empty signal is TTL level 1, and the empty signal of the bypass cell transmitter 1-2 is In the tee state, and indicates that the bypass cell transmitter operation signal is not in operation, the counter circuit 2-2 which starts counting operation in synchronization with the system clock, the reset signal and the counter of the counter circuit 2-2 While receiving the output value, the self-cell read signal is continuously output to the 9-bit unit synchronous FIFO (2-1) while the counter output value is increased so that the stored self-cell start signal and the self-cell input data are read in synchronization with the system clock. The self-cell read signal generation circuit 2-4, the system clock and reset signal, the empty signal from the bypass cell transmitter 1-2 and the bypass cell transmitter operating signal, and receive the 9-bit unit in parallel synchronization. A programmable maximum empty signal is input from a FIFO 2-1, and a magnetic maximum read signal is input from the magnetic cell read signal generation circuit 2-4, and the programmable maximum empty signal is TTL level 1 (53 octets). this ) And the empty signal of the bypass cell transmitter 1-2 is empty and the in-operation signal is not in operation, an output signal and 32-bit output signal for starting 32-bit unit conversion by starting the operation. To generate the unit conversion and magnetic cell control signal to transmit the 32-bit data write signal, ring selection signal and section signal by transmitting the in-operation signal of the magnetic cell transmitter to the bypass cell transmitter 1-2. 53-octet magnetic cell output data and magnetic field from circuit 2-3, reset signal, 9-bit unit parallel synchronous FIFO 2-1, unit conversion and magnetic cell control signal generation circuit 2-3. Receives the cell output start signal and the output signal for 32-bit unit conversion, attaches the header of the highest 3 octets regardless of the data value to the frame synchronization related to the physical media connection of the physical layer to its cell. 32-bit units converted to 56 octets A transmitting apparatus for performing communication module comprising the ring selecting and outputting a magnetic cell transmission data and magnetic data cell transmission start signal circuit (2-6). The quadrature divider circuit (3) according to claim 1, wherein the receiving means (1-2) receives a system clock and a reset circuit and divides the system clock (62.5 MHz) into four to generate a four-division clock (15.625 MHz). 1), the bypass cell start signal and the bypass cell output data are input according to the input of the bypass cell write signal, and the 4 division clock, which is the output of the 4 divide circuit 3-1, is input, and an empty signal is separately installed. When the bypass cell input data is stored in one or more long words, a 33-bit unit parallel synchronous FIFO (3-2) outputs from TTL level 0 to 1, a reset signal, a signal in operation of the magnetic cell transmitter, and the four divider circuit ( 4-1) and the empty signal from the 33-bit unit synchronous FIFO (3-2), the empty signal is TTL level 1, and the self-cell transmitter is in operation. If not, the counter circuit (3-3) for performing the count in synchronization with the input divided clock; Bypass cell read signal generation circuit 3 which receives the output value of the counter circuit 3-3 as an input and continuously outputs the bypass cell read signal to the 33-bit unit parallel synchronous FIFO 3-2 while the counter output value is increased. -5), a 4-division clock and a reset circuit are input, an empty signal is input from the 33-bit unit synchronous FIFO 3-2, and the magnetic cell transmitter from the magnetic cell transmitter 1-1 is operated. When the signal is received and the empty signal is TTL level 1 and the signal in operation of the magnetic cell transmitter indicates that the magnetic cell transmitter 1-1 is not in operation, a 32-bit output signal is generated. And a bypass cell control signal generation circuit 3-4 that outputs a 32-bit data write signal, a ring selection signal, and an interval signal to the self-cell transmitter 1-1, indicating that it is in operation, and 33-bit unit parallel. 14 long words from the synchronous FIFO 3-2 and the bypass cell control signal generation circuit 3-4. A D flip-flop unit (3-6) for receiving bypass cell output data, bypass cell output start signal, 32-bit output signal, and reset signal and outputting bypass cell transmission data and bypass cell transmission data start signal in 32-bit units; Receives bypass cell output data while receiving 32-bit data write signal, ring select signal, and interval signal and checks whether a specific data bit of the first long word of bypass cell output data is 0 or 1, and if it is 0, bypasses ring 1 And a ring selection circuit (3-7) for outputting a cell transmission data write signal and outputting a ring 2 bypass cell transmission data write signal if it is 1. ※ Note: The disclosure is based on the initial application.