KR970024711A - Synchronous Control of Digital Voice Signal - Google Patents

Synchronous Control of Digital Voice Signal Download PDF

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Publication number
KR970024711A
KR970024711A KR1019950035109A KR19950035109A KR970024711A KR 970024711 A KR970024711 A KR 970024711A KR 1019950035109 A KR1019950035109 A KR 1019950035109A KR 19950035109 A KR19950035109 A KR 19950035109A KR 970024711 A KR970024711 A KR 970024711A
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KR
South Korea
Prior art keywords
data
parallel
serial
output
register
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KR1019950035109A
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Korean (ko)
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KR100211333B1 (en
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조용선
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정장호
엘지정보통신 주식회사
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Priority to KR1019950035109A priority Critical patent/KR100211333B1/en
Publication of KR970024711A publication Critical patent/KR970024711A/en
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Publication of KR100211333B1 publication Critical patent/KR100211333B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch

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  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

본 발명은 PCM 64K 데이타를 바이트 단위로 변환하여 동기를 맞추므로서 전송망에서 수신, 송신 클럭이 상이한 장치에 적당하도록 한 디지탈 음성신호의 동기 조절장치에 관한 것이다.The present invention relates to a synchronization control apparatus for digital voice signals that converts PCM 64K data into units of bytes to synchronize them so that the reception and transmission clocks of the transmission network are suitable for different devices.

이를 달성하기 위해 본 발명은 수신되는 직렬 데이타를 바이트 단위의 병렬 데이타로 변환하는 직렬/병렬 변환부와, 직렬/병렬 변환부에서 출력되는 병렬 데이타와 제1병렬 레지스터에서 출력되는 데이타를 수신 프레임 펄스에 따라 선택하여 출력하는 제1데이타 선택부와, 제1데이타 선택부에서 선택된 데이타를 순차 시스트시키는 제1병렬 레지스터와, 송신 클럭과 프레임 펄스에 따라 데이타 래치신호를 발생하는 카운터와, 카운터의 출력신호를 선택신호로 함께 제1병렬 레지스터에서 출력되는 데이타와 제2병렬 레지스터에서 출력되는 데이타를 선택하여 출력하는 제2데이타 선택부와, 제2데이타 선택부에서 출력되는 데이타를 순차 시프트시켜 출력하는 제2병렬 레지스터와, 제2병렬 레지스터에서 출력되는 병렬 데이타를 직렬 데이타로 변환하는 병렬/직렬 변환부와, 병렬/직렬 변환부에서 출력되는 직렬 데이타를 송신 클럭에 동기시켜 출력하는 플립플롭을 구비한다.In order to achieve this, the present invention provides a serial / parallel conversion unit for converting received serial data into parallel data in units of bytes, and parallel frame output from the serial / parallel conversion unit and data output from the first parallel register. A first data selector for selecting and outputting according to the first data; A second data selector which selects and outputs data output from the first parallel register and data output from the second parallel register together with a signal as a selection signal, and sequentially outputs the data output from the second data selector; Converts parallel data output from the second parallel register and the second parallel register into serial data. And a flip-flop for outputting the serial data output from the parallel / serial conversion section in synchronization with the transmission clock.

Description

디지탈 음성신호의 동기 조절장치Synchronous Control of Digital Voice Signal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 의한 디지탈 음성신호의 동기 조절장치 구성도.1 is a block diagram of a synchronization control device for digital voice signals according to the present invention.

Claims (1)

수신되는 직렬 데이타를 바이트 단위의 병렬 데이타로 변환하는 직렬/병렬 변환수단과, 상기 직렬/병렬 변환 수단에서 출력되는 병렬 데이타와 제1병렬 레지스터에서 출력되는 데이타를 수신 프레임 펄스에 따라 선택하여 출력하는 제1데이타 선택수단과, 상기 제1데이타 선택수단에서 선택된 데이타를 순차 시스트시키는 제1병렬 레지스터와, 송신 클럭과 프레임 펄스에 따라 데이타 래치신호를 발생하는 카운터와, 상기 카운터의 출력신호를 선택신호로 하여 제1병렬 레지스터에서 출력되는 데이타와 제2병렬 레지스터에서 출력되는 데이타를 선택하여 출력하는 제2데이타 선택수단과, 상기 제2데이타 선택수단에서 출력되는 데이타를 순차 시프트시켜 출력하는 제2병렬 레지스터와, 상기 제2병렬 레지스터에서 출력되는 병렬 데이타를 직렬 데이타로 변환하는 병렬/직렬 변환수단과, 상기 병렬/직렬 변환수단에서 출력되는 직렬 데이타를 송신 클럭에 동기시켜 출력하는 플립플롭으로 구성된 것을 특징으로 하는 디지탈 음성신호의 동기 조절장치.Serial / parallel conversion means for converting received serial data into parallel data in units of bytes, and parallel data output from the serial / parallel conversion means and data output from the first parallel register are selected and output according to a received frame pulse. A first data selecting means, a first parallel register for sequentially sifting the data selected by the first data selecting means, a counter for generating a data latch signal in accordance with a transmission clock and a frame pulse, and an output signal of the counter. Second data selecting means for selecting and outputting the data output from the first parallel register and the data output from the second parallel register, and a second parallel output for sequentially shifting and outputting the data output from the second data selecting means. Register and parallel data output from the second parallel register as serial data. And a flip-flop for converting the parallel / serial conversion means for converting and the serial data outputted from the parallel / serial conversion means in synchronization with a transmission clock. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950035109A 1995-10-12 1995-10-12 Adjustment synchronization device of digital voice signal KR100211333B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950035109A KR100211333B1 (en) 1995-10-12 1995-10-12 Adjustment synchronization device of digital voice signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950035109A KR100211333B1 (en) 1995-10-12 1995-10-12 Adjustment synchronization device of digital voice signal

Publications (2)

Publication Number Publication Date
KR970024711A true KR970024711A (en) 1997-05-30
KR100211333B1 KR100211333B1 (en) 1999-08-02

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KR1019950035109A KR100211333B1 (en) 1995-10-12 1995-10-12 Adjustment synchronization device of digital voice signal

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KR100211333B1 (en) 1999-08-02

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