KR970056141A - Speed conversion circuit for E1 / T1 matching - Google Patents

Speed conversion circuit for E1 / T1 matching Download PDF

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Publication number
KR970056141A
KR970056141A KR1019950052875A KR19950052875A KR970056141A KR 970056141 A KR970056141 A KR 970056141A KR 1019950052875 A KR1019950052875 A KR 1019950052875A KR 19950052875 A KR19950052875 A KR 19950052875A KR 970056141 A KR970056141 A KR 970056141A
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KR
South Korea
Prior art keywords
channel
data
kbps
rate
selector
Prior art date
Application number
KR1019950052875A
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Korean (ko)
Other versions
KR0185872B1 (en
Inventor
이성배
Original Assignee
유기범
대우통신 주식회사
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Application filed by 유기범, 대우통신 주식회사 filed Critical 유기범
Priority to KR1019950052875A priority Critical patent/KR0185872B1/en
Publication of KR970056141A publication Critical patent/KR970056141A/en
Application granted granted Critical
Publication of KR0185872B1 publication Critical patent/KR0185872B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

본 발명은 E1/T1 정합용 속도변환회로에 관한 것으로, 시험을 위하여 T1 또는 E1속도의 데이타를 루프백할 수 있는 루프백 테스트부(21); 루프백이 해제된 상태에서 상기 루프백 테스트부로부터 T1 또는 E1 데이타를 SHWFS, SHWCLK클럭에 따라 수신하여 채널번호에 의해 선택된 채널의 타임슬롯을 추출하고, 채널번호에 의해 선택된 채널의 타임슬롯상에 송신 채널데이타를 실어준 후 상기 루프백 테스트부로 출력하는 채널선택부(22); 64Kbps 채널속도의 송신 데이타를 E1 속도의 송신채널 데이타로 변환해 주는 송신속도변환부(24); T1/E1선택신호에 따라 T1일 경우 64Kbps의 채널데이타를 56Kbps의 채널 데이타로 변환하여 T1속도로 상기 채널 선택부로 출력하는 T1/E1선택부(32); 및 상기 채널선택부(23)로부터 E1속도의 수신채널 데이타를 64Kbps의 수신채널 데이타로 변환하는 수신속도 변환부(25)가 FPGA로 구현되어 있다.The present invention relates to an E1 / T1 matching speed conversion circuit, comprising: a loopback test unit 21 capable of looping back data of T1 or E1 speed for a test; Receives T1 or E1 data from the loopback test unit according to the SHWFS and SHWCLK clocks in the loopback released state, extracts the timeslot of the channel selected by the channel number, and transmits the transmission channel on the timeslot of the channel selected by the channel number. A channel selector 22 which loads data and outputs the data to the loopback test unit; A transmission rate conversion section 24 for converting transmission data of 64 Kbps channel rate into transmission channel data of E1 rate; A T1 / E1 selector 32 for converting channel data of 64 Kbps into 56 Kbps channel data and outputting the channel data to the channel selector at T1 speed in the case of T1 according to the T1 / E1 selection signal; And a receiving rate converter 25 for converting the receiving channel data of the E1 rate from the channel selector 23 into the receiving channel data of 64 Kbps.

Description

E1/T1 정합용 속도변환회로Speed conversion circuit for E1 / T1 matching

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 E1/T1정합용 속도변환회로를 도시한 블럭도.2 is a block diagram showing a speed conversion circuit for E1 / T1 matching according to the present invention.

Claims (1)

시험을 위하여 T1 도는 E1속도의 데이타를 루프백할 수 있는 루프백 테스트부(21); 루프백이 해제된 상태에서 상기 루프백 테스트부로부터 T1 또는 E1 데이타를 SHWFS, SHWCLK클럭에 따라 수신하여 채널번호에 의해 선택된 채널의 타임슬롯을 추출하고, 채널번호에 의해 선택된 채널의 타임슬롯상에 송신 채널데이타를 실어준 후 상기 루프백 테스트부로 출력하는 채널선택부(22); 64Kbps 채널속도의 송신 데이타를 E1 속도의 송신채널 데이타로 변환해 주는 송신속도변환부(24); T1/E1선택신호에 따라 T1일 경우 64Kbps의 채널데이타를 56Kbps의 채널 데이타로 변환하여 T1속도로 상기 채널선택부로 출력하는 T1/E1선택부(32); 및 상기 채널선택부(23)로부터 E1속도의 수신채널 데이타를 64Kbps의 수신채널 데이타로 변환하는 수신속도 변환부(25)가 FPGA로 구현되어 있는 것을 특징으로 하는 E1/T1 정합용 속도변환회로.A loopback test unit 21 capable of looping back data of T1 or E1 speed for testing; Receives T1 or E1 data from the loopback test unit according to the SHWFS and SHWCLK clocks in the loopback released state, extracts the timeslot of the channel selected by the channel number, and transmits the transmission channel on the timeslot of the channel selected by the channel number. A channel selector 22 which loads data and outputs the data to the loopback test unit; A transmission rate conversion section 24 for converting transmission data of 64 Kbps channel rate into transmission channel data of E1 rate; A T1 / E1 selector 32 for converting channel data of 64 Kbps into 56 Kbps channel data and outputting the channel data to the channel selector at T1 speed in the case of T1 according to the T1 / E1 selection signal; And a reception speed converter (25) for converting the reception channel data of the E1 rate from the channel selector (23) into the reception channel data of 64 Kbps. The speed conversion circuit for E1 / T1 matching. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052875A 1995-12-20 1995-12-20 Speed change circuit for junction of e1/t1 KR0185872B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950052875A KR0185872B1 (en) 1995-12-20 1995-12-20 Speed change circuit for junction of e1/t1

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950052875A KR0185872B1 (en) 1995-12-20 1995-12-20 Speed change circuit for junction of e1/t1

Publications (2)

Publication Number Publication Date
KR970056141A true KR970056141A (en) 1997-07-31
KR0185872B1 KR0185872B1 (en) 1999-05-15

Family

ID=19441977

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950052875A KR0185872B1 (en) 1995-12-20 1995-12-20 Speed change circuit for junction of e1/t1

Country Status (1)

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KR (1) KR0185872B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100293502B1 (en) * 1998-06-15 2001-07-12 공비호 Signal interface framer
KR100292201B1 (en) * 1998-06-17 2001-11-22 박종섭 Recognition method of distinguishing 1 and T 1 framers in communication system
KR100328432B1 (en) * 1997-12-19 2002-06-24 박종섭 E1/t1 transmitting apparatus for packet data in mobile communication system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101028148B1 (en) * 2010-11-11 2011-04-08 주식회사 한국코아엔지니어링 Cable duct for information and communications

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328432B1 (en) * 1997-12-19 2002-06-24 박종섭 E1/t1 transmitting apparatus for packet data in mobile communication system
KR100293502B1 (en) * 1998-06-15 2001-07-12 공비호 Signal interface framer
KR100292201B1 (en) * 1998-06-17 2001-11-22 박종섭 Recognition method of distinguishing 1 and T 1 framers in communication system

Also Published As

Publication number Publication date
KR0185872B1 (en) 1999-05-15

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