KR940023307A - Data transmission and reception circuit through subhighway - Google Patents

Data transmission and reception circuit through subhighway Download PDF

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Publication number
KR940023307A
KR940023307A KR1019930005420A KR930005420A KR940023307A KR 940023307 A KR940023307 A KR 940023307A KR 1019930005420 A KR1019930005420 A KR 1019930005420A KR 930005420 A KR930005420 A KR 930005420A KR 940023307 A KR940023307 A KR 940023307A
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KR
South Korea
Prior art keywords
data
time slot
transmission
clock
output
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KR1019930005420A
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Korean (ko)
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KR960002845B1 (en
Inventor
정의석
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박성규
대우통신 주식회사
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Priority to KR1019930005420A priority Critical patent/KR960002845B1/en
Publication of KR940023307A publication Critical patent/KR940023307A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

본 발명은 전전자 교환기의 서브하이웨이를 통하여 데이타를 송수신하는 회로에 관한 것으로, 특히 임의의 타임슬롯을 선택하여 데이타를 송수신하는 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for transmitting and receiving data over a subhighway of an electronic switchboard, and more particularly to a circuit for transmitting and receiving data by selecting an arbitrary time slot.

본 발명은 프레임 동기신호(FS)와 4Mbps의 클럭(CLK)을 계위받아 2Mbps의 클럭과 프레임 동기신호(FS)를 출력하는 클럭 분주수단(12)과, 타임슬롯 지정 데이타를 입력받아 타임슬롯 지정번호를 출력하는 타임슬롯 지정수단(11)과, 상기 타임슬롯 지정데이타를 입력받아 타임슬롯 지정신호를 출력하는 타임 슬롯지정수단(11)과, 상기 타임슬롯지정수단(11)의 출력과 상기 클럭 분주수단(12)의 출력을 입력받아 2Mbps, 256Kbps, 및 64Kbps 클럭과 타임슬롯 동작신호를 출력하는 타임슬롯 선택수단(13)과, 상기 타임슬롯 선택수단(13)의 출력을 이용하여 서브하이웨이에서 수신되는 수신 데이타를 변환하여 데이타 송수신 회로팩으로 전달하는 수신 데이타 출력수단(14)과, 상기 타임슬롯 선택수단(13)의 출력을 이용하여 데이타 송수신 회로팩으로부터의 송신데이타를 변환하여 서브하이웨이로 전달하는 송신데이타 출력수단(15)을 구비한다.According to the present invention, a clock divider 12 for outputting a clock of 2Mbps and a frame synchronous signal FS by receiving the frame synchronizing signal FS and a clock of 4 Mbps CLK and time slot designation is received. A time slot designation means 11 for outputting a number, a time slot designation means 11 for receiving the time slot designation data and outputting a time slot designation signal, an output of the time slot designation means 11, and the clock; In the subhighway using the output of the dividing means 12 and the output of the time slot selecting means 13 and outputting the 2 Mbps, 256 Kbps and 64 Kbps clock and time slot operation signal. The transmission data from the data transmission / reception circuit pack is converted by using the reception data output means 14 for converting the received reception data to be transmitted to the data transmission / reception circuit pack, and the output of the time slot selecting means 13. Transmission data output means 15 for transmitting to the subhighway is provided.

Description

서브하이웨이를 통한 데아타 송수신 회로Deata transmit / receive circuit through subhighway

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

도면은 본 발명의 전체 구성도.Figure is the overall configuration of the present invention.

Claims (5)

프레임 동기신호(FS)와 4Mbps의 클럭(CLK)을 계위받아 2Mbps의 클럭과 프레임 동기신호(FS)를 출력하는 클럭 분주수단(12)과, 타임슬롯 지정 데이타를 입력받아 타임슬롯 지정신호를 출력하는 타임슬롯 지정수단(11)과, 상기 타임슬롯 지정수단(11)의 출력과 상기 클럭 분주수단(12)의 출력을 입력받아 2Mbps, 256Kbps, 및 64Kbps 클럭과 타임슬롯 동작신호를 출력하는 타임슬롯 선택수단(13)과, 상기 타임슬롯 선택수단(13)의 출력을 이용하여 서브하이웨이에서 수신되는 수신 데니타를 변환하여 데이타 송수신 회로팩으로 전달하는 수신 데이타 출력수단(14)과, 상기 타임슬롯 선택수단(13)의 출력을 이용하여 데이타 송수신 회로팩으로부터의 송신데이타를 변환하여 서브하이웨이로 전달하는 송신데이타 출력수단(15)을 구비하는 것을 특징으로 하는 서브하이웨이를 통한 데이타 송수신 회로.A clock divider 12 for receiving a frame synchronization signal FS and a clock of 4 Mbps CLK and outputting a clock of 2 Mbps and a frame synchronization signal FS; and receiving a time slot designation data and outputting a time slot designation signal. A time slot specifying means 11, an output of the time slot specifying means 11 and an output of the clock divider 12, and a time slot for outputting 2 Mbps, 256 Kbps, and 64 Kbps clock and time slot operation signals A receiving data output means 14 for converting the receiving denita received from the subhighway using the output of the selecting means 13, the timeslot selecting means 13, and transferring the received data to a data transmission / reception circuit pack; Through the subhighway, characterized in that it comprises a transmission data output means 15 for converting the transmission data from the data transmission and reception circuit pack by using the output of the selection means 13 and forwarded to the subhighway. Data transmission and reception circuit. 제1항에 있어서, 상시 수신 데이타 출력수단(14)은, 상기 타임슬롯 선택수단(13)으로부터 제공되는 2Mbps 클럭을 이용하여 서브하이웨이로부터 수신되는 2Mbps의 수신 데이타를 8비트 병렬 데이타로 변환하는 1차 수신 데이타 변환수단(141)과, 상기 타임스롯 선택수단(13)에서 제공되는 256Kbps 클럭과 타임슬롯 동작신호를 이용하여 상기 1차 수신 데이타 변환수단(141)의 출력을 래치하는 2차 수신 데이타 변환수단(142)과, 상기 타임슬롯 선택수단(13)에서 제공되는 64Kbps 클럭을 이용하여 상기 2차 수신 데이타변환수단(142)에서 래치된 8비트 병렬 데이타를 64Kbps의 직렬 데이타로 변환하여 출력하는 3차 수신 데이타 변환수단(143)을 구비하는 것을 특징으로 하는 서브하이웨이를 통한 데이타 송수신 회로.2. The receiver according to claim 1, wherein the constant reception data output means 14 converts 2 Mbps received data received from the subhighway into 8-bit parallel data using the 2 Mbps clock provided from the time slot selecting means 13. Secondary received data for latching the output of the primary received data converting means 141 using the secondary received data converting means 141 and the 256 Kbps clock and the timeslot operation signal provided by the time slot selecting means 13. Converts 8-bit parallel data latched by the secondary receive data conversion means 142 into serial data of 64 Kbps using the conversion means 142 and the 64 Kbps clock provided by the time slot selecting means 13. And a tertiary receiving data converting means (143). 제1항에 있어서, 상기 송신 데이타 출력수단(15)은, 상기 타임슬롯 선택수단(13)에서 제공되는 64Kbps 클럭을 이용하여 데이타 송수신 회로팩으로부터의 송신 데이타를 8비트 병렬 데이타로 변환하는 1차 송신 데이타 변환수단(151)과, 상기 타임슬롯 선택수단(13)에서 제공되는 256Kbps 클럭을 이용하여 상기 1차 송신 데이타 변환수단(151)의 출력을 래치하는 2차 송신 데이타 변환수단(152)과, 상기 타임슬롯 선택수단(13)에서 제공되는 2Mbps 클럭과 타임슬롯 동작신호를 이용하여 상기 2차 송신 데이타 변환수단(152)에서 래치된 8비트 병렬데이타를 직렬 데이타로 변환하여 출력하는 3차 송신 데이타 변환수단(153)을 구비하는 것을 특징으로 하는 서브하이웨이를 통한 데이타 송수신 회로.The transmission data output means (15) according to claim 1, wherein the transmission data output means (15) converts transmission data from a data transmission / reception circuit pack into 8-bit parallel data using a 64 Kbps clock provided by the time slot selection means (13). Transmission data conversion means 151 and secondary transmission data conversion means 152 for latching the output of the primary transmission data conversion means 151 using a 256 Kbps clock provided from the time slot selection means 13; And tertiary transmission for converting and outputting 8-bit parallel data latched by the secondary transmission data conversion means 152 into serial data using a 2 Mbps clock and a time slot operation signal provided by the time slot selection means 13. And a data conversion means (153). A data transmission / reception circuit via a subhighway. 제1항에 있어서, 상기 타임슬롯 지정수단(11)은, 상기 타임슬롯 선택수단(13)에서 제공하는 타임슬롯 클럭을 이용하여 타임슬롯 클럭으로 선택된 타임슬롯 지정신호를 출력하도록 구성된 것을 특징으로 하는 서브하이웨이를 통한 데이타 송수신 회로.2. The time slot designation means (11) according to claim 1, characterized in that the time slot designation means (11) is configured to output a time slot designation signal selected as a time slot clock using the time slot clock provided by the time slot selection means (13). Data transmission and reception circuit over subhighway. 제1항에 있어서, 상기 타임슬롯 지정수단(11)이 입력받는 타임슬롯 지정데이타는 5비트의 병렬 데이타인 것을 특징으로 하는 서브하이웨이를 통한 데이타 송수신 회로.2. The data transmission / reception circuit via the subhighway according to claim 1, wherein the timeslot designation data input by the timeslot designation means is 5-bit parallel data. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930005420A 1993-03-31 1993-03-31 Data transmission circuit via subhighway KR960002845B1 (en)

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Application Number Priority Date Filing Date Title
KR1019930005420A KR960002845B1 (en) 1993-03-31 1993-03-31 Data transmission circuit via subhighway

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Application Number Priority Date Filing Date Title
KR1019930005420A KR960002845B1 (en) 1993-03-31 1993-03-31 Data transmission circuit via subhighway

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KR940023307A true KR940023307A (en) 1994-10-22
KR960002845B1 KR960002845B1 (en) 1996-02-26

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