KR0185872B1 - Speed change circuit for junction of e1/t1 - Google Patents

Abstract

The present invention relates to a speed conversion circuit for E1 / T1 matching, the loopback test unit 21 for looping back the data of the T1 or E1 speed for testing; Receive T1 or E1 data from the loopback test unit according to the SHWFS clock while loopback is released, extract the time slot of the channel selected by the channel number, and load the transmission channel data on the time slot of the channel selected by the channel number. A channel selector 22 outputting the loopback test unit to the loopback test unit; A transmission rate conversion section 24 for converting transmission data of 64 Kbps channel rate into transmission channel data of E1 rate; A T1 / E1 selector 23 for converting channel data of 64 Kbps into 56 Kbps channel data and outputting the channel data to the channel selector at T1 speed in the case of T1 according to the T1 / E1 selection signal; And a receiving rate converter 25 for converting the receiving channel data of the E1 rate from the channel selector into a receiving channel dada of 64 Kbps.

Description

Fast conversion for E1 / T1 matching

1 is a schematic diagram showing a speed conversion chip for matching E1 / T1.

2 is a block diagram showing an E1 / T1 matching fast conversion circuit according to the present invention.

3 is a detailed block diagram of a loopback test unit and a channel selector in FIG.

4 is a detailed block diagram of a transmission rate converter and an E1 / T1 selector in FIG.

FIG. 5 is a detailed block diagram of a reception speed converter of FIG. 2.

* Explanation of symbols for main parts of the drawings

10: speed conversion chip 11: mode setting register cell

21: Loopback test unit 22: Channel selector

23: T1 / E1 selector 24: Transmission speed converter

25: reception speed converter 41, 51: serial-to-parallel converter

45, 53: parallel-line transfer machine 43: D flip-flop

47: 3-phase buffer 49: Oagate

The present invention relates to a speed conversion circuit for converting or inversely converting DSO-class (typically 64Kbps) channels into sub-highway (SHW) with DSI-class (1.544Mbps or 2.048Mbps) speed in digital electronic switching system. will be.

In an overnight digital electronic switch, voice signals are PCM-modulated to be 64 Kbps DSO signals, and when 24 channels are multiplexed, they become 1.544 Mbps T1 (also known as DS1) signals, and when 32 channels are multiplexed, 2.01 Mbps E1 ( Also known as DS1E). In addition, when using the T1 method for data transmission such as a computer using the voice channel, since the robbed-bit signaling is used, only 56 Kbps is used and the E1 method is used. 64Kbps can be used.

On the other hand, in the digital electronic switch, 32 channels having a 64Kbps rate are multiplexed to form a 2.048Mbps subhighway signal (SHW), and 32 subhighways are multiplexed to form a 1K capacity highway signal (HW). And E1 or T1 can be used to transmit data from the trunk shaft or on the truck. As is well known, it accepts 24 channels of T1 and has a transmission speed of 1.544 Mbps, and transfers 32 channels of E1 and 2.048 Mbps. Have speed.

Therefore, if you want to extract a specific channel from E1 or T1 data such as IPC or No.7 signal processing, you need to apply E1 or T1 data rate as the channel speed. It is called Rate Conversion (RA).

1 is a diagram illustrating a conventional speed conversion chip which extracts a characteristic channel from E1 or T1 data or inserts a channel signal at a specific channel position on E1 or T1 data. In FIG. 1, when data of 2.01 Mbps E1 or 1.544 Mbps T1 is input to the RA dedicated chip 10, a channel of 64 Kbps or 56 Kbps is selected and output according to the channel selection signal and the E1 / T1 selection signal. do. In this case, one RA dedicated chip 10 may extract any eight channels, and on the contrary, may convert and output any eight-channel data into data of T1 or E1 speed. Then, a T1 / E1 selection signal for selecting T1 or E1 data and a channel selection signal for specifying eight channels are set in the mode setting register cell 11, and corresponding to the setting value of the mode setting register cell 11. Extract the channel.

However, since the conventional speed conversion chip is implemented as one dedicated chip, even if one wants to use only one channel in order to simplify the route, a chip supporting 8 channels has to be purchased. In case of use, there is a problem that the whole should be exchanged even if one channel fails. In particular, since such a dedicated chip is expensive, it would be highly desirable to be able to implement it using a field programmable gate array (FPGA) which is widely used in the market.

Accordingly, the present invention has been made to solve the above-mentioned problems, and provides an E1 / T1 matching speed conversion circuit implemented using an FPGA to implement a speed conversion (RA) function at a low cost. have.

In order to achieve the above object, the E1 / T1 matching speed conversion apparatus according to the present invention includes a loopback test unit capable of looping back data of T1 or E1 speed for a test;

Receives T1 or E1 data from the loopback test unit according to the SHWFS and SHECLK clocks, extracts the timeslot of the channel selected by the channel number, and transmits the transmission channel on the timeslot of the channel selected for the channel number while the loopback is released. A channel selector which loads data and outputs the data to the loopback test unit; A transmission rate conversion unit for converting transmission data of 56 Kbps or 64 Kbps channel speed into transmission channel data of T1 or E1 speed; A T1 / E1 selector for selecting T1 or E1 transmission channel data according to a T1 / E1 selection signal and outputting the data to the channel selector; And a reception rate conversion unit for converting the reception channel data of the T1 or E1 rate into the reception channel data of 56 Kbps or 64 Kbps from the channel selection unit.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

The speed conversion circuit according to the present invention includes a loopback test unit 21 capable of looping back data of T1 or E1 speed for testing as shown in FIG. 2; Receives T1 or E1 data from the fraudulent loopback test unit 21 according to the SHWFS and SHWLK clocks, extracts the timeslot of the channel selected by the channel number in the loopback canceled state, and displays the timeslot of the channel selected by the channel number. A channel selector 22 outputting the transmission channel data to the loopback test 21 and converting the transmission data of the 64 Kbps channel rate into the transmission channel data of the E1 rate; T1 Receive rate conversion for converting channel data of 64 Kbps into channel data of 56 Kbps in case of T1 according to the / E1 selection signal and converting receiving channel data of E1 speed into receiving channel data of 64 Kbps from the channel selector 22 at T1 speed. Part 25 is implemented in an FPGA.

FIG. 3 is a detailed circuit diagram of the loop-fold test unit 21 and the channel selector 22 in FIG. 2, where the loopback test unit 21 is composed of two end gates and one ogate. Reference numeral 22 is made up of ten endgates, three noahgates, one ogate and one inverter.

4 is a detailed block diagram of the transmission speed converter 24 and the T1 / E1 selector 23 in FIG. 2, and the parallel-to-parallel converter 41, the D flip-flop 43, the parallel-to-parallel converter 45, and FIG. It consists of an upper buffer 47 and an oragate 49.

FIG. 5 is a detailed block diagram of the reception speed converter 25 in FIG. 2 and includes a serial-to-parallel converter 51 and a parallel-to-parallel converter 53. As shown in FIG.

Referring to the operation and effect of the E1 / T1 matching speed conversion circuit of the present invention configured as described above are as follows.

First, when the loopback command is input for the test under the control of the controller (not shown), the loopback test unit 21 loops back the received SHW data to the transmission SHW data, and transmits data transmitted from the channel selector 22. Loops back to the received data of the channel selector 22. In this looped state, the channel side can receive the data transmitted by itself and compare the data to check the state of the line.

Referring to FIG. 3, the loopback test unit 21 actually selects the value of 'SHWRXD' as the value of 'SHW_RXD' according to the 'SHWLOOP' signal determined by the controller (not shown). Incoming subhighway (SHW) is connected, and if the value of 'SHW_TXD' is selected, the 'SHW_TXD' is used as the loopback mode to inflow again, and the controller uses the 'SHWLOOP' value as the loopback during the initial test.

The channel selector 22 extracts or inserts data into a time slot of a corresponding channel number (0 to 31; 5 bits) from the subhighway data input in accordance with the frame synchronization signal SHWFS and the clock SHWCLK of the subhighway. This is to be described in more detail with reference to FIG. That is, the channel selector 22 uses the divided clocks generated based on the subhighway clock (SHWCLK), 128KHz, 64KHz, 32KHz, 16KHz, and 8KHz to select 0 times using CHO to CH4 externally selected. Select each channel from 31 to 31. Here, CHO to CH4 have a value of OOOOO to 11111, and are combined with each divided block to generate the signals '/ CHSELL' and '/ CHSELH' which are kept 'low' and 'high' only during the corresponding channel. do. This signal is used to generate a clock that selects only the corresponding channel of the actual subhighway to select data.

The transmission rate conversion unit 24 is for converting transmission data of 64 Kbps channel speed into transmission channel data of E1 speed, which will be described in more detail with reference to FIG. 4. That is, the transmission rate converting section 24 carries one channel data (SDLTXD) of 64 Kbps to the subhighway transmission data (SHWTXD) of the channel selected by the channel selecting section 23. To this end, first, the transmission data (SDLTXD) flowing in 64 Kbps is latched in units of 8 bits to the flip-flop 43 through the serial-to-parallel converter 41. The latched data is serially converted into a clock signal valid only in the selected channel by the parallel serial converter. At this time, the 'SHWTXD' output from the parallel converter 45 is output only in the corresponding channel using 3 (47). On the other hand, the serial-to-parallel converter 41, the D flip-flop 43, and the parallel-to-parallel converter 45 perform a corresponding function using a clock synchronized with the subhighway clock SHWCLK.

According to the T1 / E1 selection signal, the T1 / E1 selector 23 converts a channel of 64Kbps into a channel of 56Kbps in case of T1 and transmits it to T1 of 1.544Mbps, and outputs an E1 signal of 2.048Mbps in case of E1. Referring to FIG. 4, the T1 / E1 selector 23 performs a speed conversion function at a speed of 64 Kbps in the case of T1 and a speed of 56 Kbps in the case of E1 according to the selection signal 'CLKSEL'. For this purpose, according to the T1 / E1 selection signal 'CLKSEL', the output data of the parallel-to-serial converter 45 is valid as it is when T1 is selected, and when the E1 is selected, the D flip-flop 43 of the transmission speed converter 24 is selected. In step 8, the last bit of the 8-bit data linked to the serial-to-parallel converter 45 is set to '1' unconditionally to generate 'SHWTXD'. In addition, 'CLLCSEL' is used to provide 'SDLCLK' signals in T1 and E1 states.

The reception speed converter 25 converts the channel selector 22 from the channel selection unit 22 into channel data of 64 Kbps of the reception channel data on the E1 speed. This will be described in more detail with reference to FIG. 5. That is, when the reception data (SHW___RXD) of the subhighway flows into the serial-to-parallel converter 51 in the normal mode in the loopback test unit 21, the clock signal generated only in the channel selected by the channel selector 22. After parallel latching 8 bits per channel in parallel, the parallel-to-serial converter 53 generates the 8-bit data at a clock of 64 Kbps synchronized with 'SHWCLK' to generate 'SDLRXD'.

As described above, rate conversion can be achieved at low cost by simply implementing a rate adaptation (RA) function using an FPGA to extract or insert DSO channel data from data at a speed of T1 or E1 according to the present invention. have.

Claims (1)

A loopback test unit 21 capable of looping back data of T1 or E1 speed for testing; Receives T1 or E1 data from the loopback test unit according to the SHWFS and SHWCLK clocks in the loopback released state, extracts the time slot of the channel selected by the channel number, and transmits the transmission channel on the timeslot of the channel selected by the channel number. A channel selector 22 which loads data and outputs the data to the loopback test unit; A transmission rate conversion section 24 for converting transmission data of 64 Kbps channel rate into transmission channel data of E1 rate; A T1 / E1 selector 23 for converting 64 Kbps channel data into 56 Kbps channel data and outputting the channel data to the channel selector at T1 speed in the case of T1 according to the T1 / E1 selection signal; And a reception converting section (25) for converting the receiving channel data of the E1 rate from the channel selecting section (23) into the receiving channel data of 64 Kbps in an FPGA.