KR100293502B1 - Signal interface framer - Google Patents

Signal interface framer Download PDF

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Publication number
KR100293502B1
KR100293502B1 KR1019980022832A KR19980022832A KR100293502B1 KR 100293502 B1 KR100293502 B1 KR 100293502B1 KR 1019980022832 A KR1019980022832 A KR 1019980022832A KR 19980022832 A KR19980022832 A KR 19980022832A KR 100293502 B1 KR100293502 B1 KR 100293502B1
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South Korea
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framer
signal
fdl
matching
built
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KR1019980022832A
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Korean (ko)
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KR19980065033A (en
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공비호
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공비호
주식회사 아이티
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/08—Protocols for interworking; Protocol conversion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/18—Multiprotocol handlers, e.g. single devices capable of handling multiple protocols

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE: A signal interface framer is provided to simply interface T1 and E1 signals and perform a remote control by embedding an FDL(Facility Data Link) and performing T1 and E1 signal processes in one element. CONSTITUTION: A T1/E1 framer(10) satisfy T1 and E1 signal interface standards, and provides a data interface clock, an enable signal, and an input and output signal for selectively performing a control using an external FDL. An embedded DPLL(Digital Phase-Locked Loop)(30) generates a clock for the T1/E1 signal interface. An embedded FDL device(20) performs a remote control of an in-service state.

Description

신호정합 프레이머Signal Matching Framer

본 발명은 T1(1544 kbps)급 신호와 E1(2048 kbps)급 신호를 정합하고 이에 따른 데이터, FDL(Facillity Data Link), 시그널링을 처리하기 위한 신호정합 프레이머장치에 관한 것이다.The present invention relates to a signal matching framer device for matching T 1 (1544 kbps) and E 1 (2048 kbps) signals and processing data, FDL (FDL), and signaling accordingly.

기존의 신호정합 프레이머는 도 1에 도시된 바와 같이, T1급 프레이머(1)와 E1급 프레이머(2)가 각각 분리되어 있어 T1과 E1신호를 정합하고자 할 경우,In the conventional signal matching framer, as shown in FIG. 1, when the T 1 framer 1 and the E 1 framer 2 are separated, respectively, and want to match the T 1 and E 1 signals,

T1프레이머(1)와 E1프레이머(2)를 AGEB 내장시키거나, 단독으로 사용되고 있는 경우는 T1프레이머(1)를 E1프레이머(2), 또는 그 반대로 상호교체해 주어야 하는 단점이 있다.If the T 1 framer 1 and the E 1 framer 2 are AGEB-embedded or used alone, the T 1 framer 1 must be replaced with the E 1 framer 2 or vice versa.

또한 기존에 T1프레이머(1)와 E1프레이머(2)를 단독 사용 또는 모두 내장시켜 사용하고 있는 경우 FDL 정합기능을 내장하고 있지 않아 프레이머(1)(2)를 통한 인서비스상태의 대국제어(Remate control)가 불가능하게 되며, 대국제어가 가능하게 하기 위해서는 외부에 FDL용 정합소자(3)를 추가로 설치하여야만 하였다In addition, when the T 1 framer (1) and the E 1 framer (2) are used alone or in combination, the FDL matching function is not built in. Therefore, the international language of the in-service state through the framer (1) (2) is used. (Remate control) became impossible, and in order to enable international language, additional matching device (3) for FDL had to be installed outside.

즉 기존에는 T1프레이머(1) 또는 E1프레이머(2)를 단독으로 사용하여 신호 정합시 상호 교체해 주어야 하거나 모두 내장시켜야 하는 단점이 있으며 또한 FDL기능이 내장되어 있지 않아 대국제어가 불가능하고 이를 위해서는 별도의 FDL 정합소자(3)를 추가 설치하여야 하는 단점이 있다.That is, conventionally, T 1 framer (1) or E 1 framer (2) must be used alone or interchanged when matching signals, or both must be built-in. Also, because FDL function is not built-in, international language is impossible. There is a disadvantage in that an additional FDL matching element 3 must be additionally installed.

본 발명은 FDL기능을 내장하고 하나의 소자에서 T1급 신호와 E1급 신호처리가 가능한 T1/E1겸용 프레이머를 제공하므로써 T1및 E1신호를 간단히 정합하고 대국제어가 가능하도록 한 것으로,The present invention integrates the FDL function and simply match the one of the device by providing a T 1 grade signal E 1 grade signal processing is possible T 1 / E 1 Combine framer T 1 and E 1 signal and to enable powers control In that,

내부에 T1/E1변환용 로직과 FDPLL(Full Digital Phase-Locked Loop)를 내장하여 N×56, N×64 클릭을 발생하고 FDL정합기능을 내장하여 T1/E1을 위한 대국제어가 가능하며 데이터 및 시그널링의 처리를 위한 T1/E1겸용 프레이미를 고속집적회로로 제작하므로써 이루어진다.Built-in logic for T 1 / E 1 conversion and FDPLL (Full Digital Phase-Locked Loop) generates N × 56, N × 64 clicks, and has built-in FDL matching function to provide international language for T 1 / E 1 This is achieved by fabricating a T 1 / E 1 frame for high-speed integrated circuits for data and signaling.

도 1 은 기존의 신호정합 프레이머 구성도1 is a block diagram of a conventional signal matching framer

도 2 는 본 발명의 신호정합 프레이머 구성도2 is a block diagram of a signal matching framer according to the present invention

1 : T1프레이머 2 : E1프레이머1: T 1 Framer 2: E 1 Framer

3 : FDL정합소자 10 : T1/E1프레이머3: FDL matching element 10: T 1 / E 1 framer

20 : 내장F이소자 30 : DPLL장치20: built-in F device 30: DPLL device

도 2 는 본 발명의 신호정합 프레이머 구성도로써, 본 발명은 T1급 신호와 E1급 신호를 처리할 수 있는 T1/E1프레이머(10)와, 대국제어가 가능한 내장 FDL소자(20)를 구비하는 한편 Digital Phase-Locked Loop(DPLL)장치(30)를 구비하여 이루어진다.2 is as a signal matching framer block diagram of the present invention, the present invention is T 1 class signal and E and T 1 / E 1 framer 10 to handle first class signal, a built-in powers controllable FDL element (20 A digital phase-locked loop (DPLL) device 30 is provided.

여기서 T1/E1프레이머(10)는 T1과 E1신호 정합 규격인 ITU(International Telecommunication Union)규격을 만족하게 되고 외부신호선으로 데이터 정합용 클럭과 인에이블신호, 그리고 선택적으로 외부의 FDL을 이용한 제어를 위하여 입출력 신호를 제공한다.Herein, the T 1 / E 1 framer 10 satisfies the International Telecommunication Union (ITU) standard, which is a T 1 and E 1 signal matching standard, and uses an external signal line to provide a data matching clock, an enable signal, and optionally an external FDL. Provides input and output signals for the used control.

그리고 내장된 DPLL장치(30)는 T1신호와 E1신호의 정합을 위한 N×56, N×64용 클럭을 제공하게 된다.The built-in DPLL device 30 provides N × 56 and N × 64 clocks for matching the T 1 and E 1 signals.

T1/E1프레이머(10)는 사용자선택에 의해 T1/E1의 변환이 가능하며 인서비스 상태에서도 내장된 내장 FDL소자(20)를 이용하여 대국의 상태를 제어 및 감시가 가능하다.The T 1 / E 1 framer 10 can convert T 1 / E 1 by user selection, and can control and monitor the state of the power station by using the built-in FDL element 20 even in the in-service state.

따라서 T1/E1신호정합을 위하여 기존과 같이 장치의 상호교체 또는 두장치를 동시에 탑재시킬 필요가 없으며 또한 내장 FDL소자(20)에 의해 대국제어가 가능하므로 별도의 FDL을 위한 장치의 설치가 불필요하다.Therefore, for T 1 / E 1 signal matching, there is no need to replace devices or mount two devices at the same time as in the past, and because the international language is possible by the built-in FDL element 20, it is possible to install a device for a separate FDL. It is unnecessary.

특히 T1/E1프레이머(10)는 고집적 VLSI 기술을 이용하여 제작하므로써 저소비 전력을 구현할 수 있게 된다.In particular, the T 1 / E 1 framer 10 may be manufactured using a highly integrated VLSI technology to realize low power consumption.

그리고 T1/E1프레이머(10)는 내장된 데이터 패턴 발생기를 이용하여 아웃 오브 서비스상태에서의 자체 진단기능수행도 가능하다.In addition, the T 1 / E 1 framer 10 may perform a self-diagnosis function in an out-of-service state by using a built-in data pattern generator.

본 발명은 T1/E1신호정합이 가능한 T1/E1프레이머를 사용하여 신호 정합시 장치의 교체나 두장치를 모두 내장시켜야 하는 불편이 없으며, 또한, FDL정합기능을 내장하여 인서비스 상태의 대국제어가 가능한 효과가 있다.The present invention has no inconvenient to be built all the changes, or the devices at the time of signal matching by using the T 1 / E 1 signal matching the possible T 1 / E 1 framer devices, and, in the service state to embed FDL Interface Function International languages are possible.

Claims (2)

T1과 E1신호 정합규격을 만족하고 데이터 정합용 클럭과 인에이블신호 및 선택적으로 외부의 FDL를 이용한 제어를 위해 입출력신호를 제공하는 T1/E1프레이머(1)(2)와, T1/E1신호정합을 위한 클럭을 발생시키는 내장 DPLL 장치(30)와, 인서비스상태의 대국제어를 가능케하고 내장된 내장 FDL소자(20)를 고집적 VLSI화 시킨 것을 특징으로 하는 신호정합 프레이머.And T 1 and E 1 signal T 1 / E 1 framer that provides input and output signals to meet the matching specifications and data registration for the clock and enable signals and optionally to the control using the external FDL (1) (2), T A signal matching framer comprising a built-in DPLL device (30) for generating a clock for 1 / E 1 signal matching and a highly integrated VLSI of an embedded FDL device (20) that enables international languages in an in-service state. 제 1 항에서, T1/E1프레이머(1)(2)를 내장된 패턴발생기로 아웃 오브 서비스상태의 자체 진단기능을 제공하는 것을 특징으로 하는 신호정합 프레이머.The signal matching framer according to claim 1 , wherein the T 1 / E 1 framer (1) (2) is provided with a built-in pattern generator to provide a self-diagnosis function of an out of service state.
KR1019980022832A 1998-06-15 1998-06-15 Signal interface framer KR100293502B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970056141A (en) * 1995-12-20 1997-07-31 유기범 Speed conversion circuit for E1 / T1 matching

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970056141A (en) * 1995-12-20 1997-07-31 유기범 Speed conversion circuit for E1 / T1 matching

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