KR100421951B1 - parallel VC3 mapping circuit of the transferring system - Google Patents

Abstract

The present invention provides an ELB for receiving and storing a line clock signal and a line data signal from the DS3 hierarchy device in a V3 mapping system for mapping a DS3 signal of a digital signal (3) hierarchy device to a synchronous digital hierarchy (SDH) device. An elastic buffer), a latch block portion for latching a plurality of DS3 signals stored in the ELB into parallel signals in units of bytes by one address signal, a read address generator for generating a read address signal of the latch block portion, and the read A VC3 counter that applies a control signal according to the STM-n format to the address generator and controls the V3 mapping function overall, and an overhead of the STM-n format for DS3 data latched in the latch block unit according to the control signal of the VC3 counter. Provided is a parallel VC3 mapping circuit of a transmission system including a mux part for muxing a signal, a stuff signal, and 8-bit line data.

The circuit of the present invention as described above reduces the number of intermediate clocks by storing all DS3 signals input as 1-bit serial data in a line in a buffer and mapping them to upper levels by byte units using byte clock signals. This improves circuit reliability and eliminates the need for intermediate bit clock circuits.

Description

Parallel VC3 mapping circuit of the transferring system

The present invention relates to a parallel VC3 mapping circuit of a transmission system, and in particular, by storing all DS3 signals input as 1-bit serial data in a line in a buffer and VC3 mapping the upper level by byte unit using a byte clock signal. A parallel VC3 mapping circuit in a transmission system that reduces the number of intermediate clocks and significantly improves circuit characteristics.

In general, the transmission technology began with the spiral carrier in the 1910s, developed into the analog transmission technology, and in the form of a digital transmission technology. Later, in the 1960s, the digital transmission technology started to develop a T1 channel bank with a 1.544 Mbps transmission rate. It was. Moreover, the digital transmission method has been developed into an optical transmission method using an optical cable as a transmission medium. As the point-to-point type optical communication has evolved into an optical communication network, as a result of standardization of a broadband integrated information network (B-ISDN), It is called synchronous transmission.

Here, while making a synchronous optical network (SONET) connection standard to enable the construction of the network by the optical communication systems, this is also referred to as the network node interface (NNI) standard of B-ISDN. Synchronized digital hierarchy (SDH) has been generalized for use, and a synchronous transmission scheme is a transmission scheme based on this synchronous digital hierarchy. In particular, a new transmission method for configuring and transmitting the synchronous digital step signals is called a synchronous transmission method, compared to a conventional communication method for constructing similar synchronous digital step signals and transmitting them through a baseband.

Therefore, through the synchronous multiplexing process, the existing DS-1 to DS-4 hierarchical signals are multiplexed into STM-n signals and reconfigured through an ADM device having a synchronous branch coupling function or a DACS device having a synchronous cross linking function. Synchronous transmission can be referred to as a series of synchronous processing processes transmitted and reproduced through a synchronous optical communication network.

Next, referring to FIG. 1, the VC (virtual container) mapping device 70 of the optical transmission system using the SDH multiplexing method as described above is used. The optical signal data mapped from the lower level to DS3 (44.736 Mbps) is serial-bit unit. A DS3 hierarchical unit 71 for outputting a digital signal; an elastic buffer 72 (hereinafter referred to as ELB) for receiving and storing up to 128 bits of a line clock signal and a line data signal from the DS3 hierarchical unit 71; A mux 79 for muxing the DS3 signal stored in the ELB 72 in units of bits and a read address generator for generating a read address signal so that the mux 79 muxes the data of the ELB 72 ( 80), S (serial) / P (parallel) converter 73 for converting the serial data output from the MUX 79 in 1-bit unit into 8-bit data in byte unit, and the lead address generator 80 Enable signal, which is a control signal according to the STM-n format, VC3 counter 74 for controlling the V3 mapping function and the latch 75 for latching data output from the S / P converter 73 in units of 8 bits, and the latch 75 And a muxing unit 76 which muxes the data stored in the STM-n format overhead signal, stuff signal, and 8-bit line data according to the control signal of the VC3 counter 74.

Then, at one end of the muxing unit 76, an OH generator 77 for generating an overhead signal under the control of the VC3 counter 74 and a stuff generator 78 for generating a stuff (STUFF) signal. Is connected.

On the other hand, referring to the operation of the mapping device of the conventional optical transmission system as described above, when the optical data is first mapped to the SDH device 81 which is a higher level device, the DS3 level device unit 71 serializes the DS3 signal according to the line clock signal. Are output to the ELB 72 by 1 bit. Then, the ELB 72 receives the DS3 signal input from the DS3 hierarchical unit 71 one bit at a time and stores up to 128 bits, for example. At this time, the VC3 counter 74 applies a bit control signal to the read address generator 80, and accordingly, the read address generator 80 inputs the selection control signal to the mux 79. Then, the MUX 79 serially converts the corresponding signal among the 128-bit DS3 signals stored in the ELB 72 according to the selection control signal of the read address generator 80 into bit by bit using a bit clock signal. Output to S / P converter 73. The S / P converter 73 converts the DS3 signal input bit by bit from the ELB 72 via the mux 79 into an 8 bit signal in byte units and outputs it to the latch 75. Accordingly, the latch 75 latches the DS3 signal output from the S / P converter 73 in units of bytes according to the byte clock signal and outputs the signal to the mux unit 76.

At this time, the muxing unit 76 muxes the DS3 signal latched in units of bytes to the latch 75 by the control signal according to the STM-n format configuration input from the VC3 counter 74, SDH device ( 81). For example, the muxing unit 76 muxes the signal generated from the OH generating unit 77 in the overhead portion of the STM-n format, and muxes and maps the DS3 signal latched in the latch 75 in the data portion.

However, the mapping apparatus of the conventional optical transmission system as described above uses the MUX 79 and the read address generator 80 to map data from the DS3 hierarchy device 71 to the SDH device 81 which is a higher hierarchy. Since the data must be mapped again in byte units after processing, the component circuits for bit unit data processing are separately required, which increases the manufacturing cost of the mapping circuit. In addition, the conventional mapping apparatus has a problem that the processing speed of the data is slowed because the DS3 signal must be processed in units of bits and then in units of bytes in order to map the DS3, thereby degrading the performance of the mapping apparatus.

Accordingly, the present invention has been invented to solve the above-described general problems, and the DS3 signal input as serial data of 1 bit in the line is sequentially stored in the buffer, and the VC3 in higher order by byte unit using the byte clock signal. By mapping, the number of intermediate clocks can be reduced, thereby improving the data mapping process speed, thereby providing a parallel VC3 mapping circuit of a transmission system that can significantly improve circuit characteristics.

Another object of the present invention is to provide a parallel VC3 mapping circuit of a transmission system that directly maps DS3 by byte, thereby eliminating the need for using an intermediate bit clock circuit, thereby significantly reducing the manufacturing cost of the V3 mapping circuit.

The present invention for achieving the above object in the VC3 mapping system for mapping the DS3 signal of the DS3 hierarchy unit to the SDH (synchronous digital hierarchy) device, the line clock signal and the line data signal from the DS3 hierarchy unit receives and stores ELB (Elastic buffer); Read-out of a plurality of DS3 signals from the ELB and a data output unit for simultaneously outputting 8-bit DS3 signals sequentially shifted by 1 bit, and a read address of a DS3 signal sequentially shifted by 1 bit by the data output unit. A latch block portion including a parallel mux portion for outputting a parallel signal of 8 bits per address output from the generator, and a latch output in parallel in units of bytes by the parallel mux portion; A read address generator for generating a read address signal of the latch block portion; A VC3 counter for applying a control signal according to STM-n format to the lead address generator and controlling overall VC3 mapping function; Provided is a parallel VC3 mapping circuit of a transmission system including a mux part for mushing DS3 data latched in the latch block part into an STM-n format overhead signal, stuff signal, and 8-bit line data according to a control signal of a VC3 counter. .

1 is a block diagram illustrating a VC3 mapping circuit of a conventional transmission system.

2 is a block diagram illustrating the present invention.

3 is an explanatory diagram for explaining a latch block portion of the present invention.

<Detailed Description of Codes>

1: DS3 hierarchy 2: ELB

3: latch block portion 4: lead address generator

5: VC3 counter 6: musbu

7: Data output unit 8: Parallel mux unit

9: latch 10a-h: 1-8 mux

11: OH generator 12: stuff generator

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

As shown in Fig. 2, the circuit of the present invention includes a DS3 hierarchical unit 1 for outputting optical signal data mapped to DS3 (44.736 Mbps) from a lower hierarchical unit in serial bit units, and from the DS3 hierarchical unit 1; An ELB 2 that receives and stores a line clock signal and a line data signal, for example, up to 128 bits, and a plurality of DS3 signals stored in the ELB 2 are parallel signals in units of bytes by one address signal. A latch block portion 3 for reading and latching a parallel signal of bits, a read address generator 4 for generating a read address signal of the latch block portion 3, and the read address generator 4 A control signal according to the STM-n format and controls the V3 mapping function as a whole, and DS3 data latched to the latch block part 3 according to the control signal of the VC3 counter 5. Overhead and Stuff Signals in STM-n Format And a multiplexer unit (6) which Muxing to 8-bit data line.

As shown in FIG. 3, the latch block unit 3 simultaneously outputs a plurality of DS3 signals, for example, 8-bit DS3 signals shifted sequentially by 128 bits from the ELB 2, as shown in FIG. Parallel output for outputting a data output unit 7 and a DS3 signal sequentially shifted by one bit by the data output unit 7 in the form of a parallel signal of 8 bits per address output from the read address generator 4. The mux section 8 and the latch 9 are output in parallel by the unit by the parallel mux section 8.

In addition, the parallel mux unit 8 is composed of 1-8 mux 10a-h which mux each DS3 signal sequentially sequenced by 1 bit from the data output unit 7.

Here, each of the muxes 10a-h of the parallel mux unit 6 muxes all DS3 signals of the data output unit 7 in a sequence of 1 bit, for example, the first mux 10a. When DS3 (0) is input to the DS3, the DS3 (1), which is increased by one bit from the DS3 (0) of the first mux 10a, is muxed at the same time as the second mux 10b. In this manner, the last eighth mux 10h of the one read address signal of the read address generator 4 is muxed by the DS3 (7) which is increased 7 bits from the DS3 (0) of the first mux 10a.

At one end of the mux unit 6, an OH generator 11 for generating an overhead signal under the control of the VC3 counter 5 and a stuff generator 12 for generating a stuff (STUFF) signal are provided. Is connected.

Next, the operation and effect of the mapping circuit of the present invention as described above will be described.

In the circuit 13 of the present invention, when the optical data is first mapped to the SDH device 14, which is a higher level device, the DS3 level device unit 1 converts the DS3 signal into ELB 2 in serial by 1 bit according to the line clock signal. Output Then, the ELB 2 receives the DS3 signal input from the DS3 hierarchy 1 by 1 bit and stores up to 128 bits, for example. Then, the ELB 2 inputs all of the stored 128-bit DS3 data to the data output section 7 of the latch block section 3. Therefore, the data output unit 7 always has 128 bits of DS3 simultaneously.

At this time, the VC3 counter 5 applies the read address control signal to the read address generator 4 according to the J1 time signal, and accordingly the read address generator 4 sends the address selection control signal to the latch block unit 3. Input to parallel mux part 8, respectively. Then, each of the 1-8 muxes 10a-h of the parallel mux unit 8 is sequentially sequentially one bit from the data output unit 7 according to one read address signal of the read address generator 4. Each of the DS3 shifted signals is muxed and output to the latch 9.

For example, when the first mux 10a of the parallel mux unit 8 muxes DS3 " 7 " from the data output unit 7, the second mux 10b at the same lead address as the first mux 10a. ) Is "8", the third mux 10c is "9", the fourth mux 10d is "10", the fifth mux 10e is "11", and the sixth mux 10f is "12", the seventh mux 10g output "13", and the eighth mux 10h output "14" to the latch 9 at the same time.

If the first mux 10a of the parallel mux unit 8 muxes DS3 " 20 " from the data output unit 7, the second mux (in the same lead address as the first mux 10a). 10b) is "21", the third mux 10c is "22", the fourth mux 10d is "23", the fifth mux 10e is "24", and the sixth mux 10f. Denotes "25", the seventh mux 10g outputs "26", and the eighth mux 10h outputs "27" to the latch 9 at the same time.

Therefore, 8 bits of DS3 data shifted by 1 bit are simultaneously inputted in parallel to the input terminal of the latch 9. Then, the latch 9 of the latch block part 3 latches DS3 data output in parallel from the respective muxes 10a-h of the parallel mux part 8 in byte units so that the mux part 6 )

At this time, the mux unit 6 muxes the DS3 signal latched in units of bytes in the latch 9 by the control signal according to the STM-n format configuration input from the VC3 counter (5) SDH device ( 14). For example, the mux unit 6 muxes the signal generated from the OH generating unit 11 in the overhead portion of the STM-n format, and muxes and maps the DS3 signal latched in the latch 9 in the data portion.

Therefore, according to the present invention, since the DS3 signal is processed in bytes in parallel, there is no need for a separate circuit such as a mux, a read address generator, and an S / P converter for bit clock processing as in the conventional circuit.

As described above, the present invention sequentially stores the DS3 signal input as 1-bit serial data in a line in a buffer and maps the number of clocks in the intermediate stage by mapping VC3 to upper level by byte unit using the byte clock signal. This has the advantage of significantly reducing circuit reliability.

According to the present invention, since DS3 is directly mapped in a byte unit, there is no need to use an intermediate bit clock circuit, and accordingly, the manufacturing cost of the V3 mapping circuit is also significantly reduced.

Claims (3)

In the VC3 mapping system for mapping the DS3 signal of the DS3 hierarchy unit to the SDH (synchronous digital hierarchy) device, An ELB (Elastic buffer) for receiving and storing a line clock signal and a line data signal from the DS3 hierarchy device; Read-out of a plurality of DS3 signals from the ELB and a data output unit for simultaneously outputting 8-bit DS3 signals sequentially shifted by 1 bit, and a read address of a DS3 signal sequentially shifted by 1 bit by the data output unit. A latch block portion including a parallel mux portion for outputting a parallel signal of 8 bits per address output from the generator, and a latch output in parallel in units of bytes by the parallel mux portion; A read address generator for generating a read address signal of the latch block portion; A VC3 counter for applying a control signal according to STM-n format to the lead address generator and controlling overall VC3 mapping function; Parallel VC3 mapping of the transmission system comprising a mux unit for muxing the DS3 data latched in the latch block unit into an STM-n format overhead signal, stuff signal, and 8-bit line data according to a control signal of a VC3 counter. Circuit. delete The parallel VC3 mapping circuit of claim 1, wherein the mux comprises a plurality of muxes capable of muxing a DS3 signal into a parallel signal in units of bytes.