KR100289574B1 - Multiplexing and demultiplexing device between DS-3 signal and management unit signal in synchronous transmission device - Google Patents

Abstract

The present invention relates to a multiplexing and demultiplexing device between a DS-3 signal and a management unit signal (AU-3) in a synchronous transmission device. The present invention relates to a clock unit switching unit, a senior box signal processing unit, a senior virtual box signal processing unit, and a management unit signal. It consists of a processing part and a preliminary overhead connection part.

Among the components of the present invention, the high box processing unit receives the encoded DS-3 signal, decodes it, and then synchronizes and outputs it as a C-3 signal, receives the C-3 signal, desynchronizes the encoded DS, and encodes the DS. Output with -3 signal. In addition, the preliminary overhead connection unit provides a means for connecting the predetermined preliminary overhead with an external device, and the high-level virtual box processing unit inserts a predetermined path overhead into the C-3 signal output from the high-level box processing unit to supply the VC-3. The signal is multiplexed into a signal and output as a C-3 signal after extracting the path overhead by receiving an aligned AU-3 signal.

Meanwhile, the management unit signal processing unit adds a predetermined management unit pointer to the VC-3 signal output from the high-level virtual box processing unit to generate an AU-3 signal, and outputs the AU-3 signal. Output with AU-3 signal.

At this time, the clock unit switching unit receives a clock signal from predetermined clock units, inspects the clock signal, selects a normal clock signal, and supplies the same to each component.

Description

A unit of multiplexing DS-3 signals to Administrative Unit-3 signals and of demultiplexing Administrative Unit-3 signals to DS-3 signals in synchronous communication equipments)

The present invention relates to a multiplexing and demultiplexing device between a DS-3 signal and a management unit signal (AU-3) in a synchronous transmission device. In particular, a DS-3 dependent signal having a transmission rate of 44.736 Mbps in a synchronous multiplex structure is DS-. 3->; High box signal (C-3)->; High virtual box signal (VC-3)->; Multiplexed along the multiplexing path of the management unit signal (AU-3) and output upward. Also, after detecting the high-virtual virtual box signal (VC-3) frame from the serial management unit signal (AU-3), the detected high-level virtual signal is detected. The present invention relates to an apparatus for processing and demultiplexing a path overhead of a box signal (VC-3) frame to extract, encode, and output the final DS-3 signal downward.

FIG. 1 is a basic network diagram of an optical subscriber transmission device, which is an example of a synchronous transmission device, and includes a main station (10: Central Office Terminal) and a remote station (11: Remote Terminal). At this time, the master station 10 is connected to each subscriber through a general switching line, a leased line, a local area network (LAN), and the like, and these subscribers are connected to the ordinary telephone subscriber or the leased line subscriber through the remote station 11. Connected with

The main station 10 and the remote station 11 constituting such an optical subscriber transmission device are connected by the optical path 12 to perform communication by light with each other. At this time, the communication by the light between the master station 10 and the remote station 11 is performed by using a synchronous transmission method. In the synchronous transmission method, each signal is multiplexed according to a synchronous digital hierarchy (SDH). It is multiplexed by the procedure and then transmitted and received.

FIG. 2 is a schematic diagram of a synchronous multiplexing procedure. A DS1 signal having a data rate of 1.544 Mbps, a DS1E signal having a data rate of 2.048 Mbps, a DS3 signal having a data rate of 44.736 Mbps, and the like are finally shown through each multiplexing process shown in FIG. The signal is mapped to a synchronous transport module signal (STM-1) and then transmitted and received.

Where C is a container, VC is a virtual container, TU is a tributary unit, TUG is a hierarchical unit group, AU is an administrative unit, and an AUG (Administrative Unit Group) Means a management unit group.

At this time, the path through which the DS-3 signal is mapped to the synchronous transport module signal STM-1 is, firstly, C-3, VC-3, TU-3, TUG-3, VC-4, AU-4, and AUG. There may be a case where, and secondly, there may be a case where C-3, VC-3, AU-3, AUG.

3 is a mapping structure diagram of the high-virtual-virtual box signal VC-3 related to the DS-3 signal, which is composed of 85 bytes of columns and 9 bytes of rows. At this time, the first column is a section in which a path overhead (POH: Path Overhead) related to the corresponding high virtual box signal (VC-3) is located, and each 85-byte row is called a sub-frame. .

W1 of the subframe is "; RRCIIIII"; W2 is "; CCRRRRRR"; and W3 is "; CCRROORJ"; Here, I represents valid information bits, O represents overhead bits, and each C bit is used for positioning control.

And, the path overhead POH of the high-virtual virtual box signal VC-3 is composed of J1 byte, B3 byte, C2 byte, G1 byte, F2 byte, H4 byte, Z3 byte, Z4 byte, and Z5 byte, It performs all the functions necessary to reliably transport the payloads of the high virtual box signal (VC-3).

To explain the function of each byte constituting the path overhead, B3 byte is a bit-orthogonal even check byte for error checking of the path, and the result of the even check through BIP-8 (Bit Interleaved Parity-8) is inserted. do. The C2 byte is a signal label for indicating the configuration of the high virtual box signal VC-3, and the F2 byte is a byte allocated for user communication between path devices. In addition, the G1 byte is a channel for notifying the transmitting side of the path state and performance at the high virtual box signal (VC-3) receiving side, and the first 4 bits indicate whether a far end block error (FEBE) is present. The first bit indicates Far End Receive Failure (FERF), which indicates an AIS (Alarm Indication Signal) status, a signal reception failure, or a path tracking failure status.

The J1 byte is a channel for continuously tracking the connection state of the path. In other words, by repeatedly transmitting a fixed length signal of 64 bytes, the receiver can confirm that it is connected to the correct transmitter. Z3 to Z5 bytes are reserved bytes.

On the other hand, in the mapping procedure of the DS-3 signal to the synchronous transport module signal (STM-1) described above, the mapping along the second path is more efficient than the mapping along the first path. Therefore, in the transmission device using the synchronous transmission method, the DS-3 signal is generated to the management unit signal (AU-3) in the procedure of mapping the DS-3 signal to the synchronous transport module signal (STM-1) along the second path. Giving device is necessary.

Accordingly, the present invention has been made to meet the above necessity, DS-3 dependent signal having a transmission rate of 44.736Mbps in a synchronous multiplex structure DS-3 signal->; High box signal (C-3)->; High virtual box signal (VC-3)->; A device that multiplexes along the multiplexing path of the management unit signal (AU-3) and outputs it upward, and demultiplexes along the reverse path to extract the final DS-3 signal and outputs it downward, that is, in the synchronous transmission device, DS- An object of the present invention is to provide a multiplexing and demultiplexing apparatus (hereinafter referred to as "; multiplexing and demultiplexing apparatus" in the detailed description) between three signals and a management unit signal.

In order to achieve the above object, in the synchronous transmission apparatus according to the present invention, the multiplexing and demultiplexing apparatus between the DS-3 signal and the management unit signal AU-3 receives and decodes a predetermined encoded DS-3 signal. High-level box signal processing unit for synchronizing and outputting the high-level box signal (C-3), and also receiving the high-level box signal (C-3), the reverse synchronization and then encoded and output as an encoded DS-3 signal; A predetermined path overhead is inserted into the high box signal C-3 output from the high box signal processing unit, multiplexed into the high box virtual box signal VC-3, and outputted, and the aligned management unit signal AU-3. A high-level virtual box signal processing unit for receiving the input and extracting the predetermined path overhead and outputting the high-level box signal (C-3); The management unit signal AU-3 is generated by adding a predetermined management unit signal pointer to the high virtual box signal VC-3 output from the high virtual box signal processing unit, and outputs the management unit signal AU-3. A management unit signal processing unit configured to receive a signal and process a pointer to output an aligned management unit signal (AU-3); A preliminary overhead connection providing a means for connecting a predetermined preliminary overhead with external connection devices; And a clock signal switching unit configured to receive a clock signal from a predetermined clock unit, inspect a clock signal, select a normal clock signal, and supply the high level box signal processing unit, the high level virtual box signal processing unit, the management unit signal processing unit, and the preliminary overhead connection unit. Characterized in that it comprises a.

The high-level box signal processing unit receives a predetermined test pattern signal and a normal DS-3 signal, and a test loopback performing unit for selecting and outputting one according to a predetermined loopback control signal from the main control device; A remote loopback execution unit which receives a predetermined DS-3 signal and an output signal of the test loopback execution unit and selects and outputs one according to the loopback control signal; A high box signal transmitter configured to output a signal output from the remote loopback performing unit to a synchronized high box signal (C-3); A high box signal receiving unit which receives a predetermined high box signal C-3, desynchronizes the signal to generate an asynchronous DS-3 signal, and outputs the asynchronous DS-3 signal; A local loopback performing unit for outputting a signal output from the high-level box signal transmitter as it is or returning it to a high-level box signal (C-3) input signal of the high-box signal receiver according to the loopback control signal; And a downward alarm display signal inserting unit inserting or outputting predetermined alarm display signal (AIS) data into the asynchronous DS-3 signal outputted from the high box signal receiving unit according to the loopback control signal. It can be carried out more preferably.

At this time, the high box signal transmitter comprises: a decoder for decoding and outputting a predetermined asynchronous DS-3 signal input in an encoded state; An upward violation state checking and removal processing unit for detecting a predetermined out-of-frame state and an in-frame state with respect to the signal output from the decoder, and correcting and outputting a parity error if there is a parity error; Outputting a DS-3 signal having a predetermined alarm display signal pattern in accordance with a predetermined alarm display signal pattern selection signal from the main control device, and detecting a predetermined alarm display signal (AIS) pattern from the signal output from the decoder; Upward alarm display signal pattern generation and detection unit; A synchronization unit for receiving a signal output from the upward violation state checking and elimination processing unit and an upward warning display signal pattern generation and detection unit, respectively, and selecting one of them and synchronizing and outputting the signal; And an asynchronous clock error detection unit for checking an error state of a predetermined clock used in the decoding unit, an upward violation state checking and elimination processing unit, an uplink alarm display signal pattern generation and detection unit, and a synchronization unit. Can be.

In addition, the upward violation state checking and removal processing unit generates an overhead position designation signal (ohp) that locates each subframe and specifies an overhead position with respect to the signal output from the decoding unit, and generates a frame according to a predetermined rule. A subframe synchronization unit for detecting an OOP or an in-frame state; And a signal (mfp) specifying a start position of a multiframe and a signal (php) specifying a position of a parity bit for a signal output from the decoder, and checking a multiframe synchronization state according to a predetermined rule. A frame detector comprising a multi-frame synchronization unit; A parity check unit that checks a parity error for each multiframe by using the overhead positioning signal (ohp) and a signal (mfp) for designating a start position of a multiframe with respect to the signal output from the decoder; And DS-3 data having the corrected parity information after correcting a corresponding parity bit value according to a parity error signal output from the parity check unit by using a signal php for designating a location of the parity bit. A parity error detector comprising a parity correcting unit for outputting a); And a frame loss detection unit that outputs a signal indicating a frame loss state (LOF) when the out-of-frame (OOF) state detected by the frame detection unit satisfies a predetermined rule.

On the other hand, the uplink alarm display signal pattern generation and detection unit DS-3 frame generation unit for forming and outputting a predetermined DS-3 frame; A second alarm display signal pattern generator for outputting a DS-3 frame output from the DS-3 frame generator into a signal having a predetermined framed alarm display signal (AIS) pattern; A first alarm display signal pattern generation unit for outputting a predetermined alarm display signal (AIS) pattern signal having all bit values as logic values '1'; And one of a signal output from the second alarm display signal pattern generator and a signal output from the first alarm display signal pattern generator according to a predetermined alarm display signal pattern selection signal transmitted from the main controller. An alarm display signal pattern generator comprising an output alarm display signal pattern selector; And a second alarm display signal pattern detector configured to receive a predetermined DS-3 signal and detect the framed alarm display signal pattern state. A first alarm display signal pattern detection unit configured to receive a predetermined DS-3 signal and detect an alarm display signal pattern in which all bit values are logic values '1'; And an alarm display signal detector configured to output a predetermined alarm display signal detection signal according to an output signal of the second alarm display signal pattern detector and an output signal of the first alarm display signal pattern detector. It can carry out more preferably.

The synchronization unit may include a first timing generator which receives a predetermined clock signal and generates and outputs predetermined synchronization clock signals using the predetermined clock signal; A first elasticity which receives a signal output from the uplink violation state checking and removal processing unit and a signal output from the uplink alarm display signal pattern generation and detection unit, selects one of them, and then synchronizes and outputs the signal using the synchronous clock signals A buffer unit; And a high-level box signal multiplexing unit configured to output a signal generated by synchronizing the output from the first elastic buffer unit into a high-level box signal C-3 by using the synchronization clock signals. have.

The high virtual box signal processor may include an upward timing signal generator configured to generate and output a predetermined path overhead multiplexed timing signal; The high box signal C-3 output from the high box signal processing unit is retimed and received, and a predetermined path overhead is multiplexed using the path overhead multiplexing timing signal to generate a high box virtual box signal VC. An overhead generation and generation unit generating -3); An uplink synchronization buffer for synchronizing the high virtual box signal (VC-3) output from the overhead generation and generation unit; And outputting a signal output from the uplink synchronization buffer unit as it is, or returning it as an input signal of a predetermined high-virtual-virtual-box signal receiver according to a predetermined high-virtual-virtual box signal (VC-3) loopback control signal from the main controller. A high virtual box signal transmitter comprising a high virtual box signal mark loopback performing unit; And a downlink synchronization unit which receives a predetermined management unit signal (AU-3) or a signal output from the high-level virtual box signal local loopback execution unit, selects one of them, and synchronizes the selected signal; A down timing signal generator for generating and outputting predetermined downlink high virtual box signal VC-3 analysis timing signals; And extracting a path overhead from the high virtual box signal (VC-3) output from the downlink synchronization buffer unit to generate a high box signal (C-3), and outputting the overhead box signal (C-3). It can be implemented more preferably by including the high virtual box signal receiver which consists of a head extraction and analysis part.

1 is a block diagram of a basic network of an optical subscriber transmitter;

2 is a schematic diagram of a synchronous multiplexing procedure;

3 is a mapping structure diagram of a high virtual box signal VC-3 related to a DS-3 signal;

4 is a block diagram of a multiplexing and demultiplexing apparatus according to the present invention;

5 is a block diagram of a clock unit switching unit;

6 is a block diagram of a high box signal processing unit;

7 is a detailed block diagram of the high box signal transmitter;

8 is a detailed block diagram of an upward violation state inspection and removal processing unit;

9 is a detailed block diagram of an uplink alarm display signal pattern generation and detection unit;

10 is a detailed block diagram of a synchronization unit;

11 is a block diagram of a high box signal receiving unit;

12 is a detailed block diagram of a reverse synchronization unit;

Fig. 13 is a detailed block diagram of the high virtual box signal processing unit.

* Explanation of symbols for main parts of the drawings

10: Main station (COT) 11: Remote station (RT)

12: optical line 400: multiplexing and demultiplexing device

410: clock unit switching unit 420: high box signal processing unit

421: down alarm display signal insertion unit 422: loop back execution unit

423: high box signal transmitter 424: high box signal receiver

430: senior virtual box signal processing unit 440: management unit signal processing unit

450: spare overhead connection 480: external clock unit

490: main control unit (MCU) 510: clock error detection unit

520: transfer determination unit 530: transfer operation unit

610: test loopback execution unit 620: remote loopback execution unit

630: local loopback execution unit 710: decoding unit

720: Upward violation check and removal processing unit

721: frame detection unit 722: subframe synchronization unit

723: multi-frame synchronization unit 724: parity error detection unit

725: parity check unit 726: parity correction unit

727: frame loss detector

730: uplink alarm display signal pattern generation and detection unit

731: alarm display signal pattern generator 732: DS-3 frame generator

733: second alarm display signal pattern generator

734: alarm display signal pattern selection unit

735: first alarm display signal pattern generator

736: alarm display signal detection unit

737: second alarm display signal pattern detection unit

738: first alarm display signal pattern detection unit

739: alarm display signal declaration unit 740: asynchronous clock error detection unit

750, synchronization unit 751: first timing generator

752: first elastic buffer unit 753: high box signal multiplexing unit

810: reverse synchronization unit 811: second timing generator

812: second elastic buffer unit 813: high box signal demultiplexer

814: Demister Determination Unit

820: Downward violation check and removal processing unit

830: Downlink display signal pattern generation and detection unit

840: asynchronous clock error detection unit 850: code unit

910: high virtual box signal transmitter 911: up timing signal generator

912: overhead generation and generation unit 913: uplink synchronization buffer unit

914: Local loopback 920: High virtual box signal receiver

921, downlink synchronization buffer 922: downlink timing signal generator

923: Overhead Extraction and Analysis Section

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

In the signal flow shown in the following description, "downward" means the direction from the device of the present invention toward each subscriber side, and "upward"; means the direction from the subscriber side to the device of the present invention. .

4 is a block diagram of the multiplexing and demultiplexing apparatus 400 according to the present invention, and includes a clock unit switching unit 410, a high box signal processing unit 420, a high level virtual box signal processing unit 430, and a management unit signal processing unit ( 440 and the preliminary overhead connection unit 450, which are controlled by a main control unit 490, which is an external device, and receives a main clock signal from a predetermined external clock unit 480.

Here, the clock unit switching unit 410 receives and monitors the main clock signals from the main clock unit 480 including two clock units 481 and 482 (CLK A and CLK B), detects an error state, and detects a good clock signal. Perform the function of selecting.

In addition, the high-level box signal processing unit 420 may synchronize the asynchronous DS-3 signal, encode and decode the DS-3 signal, generate and detect a DS-3 alarm indication signal (AIS) pattern, and check and remove a violation state. A VMR (Violation Monitoring and Removal) function, a loopback function, and the like, and the high-level virtual box signal processing unit 430 performs a processing function on a path overhead (POH).

The management unit signal processing unit 440 performs a function of processing a management unit signal pointer (AU-3 Pointer) included in the management unit signal AU-3, and the preliminary overhead connection unit 450 includes a preliminary overhead byte and Performs the function of providing external connection of J1 bytes.

Now, the present invention will be described in detail for each component.

FIG. 5 is a block diagram of the clock unit switching unit 410, and includes a clock error detection unit 510, a switching determination unit 520, and a switching execution unit 530. An external main clock unit 480 is configured. This function monitors the main clock signals (e.g. 51.84MHz clock, 8 / 2KHz composition clock) output from two clock units (CLK A and CLK B), detects an error condition, and selects and outputs a good clock. do.

Each component of the present invention operates using the main clock signal output from the clock unit switching unit 410.

First, the main clock signal clock a supplied from one clock unit CLK A: 481 and the main clock signal clock b supplied from the other clock unit CLK B: 482 are clock error detectors 510. Are each entered. The clock error detection unit 510 checks the state of each input main clock signal to detect an error of the clock state, and then sends a result signal (clock error signal) to the switching determination unit 520.

The transfer determining unit 520 sends the clock selection signal to the transfer performing unit 530 according to the clock error signal received from the clock error detecting unit 510.

Like the clock error detector 510, the switching unit 530 receives the main clock signals clock a and clock b from two clock units CLK A and CLK B 481 and 482, respectively. The main clock signal clock a input from the CLK A 481 is output in accordance with the clock selection signal received from the CLK A 481, or the main clock signal clock b input from the CLK B 482 is output.

At this time, when the clock unit switching unit 410 is initialized, any one of two main clock signals is selected. Table 1 shows the switching state according to the state of each main clock signal (clock a, clock b).

clock a clock b Transfer status normal normal Keep old normal error CLK A Operated error normal CLK b is operational error error Keep old

6 is a block diagram of the high box signal processing unit 420, and includes a downlink alarm display signal inserting unit 421, a loopback execution unit 422, a high box signal transmitting unit 423, and a high box signal receiving unit 424. Function to synchronize asynchronous DS-3 signals, encode and decode DS-3 signals, generate and detect alarm display signal patterns for DS-3 signals, check and remove violations (VMR), and loopback functions. To perform.

First, the loopback execution unit 422 will be described.

The loopback execution unit 422 includes a test loopback execution unit 610, a remote loopback execution unit 620, and a local loopback execution unit 630, and perform a local loopback or remote loopback function to perform a multiplexing and demultiplexing device ( It provides a means for checking the operating state of the 400.

The test loopback execution unit 610 performs a function of selecting one of a predetermined test pattern signal and a normal DS-3 signal into a downward signal flow. That is, a predetermined loopback control signal is received from the main controller 490: 490, and accordingly, a test pattern All '1', All '0', or framed is provided for testing the multiplexing and demultiplexing apparatus 400. '1010') and one of the normal downlink DS-3 signals.

The remote loopback execution unit 620 performs switching of uplink DS-3 data and downlink DS-3 data to perform a remote loopback function of the DS-3 signal.

Specifically, when the remote loopback execution unit 620 receives a remote loopback control signal from the main controller 490: 490, and the loopback control signal is a signal for performing remote loopback, a normal uplink DS-3 signal. And one of the signals output from the test loopback execution unit 610 is output to the high box signal transmitter 423. That is, when the remote loopback is to be performed, the remote loopback is performed by returning the downlink DS-3 data output from the test loopback execution unit 610 instead of the normal DS-3 signal. At this time, as described above, if the output signal switched by the test loopback performing unit 610 is a test pattern signal, the test pattern signal is looped back.

The local loopback execution unit 630 receives the loopback control signal from the main control unit 490: MCU, and when the loopback control signal is a signal for performing the local loopback, the upstream high box signal C-3 and the downstream high box The transfer operation is performed with the signal C-3. That is, by returning the high box signal C-3 output upward from the high box signal transmitting unit 423 back to the high box signal receiving unit 424, the local loopback function for the high box signal C-3 is performed. To perform.

Meanwhile, the downlink alarm display signal inserting unit 421 generates and detects a downlink alarm display signal pattern in response to the loopback control signal received from the main control unit 490 (MCU). 830 inserts the DS-3 alarm display signal (AIS) outputted downward.

When the clocks used for the signals input to the test loopback execution unit 610, the remote loopback execution unit 620, and the local loopback execution unit 630 are different from each other, the clock signal used for the switching target signal may also be used. Alternate together.

Now, the high box signal transmitter 423 will be described in detail.

7 is a detailed block diagram of the high box signal transmitter, the high box signal transmitter 423 includes a decoder 710, an upward violation state inspection and removal processor 720, an upward alert display signal pattern generation and detection unit 730, The asynchronous clock error detector 740 and the synchronization unit 750 are configured to receive a predetermined uplink DS-3 signal, process it, and output the high-level box signal C-3.

The decoder 710 receives the DS-3 signal, which is input in the encoded state, decodes the NRZ (None Return to Zero) data and outputs the decoded signal. At this time, a 44.736 MHz clock (ck45m) for processing the received DS-3 signal and a decoder control signal (deccon) transmitted from the main controller 490 (MCU) are received together.

That is, the DS-3 signal received using the 44.736 MHz clock (ck45m) is decoded into a signal of NRZ data and output. When the decoder control signal is a signal for stopping the operation of the decoder 710, the input signal is inputted. Output as is without decoding. In addition, when an error occurs in the input DS-3 signal, a signal indicating the error state of the DS-3 code is output separately to inform it.

8 is a detailed block diagram of the upward violation state checking and elimination processing unit 720, and includes a frame detector 721, a parity error detector 724, and a frame loss (LOF) detector 727. FIG.

The frame detection unit 721 of the upward violation state checking and removal processing unit 720 includes a subframe synchronization unit 722 and a multiframe synchronization unit 723. First, the DS-3 signal output from the decoder 710 is generated. After detecting the synchronization of each sub-frame in the sub-frame, the synchronization of the multi-frame (multi-frame) is detected to generate the necessary synchronization control signals, depending on the state of synchronization (OOF: Out Of Frame) or Outputs a signal indicating in-frame.

The subframe synchronizer 722 receives a DS-3 signal output from the decoder 710 and a 44.736 MHz clock (ck45m) used by the decoder 710 to generate a pulse signal indicating the start position of the subframe. And outputs an overhead positioning signal (ohp) specifying the overhead position. Once an in-frame is declared, it always generates a constant pulse signal before the OOP is declared.

Also, a function of determining and declaring transition between out-of-frame (OOF) and in-frame according to the state transition condition is performed. First, the transition condition from the out-of-frame (OOF) state to the in-frame state is When out of frame (OOF), it detects whether a predetermined number (e.g. 16) consecutive frame bits are received in a normal state and declares an in-frame, and also out of frame from the in-frame state (OOF). A transition condition to the) state declares out-of-frame (OOF) when an error more than a predetermined number (for example, three) out of a predetermined number (for example, 16) consecutive frame bits occurs during in-frame.

The multi-frame synchronization unit 723 generates a pulse signal (mfp) that specifies the start position of the multiframe, and also a signal (php) that specifies the location of the parity bit to perform the violation state check and removal (VMR) function. Create and print In addition, by detecting a multiframe alignment pattern and determining whether it is accidentally generated from a random data stream, a process of continuously checking whether or not it is normal by a predetermined number (for example, 4 times) is performed. Declare At this time, once an in-frame is declared, the synchronization state is maintained until an out of frame (OOF) is declared.

The parity error detector 724 includes a parity checker 725 and a parity corrector 726 to detect and correct an error of a parity bit.

The parity checker 725 counts the number of bits having a logic value '1' among pure data except for the overhead bits from the input DS-3 signal. One embodiment of the parity checker 725 that performs this function is to use a JK flip-flop.

The overhead positioning signal (ohp) output from the subframe synchronization unit 722 becomes a logical value '0' for each overhead bit position, and the multiframe positioning signal mfp is the position of the first bit of the frame. Is the logical value '0'.

Therefore, when both the overhead positioning signal (ohp) and the multiframe positioning signal (mfp) become the logic value '0', that is, the input end value of the JK flip-flop is J = 0 in the first bit of one multiframe. , K = 1. The JK flip-flop is then reset. In addition, when the overhead positioning signal ohp is not the logic value '0' and not the first bit of the multiframe, the input terminal values of the JK flip-flop are set to J = 0 and K = 0. In other words, the JK flip-flop does not operate at the overhead position.

When the multi-frame positioning signal mfp is not the logic value '0' and the logic value of the overhead positioning signal ohp is not '0', the logic value of the input bit is '1'. Set the JK flip-flop input stage values to be J = 1 and K = 1. The output value of the JK flip-flop is then toggled.

Therefore, if the number of bits having a logic value '1' in the data excluding the overhead among the data in one multiframe is an even number, the output of the JK flip-flop is in a logic value '0' state. The result value is compared with the detected parity bit value, the parity error of each multiframe is checked, and a parity error signal is output. At this time, the parity error detection declaration is not made until one multiframe is finished.

The parity correction unit 726 receives a violation state check and removal (VMR) mode selection signal from the main controller 490 (MCU), and instructs the mode selection signal to perform a violation state check and removal (VMR) function. If so, replace the parity bit with a new value. That is, the parity bit positioning signal php output from the multi-frame synchronization unit 723 becomes the logical value '0' at the position of the parity bit, and the parity output from the parity check unit 725 using this signal. After the error signal is replaced with the correct parity bit value, the calibrated DS-3 data is output. At this time, the execution of the Violation State Checking and Rejection (VMR) function is performed only when the frame is in sync.

The frame loss detector 727 receives a frame state signal output from the frame detector 721 to detect a frame loss (LOF) state.

The frame loss state is declared when the out-of-frame (OOF) state is continued over a predetermined number of frames (eg, 24 frames), and outputs a signal LOF indicating that a frame loss (LOF) has occurred. Once a frame loss (LOF) is declared, it is recovered only by a recovery condition, and when the frame synchronization state continues over a predetermined number of frames (eg, 24 frames), it recovers to a normal state.

9 is a detailed block diagram of the uplink alarm display signal pattern generation and detection unit 730, and includes an alarm display signal pattern generation unit 731 and an alarm display signal detection unit 736, and an alarm display signal in the form of a DS-3 signal. (AIS) Pattern is generated, and it detects the alarm indication signal (AIS) status from the input DS-3 signal. At this time, generation and detection of the alarm display signal AIS includes both the framed pattern '1010' alarm display signal AIS and the All '1' alarm display signal AIS.

The alarm display signal pattern generator 731 generates the DS-3 frame generator 732, the second alarm display signal pattern generator 733, the alarm display signal pattern selector 734, and the first alarm display signal pattern generator. It consists of a part 735.

The DS-3 frame generator 732 forms and outputs a predetermined DS-3 frame, and the second alarm display signal pattern generator 733 is a DS-3 frame output from the DS-3 frame generator 732. And outputs a predetermined framed alarm display signal (AIS) pattern. In addition, the first alarm display signal pattern generation unit 735 outputs an alarm display signal (AIS) pattern signal having all bit values as logic values '1'.

The alarm display signal pattern selection unit 734 is framed output from the second alarm display signal pattern generation unit 733 according to the alarm display signal (AIS) pattern selection signal transmitted from the main control unit 490 (MCU). Any one of the signal of the alarm display signal (AIS) pattern or the signal of the All '1' pattern output from the first alarm display signal pattern generator 735 is selected and output. At this time, as an example, the signal initially output from the alarm display signal pattern selection unit 734 is a signal of the framed alarm display signal (AIS) pattern, and is output from the alarm display signal pattern selection unit 734. The alarm indication signal AIS is used in each component that requires the alarm indication signal AIS.

On the other hand, the alarm display signal detection unit 736 is composed of a second alarm display signal pattern detection unit 737, a first alarm display signal pattern detection unit 738, and an alarm display signal declaration unit 739, upward DS-3 Detects the alarm indication signal (AIS) state present in the signal.

The second alarm display signal pattern detection unit 737 receives an upward DS-3 signal and detects a framed alarm display signal (AIS) state. That is, the number of bits having different logic values is counted by comparing a frame pattern generated by itself (e.g., a '1010' pattern) with a pattern of input DS-3 data. If it is wrong, declare the alarm indication signal (AIS). At this time, the determination of whether the alarm display signal (AIS) or the normal DS-3 signal is performed in units of multi-frames, and for this purpose, the count value is initialized every multi-frames.

The first alarm display signal pattern detection unit 738 generates a pulse every predetermined period (for example, 20 ms), and counts the number of bits having a logic value of '0' to declare the alarm display signal detection. In other words, when the number of bits whose logical value of the input data is '0' is less than a predetermined number (for example, 900), the alarm display signal (AIS) detection state is declared.

In this case, as an example of configuring the first alarm display signal pattern detection unit 738, a 900-degree counter can be used. The counter is incremented by one from the input signal having a logic value of '1', and thus the state of this counter. If you look at the logic value '1' you can see the number entered.

Then, in the second alarm display signal pattern detector 737 and the first alarm display signal pattern detector 738, once the alarm display signal AIS detection is declared, the alarm display signal AIS continues to be declared unless the release condition is satisfied. Maintain state.

Meanwhile, the alarm display signal declaration unit 739 receives the output signals of the second alarm display signal pattern detection unit 737 and the first alarm display signal pattern detection unit 738, respectively, and at least one signal among the two input signals is alarmed. The alarm display signal detection signal is output when the signal indicating that the display signal AIS has been detected.

As an example of configuring the alarm display signal declaration unit 739, an OR gate may be used. That is, when the alarm display signal AIS is detected, the output signals of the second alarm display signal pattern detection unit 737 and the first alarm display signal pattern detection unit 738 have a logic value '1'. When one or more logic values of the two inputs become '1', the logic value '1' is outputted, and thus the alarm display signal detection state can be output correctly.

The asynchronous clock error detection unit 740 monitors the asynchronous 44.736 MHz clock (ck45m) used on the upstream side. When the 44.736 MHz clock (ck45m) is lost more than a predetermined number (e.g., 16) in succession, Declares that the clock has failed and succeeds in recovering when a predetermined number (16 or more) is normally received.

FIG. 10 is a block diagram of the synchronization unit 750, and includes a first timing generator 751, a first elastic buffer 752, and a high box signal multiplexer 753. The DS-3 signal (out data) output from the processing unit 720 or the DS-3 alarm display signal output from the detection and detection unit 730 is output in synchronization.

Here, the first timing generator 751 receives a 50.112 MHz (gapped 50.112 MHz) clock that is gapped with a predetermined J1 clock (8 KHz), generates and outputs clock signals for synchronization. In other words, the 50.112 MHz clock is divided into 8 to create a clock for processing the high-definition virtual box signal (VC-3) of 6.264 MHz bytes in parallel, and the 29 is further divided into a clock for 216 KHz of overhead positioning. It divides and produces and supplies a clock for the 72kHz high-virtual virtual box signal (VC-3) subframe.

At this time, all generated clocks are generated in synchronization with the J1 clock derived from the system synchronization clock 8KHz, and continuously generate synchronized signals even when the J1 clock has an error.

The first elastic buffer unit 752 is a DS-3 signal (out data) output from the up-violation violation state detection and removal processing unit 720 or a DS-3 alarm display output from the generation and detection pattern of the uplink alarm display signal pattern 730. After receiving the signal AIS, one of them is selected, and then synchronized and outputted using the synchronization clock signals generated by the first timing generator 751.

One embodiment of the first elastic buffer portion 752 will be described in detail.

The first elastic buffer unit 752 first selects one of a normal DS-3 signal (out data) and a DS-3 alarm display signal (AIS) input, and then selects a predetermined 64-stage asynchronous buffer unit (not shown). To create a 44.736 MHz clock that is gapped from the 50.112 MHz clock. The write address generated by dividing the generated 44.736 MHz clock by 64 is decoded to generate a selection signal for each asynchronous buffer. At this time, the initial value of the read address (the address of the asynchronous buffer to read data) is set to a predetermined value, and this setting value is loaded at the time of initialization.

That is, the selected data is stored in predetermined latches (not shown), respectively, by the 64 write select signals thus produced. The stored signal is synchronized by being retimed after being output by the signal specifying the buffer read address.

In addition, the phase of the write signal used to write or read data to the asynchronous buffer unit is compared with the phase of the read signal and latched in units of 72 KHz subframes, and the latched state signal is output as a stuffing request signal.

On the other hand, the high box signal multiplexing unit 753 receives data output from the first timing generating unit 751 in synchronization with each of the overhead positioning clock signals and the first elastic buffer unit 752 and outputs the high box signal C. -3).

That is, the synchronized signal input from the first elastic buffer unit 752 is a state in which the positions of the overhead bits constituting the high-virtual virtual box signal VC-3 frame are filled with invalid data, and the serial data includes only pure information bits. Has the form of. In order to form effective load data in the final high virtual box signal (VC-3) frame, the overhead bits (R, C, O bits shown in FIG. 3) are multiplexed and output in parallel.

In addition, as an exemplary embodiment, even parity is calculated for each byte of the finally generated output data and output together.

Now, the high box signal receiver 424 will be described.

11 is a block diagram of the high box signal receiving unit 424, which includes a reverse synchronization unit 810, a down violation checking and removing processing unit 820, a down warning display signal pattern generation and detection unit 830, and an asynchronous clock error detecting unit ( 840 and a sign unit 850, and receive the high-level box signal (C-3) of the parallel input from the high-level virtual box signal processing unit 430, and demultiplexed for each DS-3 signal and outputs downward.

12 is a block diagram of the desynchronization unit 810, which includes a second timing generator 811, a second elastic buffer 812, a high box signal demultiplexer 813, and a de stuffing determination unit 814. It is composed of a high-rate box signal (C-3) of 6.262Mbps, which is input in parallel, and demultiplexes the parallel data and outputs it as a DS-3 asynchronous signal of 44.736Mbps.

At this time, the second timing generator 811 performs the same operation as the first timing generator 751. At this time, the de-stamping unit 814 performs the de-stamping operation on each timing signal according to the de-stamping request signal sent from the de-stamping unit 814.

The high-level box signal demultiplexer 813 receives each overhead positioning clock signal from the second timing generator 811, and uses the high-level box signal demultiplexer 813 to receive each overhead from the parallel high-level box signal C-3 received in parallel. Extract the head, convert it to serial data, and output it. In addition, the parity error signal is output after detecting an error between devices by comparing the parity value received from the high-level virtual box signal processor 430 and the parity value separately received from the high-value virtual box signal processing unit 430 with respect to the received parallel data. Then, the C bit data is extracted from the input high box signal (C-3) data and output to the de stuffing determination unit 814.

The de stuffing determination unit 814 receives the C bit data extracted from the high box signal demultiplexing unit 813, and includes the C bits of the fourth byte, the C bits of the 32nd byte, and the 61st byte. The majority vote is performed by combining the values of the C bits in place. The output value determined based on the majority vote principle is supplied to the second timing generator 811 as a de-stamping request signal by a clock signal generated at a position after the last C bit. In addition, two O bits on the high box signal (C-3) frame are extracted and output separately.

The second elastic buffer unit 812 reverse-synchronizes the signal output from the high box signal multiplexer 813 and outputs it as an asynchronous DS-3 signal, and will be described in detail with reference to an embodiment of the second elastic buffer unit 812. Shall be.

The second elastic buffer 812 first writes a signal output from the high box signal demultiplexer 813 to a predetermined 64-stage asynchronous buffer, and generates a write address and a read address for reading. That is, for buffer writing, an overhead bit position is block-gaped from an input 50.112 MHz clock and divided by 64 to generate a write address. The generated write address is decoded to generate a select signal for each asynchronous buffer. At this time, this value is loaded at initialization to set the initial value of the write address to a predetermined value (for example, 45).

That is, data serialized from the high box signal demultiplexing unit 813 is latched to a predetermined latch unit (not shown) using 64 buffer write selection signals. The latched signal is output from the latch by a signal indicating a predetermined buffer read address, and then retimed and output again.

At this time, by comparing the value of the read address and the value of the write address to determine the size, using the determined signal to calculate the difference of the address, compared with a predetermined prescribed threshold value, exceeding the threshold value In this case, a signal indicating this is output separately.

The downward violation state inspection and removal processing unit 820 has the same configuration as the upward violation state inspection and removal processing unit 720.

At this time, the DS-3 signal inputted to the downlink violation check and removal processing unit 820 is a signal output from the desynchronization unit 810, and the DS-3 signal subjected to the violation state check and removal (VMR) process is a code unit. And outputs an out-of-frame (OOF) state and a frame loss (LOF) state as separate signal lines (oof, LOF).

In addition, the downward alert display signal pattern generation and detection unit 830 has the same configuration as the upward alert display signal pattern generation and detection unit 730.

At this time, the input DS-3 signal is a signal output from the reverse synchronization unit 810, the generated DS-3 alarm display signal (AIS) is output to the sign unit 850, the detected alarm display signal state is Output through a separate signal line.

In addition, the asynchronous clock error detector 840 used in the high box signal receiving unit 424 also has the same configuration and purpose of use as that used in the high box signal transmitting unit 423.

On the other hand, the coder 850 selects one of the DS-3 signals output from the downlink violation check and removal processor 820 and the downlink alarm display signal pattern generation and detection unit 830, and encodes the signal according to the B3ZS code regulation. After generating positive data and negative data, output them downward.

At this time, the selection function is controlled by a predetermined control signal from the main control unit 490 (MCU), and is not encoded by a predetermined code part disable transmitted from the main control unit 490 (MCU). Allow the signal to pass through as is.

FIG. 13 is a block diagram of the high virtual box signal processing unit 430. The high virtual box signal transmitting unit 910 and the high virtual box signal receiving unit 920 process upper path overhead (VC-3 overhead). do.

The high virtual box signal transmitter 910 includes an upward timing signal generator 911, a high virtual box signal (VC-3) overhead generation and generation unit 912, an uplink synchronization buffer unit 913, and a local loopback unit ( 914, and performs a function of generating and outputting the synchronized high virtual box signal VC-3 from the high box signal processing unit 420 in parallel.

The uplink timing signal generator 911 generates a timing overhead multiplexing timing signal to form an uplink high virtual box signal VC-3.

That is, a predetermined 50.112 MHz clock (ck50m) and an 8KHz reference clock fr8K are input to generate a signal that distinguishes a higher path overhead seat, a fixed stuffing byte seat, and a valid data seat. It also generates a signal for BIP-8 calculation control, which consists of a signal for latching the calculated BIP-8 value every frame and a signal for initializing after latching.

Table 2 below shows an example of a path overhead positioning timing signal composed of 4 bits (pohm.0, pohm.1, pohm.2, and pohm.3) used for path overhead multiplexing.

pohm.0 pohm.1 pohm.2 pohm.3 location 0 0 0 0 J1 0 One 0 0 B3 One 0 0 0 C2 0 0 0 One G1 0 One 0 One F2 One 0 0 One H4 0 0 One 0 Z3 0 One One 0 Z4 One 0 One 0 Z5

The high-level virtual box signal VC-3 overhead generation and generation unit 912 retimes the received high-level box signal C-3 in order to smoothly connect with the high-level box signal processing unit 420. After receiving, the signal is received, and the upper path overhead is multiplexed to form an uplink high virtual box signal (VC-3) frame.

The higher path overhead multiplexing function of the overhead generation and generation unit 912 will be described in detail.

First, BIP-8 calculation is performed on the high virtual box signal VC-3 data output from the overhead generation and generation unit 912. That is, by using the BIP-8 calculation control signal generated by the uplink timing signal generator 911, the high virtual box signal VC-3 data input is latched in byte units, and this value and the parity value previously calculated. Parity is calculated by comparing bit by bit. The parity value calculated bit by bit for each byte is calculated until just before the J1 byte, and after outputting the parity value, the parity is recalculated from the J1 byte.

In addition, 64 to 1 multiplexing is performed by reading a 64 byte J1 value latched in a predetermined register (not shown) and outputting the value using the 8 KHz clock for specifying the J1 byte position.

Then, each path overhead byte is multiplexed to the re-timed high box signal C-3 parallel signal and output. That is, the signal output from the overhead generation and generation unit 912 is a high-virtual virtual box signal VC-3, in which each upper path overhead byte is inserted and multiplexed.

The uplink synchronization buffer 913 serves as a buffer to solve the clock deviation that occurs when mapping the high virtual box signal VC-3 output from the overhead generation and generation unit 912 to AU-3. do.

An embodiment of the uplink synchronization buffer 913 will be described in detail. First, a predetermined write address and a read address to be used when writing and reading the high virtual box signal VC-3 data into a predetermined synchronization buffer (not shown). Create After writing the high virtual box signal (VC-3) data to the corresponding sync buffer using the write address, the data is read from the sync buffer corresponding to the read address using the clock used for the management unit signal (AU-3). The high virtual box signal (VC-3) data can be mapped to the management unit signal frame.

At this time, the error condition of the buffer is monitored. When the read address and the write address become the same value, the buffer is automatically initialized. When the read address is set to the same address value at the time of initialization, the read address is set to be prevented. After initialization, it does not require automatic initialization until the value is '1'.

The high virtual box signal local loopback performing unit 914 performs local loopback according to the high virtual box signal VC-3 loopback control signal received from the main controller 490: MCU. That is, when performing the local loopback, the local loopback is performed by returning the signal output from the uplink synchronization buffer 913 as an input signal of the high virtual box signal receiver 424.

Now, the high-level virtual box signal receiving unit 920 will be described in detail.

The high virtual box signal receiving unit 920 includes a down synchronization buffer unit 921, a down timing signal generator 922, and an overhead extracting and analyzing unit 923. The high virtual box signal receiving unit 920 receives an input management unit signal AU-3. Processing is performed to convert the high box signal (C-3) into a parallel signal.

The downlink synchronization buffer 921 generates a predetermined write buffer selection signal, stores the input AU-3 parallel data into a corresponding latch unit (not shown), generates a predetermined read signal and a write signal, and generates the corresponding buffer. By writing the data into and rereading it, the AU-3 parallel data is mapped into the high virtual box signal (VC-3) frame.

At this time, the write address is generated after the buffer read address reaches a predetermined value, so that the difference between the read address and the write address has a set initial value. .

The down timing signal generator 922 generates timing signals for analyzing the downlink high virtual box signal VC-3 frame. That is, it generates a positioning signal of each upper path overhead, a BIP-8 control signal for BIP-8 calculation, and generates a 64KHz clock for accumulating 8 BIP-8 errors in each frame.

The overhead extraction and analysis unit 923 uses the timing signals generated from the downlink timing signal generator 922 to generate a path overhead from the high-virtual virtual box signal VC-3 output from the downlink synchronization buffer 921. After extracting, make into high-level box signal (C-3) parallel signal and output it. In addition, the function analyzes the extracted path overhead for each function.

On the other hand, the preliminary overhead connection unit 450 connects the preliminary preliminary overheads F2, Z3, Z4, Z5, O and J1 bytes extracted from the high virtual box signal processing unit 430 to predetermined external devices. Perform the function.

The management unit signal processing unit 440 creates and inserts a corresponding management unit signal pointer value into the high virtual box signal VC-3 outputted with the path overhead added from the high virtual box signal processing unit 430, thereby providing a management unit signal ( Create and print AU-3). Further, in the downward direction, the management unit signal pointer AU-3 is extracted from the input management unit signal AU-3, analyzed, and then outputs the management unit signal AU-3 in an aligned state.

Using the present invention, a predetermined DS-3 dependent signal having a transmission rate of 44.736 Mbps is obtained by DS-3->; C-3->; VC-3->; Multiplexed along the synchronous multiplexing path of the AU-3 and outputted upward, and demultiplexed along the reverse path to extract the final DS-3 signal and outputted downward. Can be used as

Claims (7)

A device used in a predetermined synchronous transmission device to perform a multiplexing and demultiplexing function between a DS-3 signal and a management unit signal (AU-3) during a synchronous multiplexing procedure under the control of a predetermined main control device. Receives the encoded DS-3 signal, decodes it, synchronizes it, and outputs it as the high box signal (C-3), and also receives the high box signal (C-3), desynchronizes it, and then encodes and encodes the DS-3 signal. High box signal processing unit for outputting a signal; A predetermined path overhead is inserted into the high box signal C-3 output from the high box signal processing unit, multiplexed into the high box virtual box signal VC-3, and outputted, and the aligned management unit signal AU-3. A high-level virtual box signal processing unit for receiving the input and extracting the predetermined path overhead and outputting the high-level box signal (C-3); The management unit signal AU-3 is generated by adding a predetermined management unit signal pointer to the high virtual box signal VC-3 output from the high virtual box signal processing unit, and outputs the management unit signal AU-3. A management unit signal processing unit configured to receive a signal and process a pointer to output an aligned management unit signal (AU-3); A preliminary overhead connection providing a means for connecting a predetermined preliminary overhead with external connection devices; And After receiving and inspecting a clock signal from predetermined clock units, the clock signal switching unit selects a normal clock signal, and supplies the high-level box signal processing unit, the high-level virtual box signal processing unit, the management unit signal processing unit, and a preliminary overhead connection unit. Multiplexing and demultiplexing device between the DS-3 signal and the management unit signal in a synchronous transmission device characterized in that the configuration. The apparatus of claim 1, wherein the high-level box signal processor comprises: a test loopback performer configured to receive a predetermined test pattern signal and a normal DS-3 signal, and select and output one according to a predetermined loopback control signal from the main controller; A remote loopback execution unit which receives a predetermined DS-3 signal and an output signal of the test loopback execution unit and selects and outputs one according to the loopback control signal; A high box signal transmitter configured to output a signal output from the remote loopback performing unit to a synchronized high box signal (C-3); A high box signal receiving unit which receives a predetermined high box signal C-3, desynchronizes the signal to generate an asynchronous DS-3 signal, and outputs the asynchronous DS-3 signal; A local loopback performing unit for outputting a signal output from the high-level box signal transmitter as it is or returning it to a high-level box signal (C-3) input signal of the high-box signal receiver according to the loopback control signal; And According to the loopback control signal, a predetermined alarm display signal (AIS) data is inserted into the asynchronous DS-3 signal output from the high box signal receiving unit or outputted as it is, or comprises a downward alarm display signal insertion unit for outputting as it is; Multiplexing and demultiplexing device between the DS-3 signal and the management unit signal in a synchronous transmission device. 3. The apparatus of claim 2, wherein the high box signal transmitter comprises: a decoder configured to decode and output a predetermined asynchronous DS-3 signal input in an encoded state; An upward violation state checking and removal processing unit for detecting a predetermined out-of-frame state and an in-frame state with respect to the signal output from the decoder, and correcting and outputting a parity error if there is a parity error; Outputting a DS-3 signal having a predetermined alarm display signal pattern in accordance with a predetermined alarm display signal pattern selection signal from the main control device, and detecting a predetermined alarm display signal (AIS) pattern from the signal output from the decoder; Upward alarm display signal pattern generation and detection unit; A synchronization unit for receiving a signal output from the upward violation state checking and elimination processing unit and an upward warning display signal pattern generation and detection unit, respectively, and selecting one of them and synchronizing and outputting the signal; And And asynchronous clock error detection unit for checking an error state of a predetermined clock used in the decoder, the uplink violation state checking and elimination processing unit, the uplink alarm display signal pattern generation and detection unit, and the synchronization unit. Device for multiplexing and demultiplexing between DS-3 signals and management unit signals. The apparatus of claim 3, wherein the upward violation state checking and elimination processing unit generates an overhead positioning signal that locates each subframe and specifies an overhead position with respect to the signal output from the decoding unit. A subframe synchronization unit that detects an out-of-frame or in-frame state; And A frame composed of a multiframe synchronization unit for generating a signal specifying a start position of a multiframe and a signal specifying a parity bit position with respect to the signal output from the decoder, and checking a multiframe synchronization state according to a predetermined rule. Detection unit; A parity checker that checks a parity error every multiframe using the overhead positioning signal and a signal specifying a start position of a multiframe with respect to the signal output from the decoder; And A parity corrector configured to correct a corresponding parity bit value according to a parity error signal output from the parity check unit by using a signal specifying the location of the parity bit, and then output DS-3 data having the corrected parity information. A parity error detector; And And a frame loss detector for outputting a signal indicating a frame loss state (LOF) when the out-of-frame (OOF) state detected by the frame detector satisfies a predetermined rule. And demultiplexing device between the control and the control unit signal. The apparatus of claim 3, wherein the upward alert display signal pattern generation and detection unit comprises: a DS-3 frame generation unit configured to output a predetermined DS-3 frame; A second alarm display signal pattern generator for outputting a DS-3 frame output from the DS-3 frame generator into a signal having a predetermined framed alarm display signal (AIS) pattern; A first alarm display signal pattern generation unit for outputting a predetermined alarm display signal pattern signal having all bit values as logic values '1'; And According to a predetermined alarm display signal pattern selection signal transmitted from the main control device, one of a signal output from the second alarm display signal pattern generator and a signal output from the first alarm display signal pattern generator is selected and output. An alarm display signal pattern generation unit comprising an alarm display signal pattern selection unit; And A second alarm display signal pattern detection unit configured to receive a predetermined DS-3 signal and detect the framed alarm display signal pattern state; A first alarm display signal pattern detection unit configured to receive a predetermined DS-3 signal and detect an alarm display signal pattern in which all bit values are logic values '1'; And And an alarm display signal detector configured to output a predetermined alarm display signal detection signal according to an output signal of the second alarm display signal pattern detector and an output signal of the first alarm display signal pattern detector. A multiplexing and demultiplexing device between a DS-3 signal and a management unit signal in a synchronous transmission device. 4. The apparatus of claim 3, wherein the synchronization unit comprises: a first timing generator which receives a predetermined clock signal and generates and outputs predetermined synchronization clock signals using the predetermined clock signal; A first elasticity which receives a signal output from the uplink violation state checking and removal processing unit and a signal output from the uplink alarm display signal pattern generation and detection unit, selects one of them, and then synchronizes and outputs the signal using the synchronous clock signals A buffer unit; And And a high box signal multiplexing unit configured to output a high box signal (C-3) by synchronizing the signal output from the first elastic buffer unit to the high box signal using the synchronous clock signals. Multiplexing and demultiplexing device between DS-3 signal and management unit signal. 2. The apparatus of claim 1, wherein the high-virtual virtual box signal processor comprises: an upward timing signal generator configured to generate and output a predetermined path overhead multiplexed timing signal; The high box signal C-3 output from the high box signal processing unit is retimed and received, and a predetermined path overhead is multiplexed using the path overhead multiplexing timing signal to generate a high box virtual box signal VC. An overhead generation and generation unit generating -3); An uplink synchronization buffer for synchronizing the high virtual box signal (VC-3) output from the overhead generation and generation unit; And According to a predetermined high virtual box signal (VC-3) loopback control signal from the main control device, the high signal outputting the signal output from the uplink synchronization buffer unit as it is or returned as an input signal of the predetermined high virtual box signal receiving unit. A high virtual box signal transmitter comprising a virtual box signal mark loopback performing unit; And A downlink synchronization unit which receives a predetermined management unit signal (AU-3) or a signal output from the high-level virtual box signal station loopback execution unit, selects one of these, and synchronizes the signal; A down timing signal generator for generating and outputting predetermined downlink high virtual box signal VC-3 analysis timing signals; And The overhead of extracting the path overhead from the high virtual box signal (VC-3) output from the downlink synchronization buffer unit to make the high box signal (C-3), and outputs, and the overhead of analyzing and processing each extracted path overhead Multiplexing and demultiplexing device between the DS-3 signal and the management unit signal in a synchronous transmission device comprising a high virtual box signal receiver comprising an extraction and analysis unit.