KR20020056422A - VC mapping system of the SDH TYPE and controlling method therefore - Google Patents

Abstract

PURPOSE: An SDH virtual container(VC) mapping system and its control method are provided to simplify an internal logic circuit of a VC mapping system and considerably reduce its production cost by integrating C0/C1 control blocks in one control block and multiplexing data by modes while implementing a 1/3 U1 waiting time jitter reduction algorithm. CONSTITUTION: A corresponding mode is set and a system is set up(S1). A system clock is assigned in a 1/3 UI method and frame pulse signals are generated according to each mode of T1-T2 and an E1 signal(S2). One signal is selected to select a corresponding individual mapping unit block among a plurality of frame pulses as generated, and generated as a before address(S3). A wad and a rad of a corresponding channel is multiplexed from corresponding individual mapping unit block according to the generated before address signal(S4).

Description

VC mapping system of the SDH TYPE and controlling method therefore}

The present invention relates to an SDH type VC mapping system and a control method thereof. In particular, by integrating the C0 / C1 control blocks provided in the individual mapping device blocks in one control block to reduce the weighting time jitter, the VC mapping is performed. Since the internal logic circuit of the system can be simplified, the present invention relates to an SDH type VC mapping system and a control method thereof, which can significantly reduce the manufacturing cost of the VC mapping system.

In general, the transmission technology began with the spiral carrier in the 1910s, developed into the analog transmission technology, and in the form of a digital transmission technology. Later, in the 1960s, the digital transmission technology started to develop a T1 channel bank with a 1.544 Mbps transmission rate. It was. Moreover, the digital transmission method has been developed into an optical transmission method using an optical cable as a transmission medium. As the point-to-point type optical communication has evolved into an optical communication network, as a result of standardization of a broadband integrated information network (B-ISDN), It is called synchronous transmission.

Here, while making a synchronous optical network (SONET) connection standard to enable the construction of the network by the optical communication systems, this is also referred to as the network node interface (NNI) standard of B-ISDN. Synchronized digital hierarchy (SDH) has been generalized for use, and a synchronous transmission scheme is a transmission scheme based on this synchronous digital hierarchy. In particular, a new transmission method for configuring and transmitting the synchronous digital step signals is called a synchronous transmission method, compared to a conventional communication method for constructing similar synchronous digital step signals and transmitting them through a baseband.

Therefore, through the synchronous multiplexing process, the existing DS-1 to DS-4 hierarchical signals are multiplexed into STM-n signals and reconfigured through an ADM device having a synchronous branch coupling function or a DACS device having a synchronous cross linking function. Synchronous transmission can be referred to as a series of synchronous processing processes transmitted and reproduced through a synchronous optical communication network.

Then, referring to FIG. 1 of the VC (virtual container) mapping system using the SDH method as described above, an individual mapping device block 70A-N for reading data from each individual line, and the individual mapping device block 70A-N. An STM-1 frame counter 71 for generating control signals capable of multiplexing the mapping device blocks 70A-N, and a separate mapping device block according to the VC address signal input from the STM-1 frame counter 71. 70A-N) is sequentially composed of a channel MUX block 72 for multiplexing and transmitting it to an STM-1 transmitter (not shown).

Here, in the conventional VC mapping system as described above, individual mapping device blocks 70A-N are configured for each mode. For example, 84 may be formed in the T1 mode and 63 may be formed in the E1 mode.

Then, one of the individual mapping device blocks formed in a plurality of mode channels in the VC mapping system as described above includes a write address generator 73 for generating a write address wad according to the input write clock signal wck; An elastic buffer (ELB) for reading and storing data from the individual subscriber line through the write data (wdt) line, and a read address generator for supplying a read address (rad) signal to the ELB 74. (75), S (serial) / P (parallel) converter 76 for outputting the serial data output from the ELB 74 in parallel, and the data transmitted through the S / P converter 76 A VC mapping control block 77 which receives and transmits to the channel MUX block 72 and a write address for the period v1 provided through the v1en line from the STM-1 frame counter 71 (TU-11 / 12/2). The wad signal of the generator 73 and the lead add CO / C1 outputting a control signal for determining whether the stuff-bit (s0 / s1) is processed by comparing the difference signal of the rad signal of the switch generator 75 to the VC mapping control block 77 to the C0 / C1 line. Control block 78.

On the other hand, referring to the operation of the conventional VC mapping system as described above, the corresponding mode is first selected in the lmode terminal of the STM-1 frame counter 71, for example, T1 or E1 mode is set. When the VC mapping system is first set up, various clock signals are input to each of the individual mapping device blocks 70A-N. For example, wck, rck, and the like are supplied. In addition, the write address generator 73 and the read address generator 75 of each of the individual mapping device blocks 70A-N generate the wad signal and the rad signal, respectively, and input them to the ELB 74. At this time, the CO / C1 control block 78 of each individual mapping device block 70A-N reads the wad signal and the rad signal from the write address generator 73 and the read address generator 75, according to the difference signal. A control signal for determining whether to process -bit (s0 / s1) is input to the VC mapping control block 77 through the C0 / C1 line.

At this time, the signal of C0 / C1 may have "00", "01", "10", "11" for stuff, for example, the VC mapping control block 77 is the value of the CO / C1 " 00 " reflects 2 bits, " 01 "," 10 ", 1 bit, and " 11 " reflects 0 bits into S0 / S1 of the VC1 _X format.

Accordingly, the STM-1 frame counter 71 controls the C0 / C1 control block 78 of each of the individual mapping device blocks 70A-N while the individual mapping device blocks 70A-N are operated by the above process. ) Inputs the v1 enable signal v1en and inputs the VC address signal to the channel MUX block 72 through the VCaddr line. Then, the channel MUX block 72 selects and multiplexes any one of 84 individual mapping device blocks 70A-N in the case of T1 according to the VCaddr signal of the STM-1 frame counter 71. When the first individual mapping device block 70A is selected, the channel MUX block 72 reads data from the first individual mapping device block 70A and transmits the data to the next STM-1 transmitter.

Accordingly, as in the above process, the channel MUX block 72 sequentially selects the individual mapping device blocks 70A according to the VCaddr signal input from the STM-1 frame counter 71 to perform normal data multiplexing.

However, in the conventional VC mapping system as described above, since the CO / C1 control block 78 for reducing the weighting time jitter must be separately provided to determine the stuff for each individual mapping device block 70A-N, VC mapping. The drawback was that the complexity for the implementation of the system increased significantly.

Accordingly, the present invention has been invented to solve the above problems, by integrating the C0 / C1 control blocks provided in the respective mapping device blocks into one control block, thereby simplifying the internal logic circuit of the VC mapping system. The purpose of the present invention is to provide a SDH type VC mapping system and a control method thereof, which can reduce the manufacturing cost of the VC mapping system accordingly.

Another object of the present invention is to provide a VC mapping system and a control method of the SDH method that can significantly reduce the weighting time jitter by implementing the mapping device block using a time-divided weighting time jitter reduction algorithm for each channel MUX block. have.

In order to achieve the above object, the present invention provides a separate mapping device block for reading data from each individual channel and outputting the data to a higher hierarchy device, and STM-1 for generating control signals capable of multiplexing the individual mapping device blocks. A frame counter, an integrated C0 / C1 control block for determining CO / C1 values for stuff-bit processing according to the frame ratio 8 signal and the multi-frame address signal of the STM-1 frame counter, and from the STM-1 frame counter. The present invention provides an SDH type VC mapping system consisting of channel MUX blocks sequentially multiplexing individual mapping device blocks according to an input VC address signal.

Another feature of the present invention is to generate a frame pulse signal for generating a frame pulse signal for implementing a 1/3 UI method to reduce the weighting time jitter of the system clock, and generated by the frame pulse generation step for each mode A non-pore-dress signal generation step for generating a non-foredress from a frame pulse, and a non-fore-dress signal generated by this non-fore-dress signal generation step are multiplexed according to the line mode to select an arbitrary channel, and the write address signal and read of the selected channel A control method of an SDH type VC mapping system comprising a data multiplexing step of determining C0 / C1 from an address signal and multiplexing actual VC data.

1 is a block diagram illustrating a conventional VC mapping system of the SDH method.

2 is a block diagram illustrating a VC mapping system of the present invention.

3 is a block diagram illustrating an integrated CO / C1 control block of the present invention.

4 is a flowchart of the present invention.

5A to 5F are waveform diagrams for explaining the frame pulse signal of the present invention.

6 (a)-(b) are waveform diagrams illustrating the C0 / C1 signal of the present invention.

<Detailed Description of Codes>

1A-N: Individual Mapping Device Block 2: STM-1 Frame Counter

3: Integrated C0 / C1 Control Block 4: Channel MUX Block

5: CO signal generator 6: Frame pulse generator

7: non-pore dress generator 8: mux

9: C1 signal generator 10: Write address generator

11: ELB 12: Lead Address Generator

13: S / P converter 14: VC mapping control block

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2, the apparatus of the present invention multiplexes individual mapping device blocks 1A-N for reading data from each individual subscriber line and outputs the data to a higher hierarchy device. STM-1 frame counter 2 for generating control signals, and stuff-bit processing is performed according to the frame ratio 8 signal fpb8 and the multi-frame address signal mfpad of the STM-1 frame counter 2. An integrated C0 / C1 control block (3) for determining a CO / C1 value for the first and individual mapping device blocks (1A-N) according to the VC address signal input from the STM-1 frame counter (2) It consists of a channel MUX block 4 for transmission to an STM-1 transmitter (not shown).

The integrated CO / C1 control block 3 includes a CO signal generator 5 for outputting a predetermined CO signal according to the mfpad signal of the STM-1 frame counter 2, as shown in FIG. Frame pulses for outputting a plurality of frame pulse signals for selecting individual mapping device blocks 1A-N by allocating a system clock in 1/3 UI manner according to the fpB8 signal of the STM-1 frame counter 2 A non-pore dress generator that selects any one of a plurality of frame pulse signals input from the frame pulse generator 6 according to the mfpad signal and the lmode signal of the STM-1 frame counter 2 and outputs a bad value. (7) and a MUX (8) for outputting the wad signal and the rad signal of the corresponding individual mapping device block (1A-N) selected in accordance with the bad signal input from the non-pore-dress generator (7), and this MUX (8) C1 signal generator 9 according to wad and rad signals output from It is.

Here, the 1/3 UI method refers to a method provided in the IEEE TRANSACTIONS ON COMMUNICATIONS, VOL.37.11, NOVEMBER 1989.

In addition, referring to an example of a plurality of individual mapping device blocks formed for each mode channel in the VC mapping system of the present invention as described above, a write address generator for generating a write address wad according to the input write clock signal wck. (10), an elastic buffer 11 (hereinafter referred to as ELB) for reading and storing data from the individual subscriber line through the write data (wdt) line and a read address (rad) signal to the ELB 11; The read address generator 12 to supply, the S (serial) / P (parallel) converter 13 which outputs the serial data output from the said ELB 11 in parallel, and this S / P converter 13 It consists of a VC mapping control block 14 for receiving the data transmitted through the channel MUX block (4).

Next, a control method of the system of the present invention as described above will be described.

First, the system of the present invention proceeds to the system setup step (S1) from the initial state as shown in Figure 4 to set the mode and set up the system. After the system setup step (S2), the system proceeds to the frame pulse generation step (S2) for each mode to generate a frame pulse signal corresponding to each mode, for example, T1-T2 and E1 signals, in a 1/3 UI manner. do. In addition, after the frame pulse generation step S2 for each mode, the non-foredressed signal generation step S3 may be performed to select a corresponding individual mapping device block among the plurality of frame pulses generated by the frame pulse generation step for each mode. Select the signal of and generate it as a non-pore dress. On the other hand, after the non-foredressed signal generation step S3, the data multiplexing step S4 is performed to multiplex wad and rad of the corresponding channel from the respective mapping device block according to the non-foredressed signal generated by the non-foreddressed signal generation step. do.

In other words, the corresponding mode is first set to the lmode terminal of the STM-1 frame counter 2, for example, the T1-T2 or E1 mode is set. At this time, the mode signal is also input to the frame pulse generator 6 of the integrated CO / C1 control block 3. When the VC mapping system is first set up, various clock signals are input to each of the individual mapping device blocks 1A-N. For example, wck, rck, and the like are supplied.

In addition, the write address generator 10 and the read address generator 12 of each of the individual mapping device blocks 1A-N generate the wad signal and the rad signal, respectively, so that the ELB 11 and the integrated CO / C1 control block ( It is also input to the MUX 8 of 3), respectively.

At this time, the STM-1 frame counter 2 inputs a v1 enable signal v1en, a fpb8 signal, and a mfpad signal to the integrated C0 / C1 control block 3, respectively, and inputs a VC address signal through a VCaddr line to a channel MUX. Input to block (4).

Then, the frame pulse generator 6 allocates a system clock according to the fpB8 signal of the STM-1 frame counter 2, for example, a system clock signal of 19 [MHZ] in a 1/3 UI manner, thereby providing each individual mapping device. As shown in (b) to (f) of FIG. 5 in which blocks 1A-N can be selected, a plurality of frame pulse signals, that is, B8ad (8 clocks ahead of the frame sync signal) and B6ad (6 clocks ahead of the frame sync signal) , B4ad (4 clocks ahead of the frame sync signal), B2ad (2 clocks ahead of the frame sync signal), B1ad (1 clock ahead of the frame sync signal), B1ad (1 clock ahead of the frame sync signal), B0ad (frame sync signal) The zero clock advance signal is generated and output to the non-foredress generator 7. Accordingly, the non-pore dress generator 7 selects one of a plurality of frame pulse signals input from the frame pulse generator 6 according to the mfpad signal and the lmode signal of the STM-1 frame counter 2 and outputs a bad value. In this case, among the B8ad, B6ad, B4ad, B2ad, B1ad, B1ad, and B0ad signals, for example, when the mode is T1, one of the non-pore dress signals is selected from B8ad, B4ad, and B0ad, and when T2, B2ad, B1ad, If any one of the b0ad signals is E1, one of the B6ad, B3ad, and b0ad signals is selected.

Here, the bad signal is a signal capable of selecting any one of a plurality of individual mapping device blocks 1A-N according to the set value.

For example, when the mode is T1 and the mfpad value is "00", the non-foredress generator 7 sets the B8ad signal 8 bits ahead of the frame synchronization signal as a bad signal and inputs it to the MUX 8. Then, the MUX 8 inputs the wad signal and the rad signal of the respective mapping device blocks 1A-N to the C1 signal generator 9 in accordance with the bad signal input from the non-pore address generator 7. Then, the C1 signal generator 9 generates the C1 signal for the stuff according to the difference signal between the corresponding wad signal and the rad signal inputted from the MUX 8, and corresponding individual mapping device as shown in FIG. It is input to the VC mapping control block 14 of blocks 1A-N, where the CO signal generator 5 is also shown in FIG. 6B according to the mfpad signal of the STM-1 frame counter 2. Likewise, the CO signal of a predetermined pattern is input to the VC mapping control block 14 of the corresponding individual mapping device blocks 1A-N.

By demultiplexing the determined C0 / C1 value, it is determined whether the S0 / S1 bit of the VC format is STUFF-DATA in the selected block.

Through the above process, the complexity and gate count of all channels can be reduced while reducing the weighting time jitter of VC DATA.

Accordingly, as in the above process, the channel MUX block 4 sequentially selects individual mapping device blocks 1A-N according to the VCaddr signal input from the STM-1 frame counter 2 to execute normal data multiplexing. do.

As described above, the present invention integrates the C0 / C1 control blocks provided in the individual mapping device blocks into one control block to multiplex the data for each mode while implementing a 1/3 UI weighting time jitter reduction algorithm. Since the internal logic circuit of the VC mapping system can be simplified, the manufacturing cost of the VC mapping system can be considerably reduced.

In addition, according to the present invention, while the weighting time jitter reduction algorithm implemented implements processing all modes of TI, E1, and T2 in one block, the actual implementation complexity is reduced more than that of the conventional algorithm.

Claims (10)

An individual mapping device block for reading data from each individual subscriber line and outputting the data to a higher level device, an STM-1 frame counter for generating control signals capable of multiplexing the individual mapping device blocks, and the STM-1 frame counter An integrated C0 / C1 control block for determining each CO / C1 value for stuff-bit processing according to the frame ratio 8 signal and the multi-frame address signal of the selected device, and selecting each individual mapping device block, and inputting from the STM-1 frame counter. The VC mapping system of the SDH method, characterized in that the channel MUX block for sequentially multiplexing the individual mapping device blocks according to the VC address signal. The system according to claim 1, wherein the integrated CO / C1 control block outputs a CO signal having a predetermined pattern according to the mfpad signal of the STM-1 frame counter, and a system according to the fpB8 signal of the STM-1 frame counter. A frame pulse generator for outputting a plurality of frame pulse signals for selecting respective individual mapping device blocks by allocating a clock in a 1/3 UI method, and a frame pulse generator according to the mfpad signal and lmode signal of the STM-1 frame counter. A non-pore dress generator that selects one of a plurality of frame pulse signals inputted from the device and outputs a bad value, and a MUX that outputs the wad signal and the rad signal of the corresponding individual mapping device block selected according to the bad signal input from the non-pore-dress generator. And a C1 signal generator according to the wad signal and the rad signal output from the MUX. The frame pulse generator of claim 2, wherein the frame pulse generator includes a B8ad eight clocks ahead of the frame synchronization signal allocated to the system clock in 1/3 UI mode, a B6ad six clocks ahead of the frame synchronization signal, and a B4ad four clocks ahead of the frame synchronization signal. B2ad two clocks ahead of the synchronization signal, B1ad one clock ahead of the frame synchronization signal, B1ad one clock ahead of the frame synchronization signal, and B0ad signal identical to the frame synchronization signal to generate and output the VC mapping system. A frame pulse generation step for generating a frame pulse signal corresponding to each mode signal in a 1/3 UI method, and a non-foredress generated from the frame pulses generated by the frame pulse generation step for each mode. The non-address signal generated by the address signal generation step and the non-fore-dress signal generation step are multiplexed according to the line mode to select an arbitrary channel, and C0 / C1 is determined from the write address and read address of the selected channel to determine the actual VC. Control method of the VC mapping system of the SDH method, characterized in that consisting of a multiplexing step of multiplexing data. 5. The method of claim 4, wherein the non-pore address signal during the non-fore-dress signal generation step is a T1 signal in which a system clock signal is allocated in a 1/3 UI method. 5. The method of claim 4, wherein the non-pore address signal during the non-fore-dress signal generation step is a T2 signal in which a system clock signal is allocated in a 1/3 UI manner. 5. The control method of claim 4, wherein the non-pore address signal during the non-fore-dress signal generation step is an E1 signal in which a system clock signal is allocated in a 1/3 UI method. 6. The SDH type VC mapping system according to claim 5, wherein the non-pore address signal includes B8ad 8 clocks ahead of the frame synchronization signal, B4ad 4 clocks ahead of the frame synchronization signal and B0ad 0 clocks ahead of the frame synchronization signal. Control method. The VC mapping system of claim 6, wherein the non-pore address signal includes B2ad two clocks ahead of the frame synchronization signal, B1ad one clock ahead of the frame synchronization signal, and B0ad ahead of the frame synchronization signal. Control method. 8. The SDH type VC mapping system of claim 7, wherein the non-foredressed signal includes B6ad six clocks ahead of the frame sync signal, B3ad three clocks ahead of the frame sync signal, and B0ad ahead of the frame sync signal. Control method.