JP2597041B2 - FIFO memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a first-in first-out (FIFO) memory device used as a buffer for communication between arithmetic processing units, for example.

[Prior art]

The FIFO memory device is a device used for transferring data between arithmetic processing units or inserting a buffer in the middle of a data transmission path to adjust the transmission speed. FIG. 5 is a block diagram of a conventional FIFO memory device (hereinafter, referred to as "FIFO"). Reference numeral 101 denotes a memory cell; 102, an input control circuit for controlling data input to the memory cell 101; An output control circuit that controls the output of data from the memory cell 101; 104 designates a position where data is to be written to the memory cell 101;
Reference numeral 105 designates a position from which data is read from the memory cell 101, and a read pointer consisting of a register which is incremented each time the data is read, and 201 is a detection logic for detecting the state of accumulation of data in the FIFO. The detection logic 201 outputs a full signal when the memory cell 101 is full, that is, when the FIFO is full. The detection logic 201 is connected to the memory cell 1
When the stored data amount of 01 becomes zero, that is, when the FIFO becomes empty, an empty signal is output. 11
A reset logic 5 resets the write pointer 104 and the read pointer 105. FIG. 6 shows an example of use of the FIFO. In this use case,
The FIFO 303 is connected between the arithmetic processing unit 301 and the arithmetic processing unit 302. Then, as a buffer for transmitting data from the arithmetic processing unit 301 to the arithmetic processing unit 302,
IFO303 is used. First, a case where data is input to the FIFO 303 will be described. The arithmetic processing unit 301 outputs the data to the DI line, outputs the shift impulse to the SI line, and transmits the data into the FIFO 303. Here, the same operation is performed even when the bit length of the data in the FIFO 303 is a plurality of bits. Then, the FIFO 303 writes the data at the position of the memory cell 101 specified by the write pointer 104. And the write pointer
104 is incremented. Here, for example, when the memory cell 101 is a ring buffer, the value obtained by adding 1 to the value of the register forming the write pointer 104 matches the value of the register forming the read pointer 105. If so, the detection logic 201 determines that the FIFO 303 as the buffer is full, and outputs a full signal to the arithmetic processing unit 301. In addition, the above-mentioned FIFO303
Is not full, the input control circuit 102
An input ready signal indicating that data can be input to the IFO 303 is output to the arithmetic processing unit 301. Therefore, the arithmetic processing unit 301 converts the data into the F
Before inputting to the IFO 303, it is necessary to check the full signal or the input ready signal to confirm that data input to the FIFO 303 is possible.
Then, data can be input to the FIFO 303 until the full signal becomes active or the input ready signal becomes inactive.
Next, a case where data is output from the FIFO 303 to the arithmetic processing unit 302 will be described. First, when the arithmetic processing unit 301 outputs a reset signal to the FIFO 303, the reset logic 115 of the FIFO 303 resets the write pointer 104 and the read pointer 105 to a value indicated by the write pointer 104 and the read pointer 105. Becomes zero, and there is no data inside the FIFO (initialized state). Then, when the value indicated by the write pointer 104 and the value indicated by the read pointer 105 match, the detection logic 201 determines that there is no data inside the FIFO 303, and outputs an empty signal to the arithmetic processing unit 302.
Output to Next, when the arithmetic processing unit 301 inputs data to the FIFO 303, the write pointer 104 is incremented. Then, the detection logic 201 makes the empty signal inactive. Also, the above FIFO
When the 303 is outputting data to the DO line, the output control circuit 103 activates the output ready signal. In order to avoid an underflow of the data in the FIFO 303, the arithmetic processing unit 302 is not necessarily required to read the data from the FIFO 303, and the empty signal is inactive or the output ready signal is active. You need to make sure that
After reading the data output from the FIFO 303 to the DO line, the arithmetic processing unit 302 outputs the shift-out pulse to the SO
Output to line. Then, the read pointer 105 of the FIFO 303 is incremented, and the FIFO 303 stores the next data.
Output to DO line. Thus, the arithmetic processing unit 301
Thus, the arithmetic processing unit 302 can first read the data written in the FIFO 303 from the FIFO 303 first. By the way, generally, an arithmetic processing unit uses an 8-bit or 16-bit processor, and thus generates a transmission code having a plurality of bit lengths. FIG. 8A is a diagram showing an example of a fixed-length code among transmission codes of a plurality of bit lengths. In the fixed length code, a binary transmission code is assigned to each of the code words 1, 2, 3, 4, and 5. When the transmission code is limited to ^{25 or} less, the transmission code length of the transmission code is at most 5 bits, and the transmission code of 8 bits or 16 bits generally used in the arithmetic processing unit is used. There is no need to transmit bits. Therefore, the arithmetic processing unit may perform the process of shifting out the lower 5 bits of the 8-bit or 16-bit transmission code. FIG. 8 (b) is a diagram showing an example of a variable length code among transmission codes of a plurality of bit lengths. In the variable length codes, transmission codes as shown in FIG. 8B are assigned to the code words 1, 2, 3, 4, and 5, respectively. For example, when transmitting a code word of 2, this code word is converted into a transmission code of 01 (binary number) and transmitted. When transmitting a code word of 4, this code word is transmitted.
It is converted to a transmission code of 0001 (binary number) and transmitted. As described above, in the variable length code, the transmission code length of the transmission code to be transmitted to the transmission path is changed according to the code word to be transmitted. In general, a short transmission code is assigned to a code word having a high frequency of appearance, so that the overall transmission code length is shortened. In addition, in order to generate a transmission code having a plurality of bits, a method called table conversion is generally used. FIG. 5 (c) is a diagram showing an example of the table conversion. Table conversion, the code word and the inside in the memory address, by storing a transmission code (b ₇ ~b ₀₎ and the transmission code length corresponding to the code words (b ₁₅ ~b ₈₎ in advance, code Convert words to transmission code and transmission code length.

[Problems to be solved by the invention]

By the way, as shown in FIG. 7, the conventional F is used as a data buffer between the transmission control unit 402 and the arithmetic processing unit 401.
When the IFO 303 is used, since the arithmetic processing unit 401 uses an 8-bit or 16-bit processor,
It is more efficient to collectively process data processing with a plurality of bits, and a FIFO having a plurality of bits is desired as the FIFO 303. However, since the transmission control unit 402 generally handles serial data, the FIFO 303 uses a one-bit configuration that inputs and outputs data on a bit-by-bit basis. For this reason, the arithmetic processing unit 401 needs to perform parallel-to-serial conversion in which a transmission code of a plurality of bits is sequentially shifted by the transmission code length and converted into serial data. When such parallel / serial conversion is performed by the arithmetic processing unit 401, the input / output processing of the arithmetic processing unit 401 becomes complicated, and there is a problem that the data processing speed of the arithmetic processing unit 401 is reduced. Also, if an external ROM is used to perform parallel-to-serial conversion of a transmission code having a multiple bit length generated by the arithmetic processing unit 401,
There is a problem that the circuit scale for the interface between the ROM and the FIFO becomes large. Therefore, an object of the present invention is to provide an input control circuit having a parallel-in / serial-out function so that an arithmetic processing unit connected to the input side does not need to perform parallel-to-serial conversion. An object of the present invention is to provide a FIFO memory device that does not reduce the processing speed.

[Means for Solving the Problems]

In order to achieve the above object, a FIFO memory device of the present invention comprises a memory cell, an input control circuit for controlling input of data to the memory cell, and a write position of data to be input to the memory cell to the memory cell. A write pointer that increments each time the data is written, an output control circuit that controls the output of data from the memory cell, and a read position of the data that is output from the memory cell from the memory cell. A read pointer that increments each time the data is read, and a FIFO memory device that includes a detection logic that detects that the amount of data in the memory cell is full and outputs a full signal indicating data full. The input control circuit receives the shift-in signal, latches the parallel input data, and A shift register that sequentially shifts the latched parallel input data in response to a clock signal; latches data indicating the number of data to be input to the memory cell in response to a shift-in signal; A down counter that receives and counts down, receives a borrow signal output by the down counter and a full signal output by the detection logic, and when the memory cell is full and when the counter value of the down counter is zero. A clock control circuit for preventing the clock signal from being input to the shift register and the down counter, the parallel control circuit latching the parallel input data latched by the shift register by the number represented by the data latched by the down counter. To the input data length. It has a parallel-in / serial-out function that can be freely changed.

[Action]

The parallel input data is latched in the shift register that has received the shift-in signal. Data representing the number of data to be input to the memory cell is latched by the down counter receiving the shift-in signal. Only when the memory cell is not full and the counter value of the down counter is not zero, a clock signal is input to the down counter and the shift register under the control of the clock control circuit. Then, the parallel input data latched by the shift register is shifted into the memory cell by one bit by the number represented by the data latched by the down counter, based on the clock signal. In other words, the data length on the input side can be arbitrarily changed,
This enables not only parallel-serial conversion and buffering of fixed-length data, but also parallel-serial conversion and buffering of variable-length codes having different code lengths for each code.

【Example】

Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 is a block diagram of a FIFO according to an embodiment of the present invention.
In this embodiment, the parts other than the input control circuit 120 are the same as the conventional FIFO shown in FIG. 5, so the same parts are assigned the same numbers, and only the parts related to the input control circuit 120 are emphasized. explain. In FIG. 1, 121 latches n-bit parallel input data DIn at the rise of a shift impulse SI as a shift-in signal, and at the rise of a down pulse signal / DOWN as a clock signal, converts the latched parallel input data DIn. This is a shift register for shifting. When the control signal SH is at a high level, the shift register 121 outputs the parallel input data DI from the output terminal Qn to the output terminal Qa.
n while the control signal SH is at a low level, the parallel input data DI is transferred from the output terminal Qa to the output terminal Qn.
Shift n. Reference numeral 124 denotes a data selector for switching a position from which the shift register 121 takes out the shifted data in accordance with a shift direction of the data. 122 latches input data CIm indicating the number of shifts of m bits at the rising edge of the shift impulse SI and outputs the down pulse signal
This is a down counter that counts down at the rising edge of / DOWN. When the count value of the down counter 122 becomes zero, the down counter 122
Set BORROW to low level. At the time of reset, the reset logic 115 receiving the reset signal outputs the shift register 121, the down counter 122, and the write pointer 1
04, the read pointer 105 is initialized. The original oscillation clock signal is a signal for generating operation timing of the internal circuit of the FIFO. FIG. 2 is a timing chart of signals on the input side of the FIFO. As shown in FIG.
When the input data DIn to the counter 121 is set to 5, the input data CIm to the down counter 122 is set to 3, and the shift impulse SI is input to the shift register 121 and the down counter 122, the down counter 12 is set at the rise of the shift impulse SI.
The counter value of 2 becomes 3, and the output data of the shift register 121 becomes 5. At this time, the down counter 12
Since the counter value of 2 is not zero, the borrow signal / BORROW
Becomes a high level. In order to synchronize the borrow signal / BORROW with the original oscillation clock signal, the flip-flop 123 and the AND gate 125 control the borrow-B signal.
I am making / BORROW-B. (The above shift impulse SI
And the original oscillation clock signal are in a synchronous relationship,
There is no need to generate the borrow-B signal / BORROW-B. )
Then, the borrow-B signal /
An AND between BORROW-B and the original oscillation clock signal is taken to generate a down pulse signal / DOWN as a clock signal. The down pulse signal / DOWN is supplied to the shift clock of the shift register 121 and the down counter 1
Functions as 22 down pulses. When the FIFO is full, the down pulse signal / DOW is used to prevent data from shifting into the memory cell 101.
N is gated with the full signal output by the detection logic 201, and when the FIFO is full, the down pulse signal / D
OWN is stored in the shift register 121 and the down counter 122.
I try not to enter it. The above flip-flops 12
3 and the AND gate 125 and the AND gate 126 constitute a clock control circuit. In the above configuration, when one pulse of the down pulse signal / DOWN is generated from the clock control circuit, the shift register 121 moves the shift register 121 to the position of the memory cell 101 indicated by the write pointer 104 at the rise of the pulse. The data at the output terminal Qa is written via the data selector 124. At the same time, the write pointer 104 is incremented. At this time, the down counter 122 is decremented so that the counter length becomes 2, and the shift register 121 shifts the data of the shift register 121 by 1 bit, and outputs the data at the output terminal Qb to the output terminal Qb. Shift to Qa. Thus, the down pulse signal / DOWN is output from the clock control circuit.
Each time one pulse is generated, the shift register 121
Is shifted into the memory cell 101 one bit at a time. When the counter value of the down counter 122 becomes zero, the borrow signal / BORR
OW becomes low level, the pulse of the down pulse signal / DOWN does not occur, and the data of the shift register 121 does not shift into the memory cell 101. The borrow signal / BORROW and the full signal are OR gate 1
27 makes an input ready signal. This input ready signal indicates that data input to the input control circuit 120 is possible. FIG. 3 shows an example of use of the FIFO. In this use case,
The FIFO 701 is connected between the arithmetic processing unit 702 and the transmission control unit 703, and 10-bit fixed-length data is input to the input side of the FIFO 701. The terminals Ci ₀ , Ci ₂ and Ci _{4 to} Ci _{n of the} FIFO 701
Is grounded, and terminals Ci ₁ and Ci ₃ are connected to a + 5V power supply.
The input data CIm to the down counter of the FIFO 701 is fixed at 10. Since only the lower 10 bits of the 16 bits are shifted into the FIFO 701, the data
Only the data buses Di _{0 to} Di _{9 of the} FO 701 are connected to the data buses D _{0 to} D ₉ of the arithmetic processing unit 702. In this connection state, when the input ready signal becomes active, the arithmetic processing unit 702 transmits the shift impulse SI to the FIFO 701.
Output to Then, the data on the data buses D _{0 to} D ₉ of the arithmetic processing unit 702 is stored in the data buses Di ₀ to Di _{0 of the} FIFO 701.
Shift into Di ₉ . The FIFO 701 can convert the parallel data on the data buses Di _{0 to} Di ₉ into serial data and output the serial data to the transmission control unit 703 from the DO terminal. FIG. 4 shows another usage example of the FIFO. In this usage example, the FIFO 801 is connected between the arithmetic processing unit 802 and the transmission control unit 803, and variable-length data of 8 bits or less is input to the input side of the FIFO 801. The terminals Ci _{0 to} Ci ₃ of the FIFO 801 are connected to the data buses D _{8 to} D of the arithmetic processing unit 802 so that the down counter of the FIFO 801 can count from 1 to 8.
Connected to ₁₁ . Terminal Ci ₄ ~Ci _n of the FIFO is grounded. Also, the FIFO 801 is controlled so that variable length data of up to 8 bits can be input to the shift register of the FIFO 801.
A data bus Di ₀ -DI ₇ of connecting to a data bus D ₀ to D ₇ of the processing unit 802. In this connection state, when the input ready signal becomes active, the arithmetic processing unit 802 outputs a shift impulse SI to the FIFO 801. Then, the arithmetic processing unit 802 outputs the contents of the variable-length data conversion memory (data bus D) as shown in FIG.
₈ High Byte b ₈ ~b ₁₅ corresponding to to D ₁₅ represents the transmission code length, lower byte b ₀ corresponding to the data bus D ₀ to D ₇ ~
b ₇ represents a transmission code. ), Directly above FIFO801
Parallel input. Then, the FIFO 801 converts the parallel input data into serial data,
The signal can be output from the DO terminal to the transmission control unit 803.

【The invention's effect】

As apparent from the above description, the FIFO memory device of the present invention uses the clock signal controlled by the clock control circuit to transfer the parallel input data latched in the shift register to the down counter only when the memory cell is not full. As many as the number represented by the latched data can be sequentially shifted into the memory cells. Therefore, according to the present invention, the data length on the input side can be arbitrarily changed, and not only parallel-serial conversion and buffering of fixed-length data, but also parallel-serial Conversion and buffering are possible. For this reason, according to the present invention, unlike the related art, the arithmetic processing unit connected to the input side does not need to perform parallel-to-serial conversion, and improves the data processing speed of the arithmetic processing unit as compared with the related art. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a FIFO memory device according to the present invention, FIG. 2 is a timing diagram of signals on the input side of the above embodiment, FIGS. FIG. 5 is a block diagram of a conventional FIFO memory device, and FIGS.
FIG. 8 is a diagram illustrating an example of use of the IFO memory device, and FIG. 8 is a diagram illustrating a transmission code having a plurality of bits. 101 ... memory cells, 102, 120 ... input control circuit, 103 ...
... output control circuit, 104 ... write pointer, 105 ... read pointer, 115 ... reset logic, 121 ... shift register, 122 ... down counter.

Claims (1)

(57) [Claims] A memory cell, an input control circuit for controlling input of data to the memory cell, a write position of data to be input to the memory cell to the memory cell, and each time the data is written A write pointer to increment, an output control circuit for controlling the output of data from the memory cell, and a read position from the memory cell for data output from the memory cell,
A FIFO memory device comprising: a read pointer that increments each time the data is read; and detection logic that detects that the amount of data in the memory cell is full and outputs a full signal indicating data full. An input control circuit receives a shift-in signal, latches parallel input data, and receives a clock signal to sequentially shift the latched parallel input data. Latching data representing the number of data to be input to the memory, receiving a clock signal and counting down; receiving a borrow signal output by the down counter and a full signal output by the detection logic; If the cell is full and the down counter A clock control circuit for preventing the clock signal from being input to the shift register and the down counter when the data value is zero, the parallel input data latched by the shift register being converted to data latched by the down counter. A FIFO memory device having a parallel-in / serial-out function capable of arbitrarily changing the input data length by sequentially shifting in the memory cells by the number represented by.