SU1736003A1 - Decoder for binary code of restraint layout space - Google Patents

Abstract

The invention relates to computing and can be used in digital signal recording systems, for example, on magnetic optical disks. The invention makes it possible to simplify a device for decoding a serial binary code at intervals of a limited format length (2.7). The device contains a shift register 1, a memory element 2 and a computing unit 3 that implements the Boolean function AND F + AD + HS + GL (where A, D, D, F, 3, L and I are the values of the logical variables) performed on the element 8 2-2-2-2И-4ИЛИ-НЕ. 1 hp ff, 3 ill.

Description

(L

with

The invention relates to a computing technique and can be used in digital signal recording systems, for example, on magnetic optical disks.

The closest in technical essence to the present invention is a device containing an eight-bit shift register, the outputs of which form signals corresponding to the last eight bits of the input code sequence, the shift input serial input is the information input of the device, the sync input is the first clock input of the device, and also combinational logic circuit performing logic operation with + еЫ- + bdf + af, the output of which is connected to the input of the memory element whose sync input is are second clock

input device, and the output - the device output.

A disadvantage of the prior art is complexity.

The purpose of the invention is to simplify the device.

Figure 1 shows the functional diagram of the device; Fig. 2 is a diagram of a specific embodiment of the device; FIG. 3 shows timing diagrams explaining the operation of the device.

The device contains a shift register 1, a memory element 2, a computing unit 3 that implements the Boolean function AND F + AD + HS + GL, where A, D, D, F, L and I are the values of the logical variables.

Positions 4-6 denote, respectively, the information input, the first and second clock inputs of the device, the position 7 denotes the device output.

J

from o

Sde

J 1

Block 3 is made on the element E-T-2-2I-4 OR-NOT 8.

In the diagrams (fig. 3) the following signals are indicated: a - signal at the input; b - input signal 5; c - signal at the output of the first bit of the register (absent in Fig. 1); g - signal at the output of the second bit of register 1; d - signal at the output of the third bit of register G; e is the signal at the output of the fourth bit of register 1 (absent in Fig. 1); W is the signal at the output of the n of that register register 1; h is the signal at the output of the sixth register bit 1} and is the signal at the output of block 3; K - signal at the input 6, l - signal at the output 7.

The device works as follows.

The input code sequence is fed to the information input k of the device synchronously with the clock frequency supplied to the clock input 5 of the device. On the edges of the clock pulses, the code sequence advances along the shift register 1, forming the first through sixth signals at the outputs of its bits. Unit 3, to the inputs of which signals are received from the information input k of the device, the outputs of the second, third, fifth, and sixth bits of the shift register 1 and the output of the memory element 2, generates a signal in accordance with the Boolean expression IF + BP + HZ + CH , from which, using the memory element 2, the information sequence is selected from the edges of the clock pulses fed to the clock input 6 of the device.

Memory element 2 may be executed on an opaque D flip-flop.

Claims (2)

1. A device for decoding serial binary code at intervals of a limited length of form 360034 a mat (2.7) containing a shift register and a memory element whose output is a device output, . the pe-j shifter serial input is connected to the information input of the device, the shift register clock input is the first clock input of the device, tg is characterized by the fact that, in order to simplify the device, a computing unit is introduced into it that implements the Boolean function I Ж + + Aq + ГЗ + ГЛ, where А, Г, Д, Ж, 3, 15 AND and L - values of logical variables, the first input of which is connected to the output of the memory element, the outputs of the second, third, fifth and sixth bits of the shift register are connected 20 respectively to the second, third, fourth and fifth inputs of the computing unit that implements the Boolean function I F + Dd n-GZ + CH, the output of which is connected to the information input of the memory element whose synchronous input is the second clock input of the device, the sixth input computing unit that implements the Boolean function And F + HELL + GZ + 10 + is connected to the information input of the device. 2. The device according to p. Is distinguished by the fact that the computing unit that implements the Boolean function I F + AD + GZ + GL, is made on 35 element 2-2-2-2И - {(OR-NOT, the output of which is the output of the block, the first input of the first element AND is the first input of the block, the second input of the first element AND is combined with the first input of the second element AND and is the second the input of the block, the first input of the third element I is the third input of the block, the first and second inputs of the fourth element I are combined and 5 are the fourth input of the block, the second inputs of the second and third elements AND are respectively the fifth and neck inputs of the block. 40 Ј009Ш Figz