CA1322032C - Serial data handling circuit - Google Patents
Serial data handling circuitInfo
- Publication number
- CA1322032C CA1322032C CA000607922A CA607922A CA1322032C CA 1322032 C CA1322032 C CA 1322032C CA 000607922 A CA000607922 A CA 000607922A CA 607922 A CA607922 A CA 607922A CA 1322032 C CA1322032 C CA 1322032C
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- Canada
- Prior art keywords
- signal
- clock signal
- output
- shift register
- data
- Prior art date
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Shift Register Type Memory (AREA)
Abstract
SERIAL DATA HANDLING CIRCUIT
Abstract of the Disclosure For processing overhead information in a serial data stream of a transmission system, a shift register comprises a plurality of stages through which the data is shifted in dependence upon a high speed clock signal. Each shift register stage is responsive to a selection signal to retain its current state during cycles of the high speed clock signal. The selection signal is produced synchronously with the high speed clock signal, in dependence upon a control signal, by sampling a low speed clock signal with the high speed clock signal and gating the sampled signal with the control signal. The circuit facilitates writing data into and reading data from the shift register at different speeds.
Abstract of the Disclosure For processing overhead information in a serial data stream of a transmission system, a shift register comprises a plurality of stages through which the data is shifted in dependence upon a high speed clock signal. Each shift register stage is responsive to a selection signal to retain its current state during cycles of the high speed clock signal. The selection signal is produced synchronously with the high speed clock signal, in dependence upon a control signal, by sampling a low speed clock signal with the high speed clock signal and gating the sampled signal with the control signal. The circuit facilitates writing data into and reading data from the shift register at different speeds.
Description
2 0 3 2 SERIAL DATA HANDLING CIRCUIT
This invention relates to a serial data handling circuit, comprising a shift register and a control circuit therefor.
It is well known in a data transmission system to provide a serial data stream which contains, in addition to data being transmitted through the system.overhead information such as control and framing information. In order to facilitate the processing of such overhead information, for example for extracting and updating it at respective nodes of the system, it is known to shift the serial data through a shift register into which data can be written and from which datacan be read at different speeds, corresponding to high speed and low speed clocksignals.
To this end, it is known to multiplex high speed and low speed clock signals together to produce a multiplexed or gapped clock signal for the shift register. This presents problems, however, in that it uses inversion of the highspeed clock signal, and hence requires accurate control of the duty cycle of thehigh speed clock signal to avoid glitches and/or pulse width variations which may lead to data errors; even with such control glitches can occur depending on the states of the clock signals when a clock selection signal changes state; and it introduces significant delays which can complicate subsequent data processing.
2 0 Accordingly, an object of this invention is to provide an improved serial data handling circuit.
According to this invention there is provided a serial data handling circuit comprising: a shift register comprising a plurality of shift register stages for serially shifting data therethrough from an input to an output thereof in response to a first clock signal supplied thereto, the shift register including means responsive to a selection signal for selectively retaining a current statethereof during cycles of the first clock signal; and a control circuit includingmeans for sampling a second clock slgnal, having a frequency which is substantially the frequency of the first clock signal divided by the number of shift
This invention relates to a serial data handling circuit, comprising a shift register and a control circuit therefor.
It is well known in a data transmission system to provide a serial data stream which contains, in addition to data being transmitted through the system.overhead information such as control and framing information. In order to facilitate the processing of such overhead information, for example for extracting and updating it at respective nodes of the system, it is known to shift the serial data through a shift register into which data can be written and from which datacan be read at different speeds, corresponding to high speed and low speed clocksignals.
To this end, it is known to multiplex high speed and low speed clock signals together to produce a multiplexed or gapped clock signal for the shift register. This presents problems, however, in that it uses inversion of the highspeed clock signal, and hence requires accurate control of the duty cycle of thehigh speed clock signal to avoid glitches and/or pulse width variations which may lead to data errors; even with such control glitches can occur depending on the states of the clock signals when a clock selection signal changes state; and it introduces significant delays which can complicate subsequent data processing.
2 0 Accordingly, an object of this invention is to provide an improved serial data handling circuit.
According to this invention there is provided a serial data handling circuit comprising: a shift register comprising a plurality of shift register stages for serially shifting data therethrough from an input to an output thereof in response to a first clock signal supplied thereto, the shift register including means responsive to a selection signal for selectively retaining a current statethereof during cycles of the first clock signal; and a control circuit includingmeans for sampling a second clock slgnal, having a frequency which is substantially the frequency of the first clock signal divided by the number of shift
3 0 register stages of the shift register, independence upon the first clock signal, and means for producing said selection signal in dependence upon the sampled signal and a control signal supplied thereto; comprising rneans for producing from the sampled signal a pulse, having a duration equal to the period of the first clocksignal, during each period of the second ciock signal, and further rneans 3 5 'qF
i, '~
responsive to said pulse and to the control signal for producing the selection signal.
Preferably the means for sampling the second clock signal comprises a first flip-flop having a data input responsive to the second clock signal, a clock input responsive to the first clock signal, and an output at which the sampled signal is produced.
Desirably the means for producing said pulse comprises a second flip-flop having a data input coupled to an output of the first flip-flop and a clock input responsive to the first clock signal, and gating means coupled to outputs of thefirst and second flip-flops.
In a preferred embodiment of the invention, each shift register stage comprises a flip-flop having a clock input for receiving the first clock signal, a data input, and a data output, and means for selectively coupling to the data input in dependence upon the selection signal either the data output of the respectiveshift register stage or the data output from the preceding shift register stage.The invention will be further understood from the following description with reference to the accompanying drawings, in which:
Fig. 1 schematically illustrates a known form of serial data handling circuit;
Fig. 2 is a timing diagram illustrating signals which can occur in operation of the circuit of Fig. 1;
Fig. 3 schematically illustrates a synchronous serial data handling circuit in accordance with this invention;
Fig. 4 schematically illustrates a flip-flop stage of the circuit of Fig. 3;
2 5 and Fig. 5 is a timing diagram illustrating signals which can occur in operation of the circuit of Fig. 3.
Referring to Fig. 1, there is illustrated a known form of serial data handling circuit comprising a shift register 10 and a clock selection circuit 12. Serial data incoming on a line 14 is clocked through the shift register 10 to an outgoing serial data line .35 t .~
1322~32 16 under the control of a shift register clock signal supplied on a line 18 by the clock selection circuit 12.
The serial data can comprise for example overhead information in a high speed data transmission signal, for example of an optical transmission system, which is to be extracted and/or updated. To this end, the data is written into and read from the shift register 10 at different speeds, namely a high speed and a low speed. The shift register comprises n D flip-flops 20-1 to 20-n, where n is the number of bits of overhead information and is assumed here for example to be equal to 8, whose D inputs and Q outputs are coupled together in ser;es and all of whose clock inputs C are connected to the line 18.
The clock selection circuit 12 produces a gapped or multiplexed clock signal on the line 18, constituted by either a high speed clock signal HSC incoming on a line 22 or a low speed clock lS signal LSC supplied on a line 24, selected under the control of a control signal CS incoming on a line 26 and synchronous with the low speed clock signal LSC. To this end the clock selection circuit 12 comprises a D flip-flop 28 having a data input D supplied with the control signal CS, a clock input C supplied with the high speed clock signal HSC, and complementary outputs Q and -Q connected to first inputs of AND gates 30 and 32 respectively. The clock signals LSC and HSC are inverted by inverters 34 and 36 respectively, whose outputs are connected to second inputs of the gates 30 and 32 respectively.
The outputs of the gates 30 and 32 are connected to an OR gate 38, whose output is coupled to the line 18 via an inverting driver stage 40.
Fig. 2 illustrates the relative timing of signals which can occur in operation of the circuit of Fig. 1, it being assumed that n=8 so that there are nominally 8 periods of the clock HSC for each period of the clock LSC. As shown by asterlsks in Fig. 2, glitches and pulse width variations can occur in the signals at the output of the gate 32 and hence on the line 18 as the result of the relative timing of the signal at the output -Q of the flip-flop 28 and the inverted high speed clock signal at the output of the inverter 36, and similarly at the output of the gate 38 due to a state change of the flip-flop 28 when the gate 30 is enabled by a high level at the output of the inverter 34. Such deficiencies can lead to improper operation of the 13~2~32 shift register and consequent data errors. In addition, direct reclocking of the output data on the line 16 by the high speed clock signal HSC may be prevented due to the relative delay of the signal on the line 18 in the circuit 12.
These problems are reduced or avoided by the circuit of Fig. 3 in accordance with an embodiment of this invention.
Referring to Fig. 3, there is illustrated a serial data handling circuit which co~prises a controllable shift register 50 and a control circuit 52, to which data on the line 14 and the same signals HSC on the line 22, LSC on the line 24, and CS on the line 26 are supplied as in Fig. 1, and from which serial data is output on the line 16.
The controllable shift register 50 consists of n, for example 8, flip-flop stages (FFS) 54 each of which has the form illustrated in Fig. 4. Each FFS 54 has a clock input C which is connected to the HSC
line 22, two data inputs D and T, a data selection input S, and an output Q which is connected back to the D input of the FFS. All of the inputs S are connected to a selection control line 56 which is constituted by an output of the control circuit 52. The incoming data line 14 is connected to the T input of the first FFS 54, the Q output of the last FFS 54 is connected to the outgoing data line 16, and the Q output of each other FFS 54 is connected to the T input of the respective following FFS 54.
Referring to Fig. 4, each FFS 54 comprises a D flip-flop 58, an AND-OR gate represented by two AND gates 60 and 62 and an OR gate 64, and an inverter 66. The D and T inputs of the FFS 54 are connected to first inputs of the AND gates 60 and 62, whose outputs are coupled via the OR gate 64 to the data input D of the flip-flop 58. A clock input C and an output Q of the fl~p-flop 58 are connected to the input C and output Q, respectively, of the FFS 54. The selection input S is connected directly to a second input of the AND
gate 62, and via the inverter 66 to a second input of the AND gate 60.
Thus when a selection signal on the line 56 is a logic 0, the gates 60 and 62 are respectively enabled and disabled whereby for each FFS 54 the flip-flop 58 has its output Q coupled to its data input D, so that there is no change of the state of the flip-flop 58 when the flip-flop is triggered by pulses of the clock signal HSC present at 1322~32 the C input. Thus in this state of the signal on the line 56, the shift register 50 acts simply to retain the data therein withsut any shifting or changing thereof. Conversely, with a logic 1 state of the selection signal on the line 56, the T input of each FFS 54 is coupled to the data input D of the stage's flip-flop 58, whereby the shift register 50 acts normally as a shift register to shift data serially therethrough from the input line 14 towards the output line 16 with pulses of the high speed clock signal HSC.
The control circuit 52 comprises D flip-flops 70, 72, and 74 each having a data input D, a clock input C connected to the high speed clock signal line 22, and an output Q or -Q, two NAND gates 76 and 78, and a non-inverting driver stage, 80 which couples the Q
output of the flip-flop 74 to the output line 56 of the control circuit. The flip-flop 70 has its D input connected to the low speed clock signal line 24 and its Q output connected to a first input of the gate 76 and to the D input of the flip-flop 72, whose inverting output -Q is connected to a second input of the gate 76. The gate 78 has its inputs connected to the output of the gate 76 and the control signal line 26, and its output connected to the D input of the flip-flop 74.
Fig. 5 illustrates the relative timing of signals which can occur in operation of the circuit of Figs. 3 and 4, it again being assumed that n=8.
As shown by Figs. 3 and 5, the low speed clock signal LSC is effectively sampled by the flip-flop 70 synchronously with the high speed clock signal HSC. The flip-flop 72 and gate 76 result in the synchronous production at the output of the gate 76 of a negative-going pulse, having a duration equal to the period of the signal HSC, for each rising edge ~and hence in each period) of the signal LSC.
The gating of this signal at the output of the gate 76 with the control signal CS by the gate 78, and reclocking of its output by the signal HSC in the flip-flop 74, results in production of the signal on the line 56 in a manner such that this is substantially free of glitches and pulse width variations, whereby data errors are avoided.
Thus in the circuit of Figs. 3 and 4 the clock gapping or multiplexing of the prior art, and consequent glitches and data errors, are avoided. In addition, transitions of the output data on 13%2~3~
the line 16 all occur in response to rising edges of the high speed clock signal HSC, so that this signal HSC can be readily used directly for further processing of the output data.
Although a particular embodiment of the ;nvention has been described in detail, it should be appreciated that numerous modifications, variations, and adaptations may be made thereto within the scope of the invention as defined in the claims.
i, '~
responsive to said pulse and to the control signal for producing the selection signal.
Preferably the means for sampling the second clock signal comprises a first flip-flop having a data input responsive to the second clock signal, a clock input responsive to the first clock signal, and an output at which the sampled signal is produced.
Desirably the means for producing said pulse comprises a second flip-flop having a data input coupled to an output of the first flip-flop and a clock input responsive to the first clock signal, and gating means coupled to outputs of thefirst and second flip-flops.
In a preferred embodiment of the invention, each shift register stage comprises a flip-flop having a clock input for receiving the first clock signal, a data input, and a data output, and means for selectively coupling to the data input in dependence upon the selection signal either the data output of the respectiveshift register stage or the data output from the preceding shift register stage.The invention will be further understood from the following description with reference to the accompanying drawings, in which:
Fig. 1 schematically illustrates a known form of serial data handling circuit;
Fig. 2 is a timing diagram illustrating signals which can occur in operation of the circuit of Fig. 1;
Fig. 3 schematically illustrates a synchronous serial data handling circuit in accordance with this invention;
Fig. 4 schematically illustrates a flip-flop stage of the circuit of Fig. 3;
2 5 and Fig. 5 is a timing diagram illustrating signals which can occur in operation of the circuit of Fig. 3.
Referring to Fig. 1, there is illustrated a known form of serial data handling circuit comprising a shift register 10 and a clock selection circuit 12. Serial data incoming on a line 14 is clocked through the shift register 10 to an outgoing serial data line .35 t .~
1322~32 16 under the control of a shift register clock signal supplied on a line 18 by the clock selection circuit 12.
The serial data can comprise for example overhead information in a high speed data transmission signal, for example of an optical transmission system, which is to be extracted and/or updated. To this end, the data is written into and read from the shift register 10 at different speeds, namely a high speed and a low speed. The shift register comprises n D flip-flops 20-1 to 20-n, where n is the number of bits of overhead information and is assumed here for example to be equal to 8, whose D inputs and Q outputs are coupled together in ser;es and all of whose clock inputs C are connected to the line 18.
The clock selection circuit 12 produces a gapped or multiplexed clock signal on the line 18, constituted by either a high speed clock signal HSC incoming on a line 22 or a low speed clock lS signal LSC supplied on a line 24, selected under the control of a control signal CS incoming on a line 26 and synchronous with the low speed clock signal LSC. To this end the clock selection circuit 12 comprises a D flip-flop 28 having a data input D supplied with the control signal CS, a clock input C supplied with the high speed clock signal HSC, and complementary outputs Q and -Q connected to first inputs of AND gates 30 and 32 respectively. The clock signals LSC and HSC are inverted by inverters 34 and 36 respectively, whose outputs are connected to second inputs of the gates 30 and 32 respectively.
The outputs of the gates 30 and 32 are connected to an OR gate 38, whose output is coupled to the line 18 via an inverting driver stage 40.
Fig. 2 illustrates the relative timing of signals which can occur in operation of the circuit of Fig. 1, it being assumed that n=8 so that there are nominally 8 periods of the clock HSC for each period of the clock LSC. As shown by asterlsks in Fig. 2, glitches and pulse width variations can occur in the signals at the output of the gate 32 and hence on the line 18 as the result of the relative timing of the signal at the output -Q of the flip-flop 28 and the inverted high speed clock signal at the output of the inverter 36, and similarly at the output of the gate 38 due to a state change of the flip-flop 28 when the gate 30 is enabled by a high level at the output of the inverter 34. Such deficiencies can lead to improper operation of the 13~2~32 shift register and consequent data errors. In addition, direct reclocking of the output data on the line 16 by the high speed clock signal HSC may be prevented due to the relative delay of the signal on the line 18 in the circuit 12.
These problems are reduced or avoided by the circuit of Fig. 3 in accordance with an embodiment of this invention.
Referring to Fig. 3, there is illustrated a serial data handling circuit which co~prises a controllable shift register 50 and a control circuit 52, to which data on the line 14 and the same signals HSC on the line 22, LSC on the line 24, and CS on the line 26 are supplied as in Fig. 1, and from which serial data is output on the line 16.
The controllable shift register 50 consists of n, for example 8, flip-flop stages (FFS) 54 each of which has the form illustrated in Fig. 4. Each FFS 54 has a clock input C which is connected to the HSC
line 22, two data inputs D and T, a data selection input S, and an output Q which is connected back to the D input of the FFS. All of the inputs S are connected to a selection control line 56 which is constituted by an output of the control circuit 52. The incoming data line 14 is connected to the T input of the first FFS 54, the Q output of the last FFS 54 is connected to the outgoing data line 16, and the Q output of each other FFS 54 is connected to the T input of the respective following FFS 54.
Referring to Fig. 4, each FFS 54 comprises a D flip-flop 58, an AND-OR gate represented by two AND gates 60 and 62 and an OR gate 64, and an inverter 66. The D and T inputs of the FFS 54 are connected to first inputs of the AND gates 60 and 62, whose outputs are coupled via the OR gate 64 to the data input D of the flip-flop 58. A clock input C and an output Q of the fl~p-flop 58 are connected to the input C and output Q, respectively, of the FFS 54. The selection input S is connected directly to a second input of the AND
gate 62, and via the inverter 66 to a second input of the AND gate 60.
Thus when a selection signal on the line 56 is a logic 0, the gates 60 and 62 are respectively enabled and disabled whereby for each FFS 54 the flip-flop 58 has its output Q coupled to its data input D, so that there is no change of the state of the flip-flop 58 when the flip-flop is triggered by pulses of the clock signal HSC present at 1322~32 the C input. Thus in this state of the signal on the line 56, the shift register 50 acts simply to retain the data therein withsut any shifting or changing thereof. Conversely, with a logic 1 state of the selection signal on the line 56, the T input of each FFS 54 is coupled to the data input D of the stage's flip-flop 58, whereby the shift register 50 acts normally as a shift register to shift data serially therethrough from the input line 14 towards the output line 16 with pulses of the high speed clock signal HSC.
The control circuit 52 comprises D flip-flops 70, 72, and 74 each having a data input D, a clock input C connected to the high speed clock signal line 22, and an output Q or -Q, two NAND gates 76 and 78, and a non-inverting driver stage, 80 which couples the Q
output of the flip-flop 74 to the output line 56 of the control circuit. The flip-flop 70 has its D input connected to the low speed clock signal line 24 and its Q output connected to a first input of the gate 76 and to the D input of the flip-flop 72, whose inverting output -Q is connected to a second input of the gate 76. The gate 78 has its inputs connected to the output of the gate 76 and the control signal line 26, and its output connected to the D input of the flip-flop 74.
Fig. 5 illustrates the relative timing of signals which can occur in operation of the circuit of Figs. 3 and 4, it again being assumed that n=8.
As shown by Figs. 3 and 5, the low speed clock signal LSC is effectively sampled by the flip-flop 70 synchronously with the high speed clock signal HSC. The flip-flop 72 and gate 76 result in the synchronous production at the output of the gate 76 of a negative-going pulse, having a duration equal to the period of the signal HSC, for each rising edge ~and hence in each period) of the signal LSC.
The gating of this signal at the output of the gate 76 with the control signal CS by the gate 78, and reclocking of its output by the signal HSC in the flip-flop 74, results in production of the signal on the line 56 in a manner such that this is substantially free of glitches and pulse width variations, whereby data errors are avoided.
Thus in the circuit of Figs. 3 and 4 the clock gapping or multiplexing of the prior art, and consequent glitches and data errors, are avoided. In addition, transitions of the output data on 13%2~3~
the line 16 all occur in response to rising edges of the high speed clock signal HSC, so that this signal HSC can be readily used directly for further processing of the output data.
Although a particular embodiment of the ;nvention has been described in detail, it should be appreciated that numerous modifications, variations, and adaptations may be made thereto within the scope of the invention as defined in the claims.
Claims (7)
1. A serial data handling circuit comprising:
a shift register comprising a plurality of shift register stages for serially shifting data therethrough from an input to an output thereof in response to a first clock signal supplied thereto, the shift register including means responsive to a selection signal for selectively retaining a current state thereof during cycles of the first clock signal;
a control circuit including means for sampling a second clock signal, having a frequency which is substantially the frequency of the first clock signal divided by the number of shift register stages of the shift register, in dependence upon the first clock signal, and means for producing said selection signal in dependence upon the sampled signal and a control signal supplied thereto; and comprising means for producing from the sampled signal a pulse, having a duration equal to the period of the first clock signal, during each period of the second clock signal, and further means responsive to said pulse and to the control signal for producing the selection signal.
a shift register comprising a plurality of shift register stages for serially shifting data therethrough from an input to an output thereof in response to a first clock signal supplied thereto, the shift register including means responsive to a selection signal for selectively retaining a current state thereof during cycles of the first clock signal;
a control circuit including means for sampling a second clock signal, having a frequency which is substantially the frequency of the first clock signal divided by the number of shift register stages of the shift register, in dependence upon the first clock signal, and means for producing said selection signal in dependence upon the sampled signal and a control signal supplied thereto; and comprising means for producing from the sampled signal a pulse, having a duration equal to the period of the first clock signal, during each period of the second clock signal, and further means responsive to said pulse and to the control signal for producing the selection signal.
2. A circuit as claimed in claim 1 wherein the means for sampling the second clock signal comprises a first flip-flop having a data input responsive to the second clock signal, a clock input responsive to the first clock signal, and an output at which the sampled signal is produced.
3. A circuit as claimed in claim 2 wherein the means for producing said pulse comprises a second flip-flop having a data input coupled to an output of the first flip-flop and a clock input responsive to the first clock signal, and gating means coupled to outputs of the first and second flip-flops.
4. A circuit as claimed in claim 3 wherein the further means comprises means for gating an output of said gating means with the control signal and a third flip-flop having a data input responsive to an output of said means for gating, a clock input responsive to the first clock signal, and an output for producing the selection signal.
5. A circuit as claimed in claim 2 wherein the further means comprises gating means responsive to the sampled signal and the control signal, and a flip-flop having a data input responsive to an output of the gating means, a clock input responsive to the first clock signal, and an output for producing the selection signal.
6. A circuit as claimed in claim 1, 2, or 3 wherein each shift register stage comprises a flip-flop having a clock input for receiving the first clock signal, a data input, and a data output, and means for selectively coupling to the data input in dependence upon the selection signal either the data output of the respective shift register stage or the data output from the preceding shift register stage.
7. A circuit as claimed in claim 4 or 5 wherein each shift register stage comprises a flip-flop having a clock input for receiving the first clock signal, a data input, and a data output, and means for selectively coupling to the data input in dependence upon the selection signal either the data output of therespective shift register stage or the data output from the preceding shift register stage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000607922A CA1322032C (en) | 1989-08-09 | 1989-08-09 | Serial data handling circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000607922A CA1322032C (en) | 1989-08-09 | 1989-08-09 | Serial data handling circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1322032C true CA1322032C (en) | 1993-09-07 |
Family
ID=4140436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000607922A Expired - Fee Related CA1322032C (en) | 1989-08-09 | 1989-08-09 | Serial data handling circuit |
Country Status (1)
| Country | Link |
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| CA (1) | CA1322032C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115766332A (en) * | 2023-01-03 | 2023-03-07 | 杭州视芯科技股份有限公司 | Serial communication device, serial communication system, and serial communication method |
-
1989
- 1989-08-09 CA CA000607922A patent/CA1322032C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115766332A (en) * | 2023-01-03 | 2023-03-07 | 杭州视芯科技股份有限公司 | Serial communication device, serial communication system, and serial communication method |
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