JPS59155884A - Signal generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a signal generating device suitable for generating program signals for symmetrical patterns used in printers, graphic displays, and the like.

(Prior Art) Conventionally, in order to generate program signals for patterns, a counter, a digital comparator, and a A signal J-+ generator was constructed by combining various types of gates. this is,
The same was true when generating symmetrical patterns.

However, in this method, when the number of channels becomes large, the complexity becomes enormous, which is not only disadvantageous in terms of cost, but also has the disadvantage that the 1:1 gram transformation becomes cumbersome.

Therefore, it is conceivable to store programs for multiple channels in memory and read them out sequentially over time, but even if the program is to form a symmetrical pattern, Storing data for configuring the entire pattern in memory necessitates an increase in memory capacity.

(Object of the Invention) The present invention has been made in view of the above points, and its object is to generate a symmetrical pattern in which the memory capacity corresponds to half of the symmetrical pattern. To provide a signal generating device which only needs to store data and whose memory capacity can be reduced.

(Example) Hereinafter, an example of the present invention will be explained. FIG. 1 is a block diagram showing one embodiment of the invention, and 1 is a block diagram showing an example of the embodiment.
The oscillator 1 and 2 are up-down counters that count up or down depending on the clock pulses, and the n-bit outputs of the counter 2 are stored in the ROM of the next stage. (Read-only memory) 3 address specification.

This ROM 3, when addressed, outputs m hits in parallel, causing the ROM 3 to operate manually. Based on the clock from the oscillator 1, this latch 4
It works to latch the data from and sequentially output the unlatched data, and one of the data is sent to the T terminal of the r-type flip-flop (hereinafter referred to as FF) 5 as a 1-return signal. Sent. And part 1 Hiso I
- by 1<The remaining hit outputs, that is, m-1 hint outputs, are taken out as pattern data. In other words, R
In the OM3, 1 bit is stored as data for controlling the FF5, and m-1 bits are stored as data for the pattern.

The Q output from the FF" 5 is input to the U/D terminal of the counter 2 as a good number for the up-count or down-count control a1 of the counter 2. 6 is the FF5).h When the power is turned on, the Q output is “1”
This is a switch that cannot be initialized to -1. Note that this can also be configured to be initialized by a time constant circuit.

In the above, when the power is turned on at the time to shown in FIG.
turns on, FI" 5 is initialized, the signal C of its Q output becomes [1-1, and the oscillator 1 starts outputting the clock pulse a. As a result, the U/D terminal of the counter 2 Since the signal C of "1" is input manually from FF5, the amplifier count is started and the FF of ROM3 is inputted manually.
°Start specifying responses in order from address 1.

Here, 1. control FF5 that has been a
1 to determine the amplifier down of counter 2.
The bit signal is 0°1.2.3.4 of ROM3.
As 1 bit of the m-bit fM number at address 5.6,
rOJ, II l-,'rll.

Assuming that rlJ, rlJ', rlJ, and 1-OJ are stored, counter 2 starts counting when the clock rises as shown in Figure 2 (bl), but until then it is "0". , ROM 3 is specified from address 0,
be done. However, although not shown,

In M3, each data is not output to the OE (data output when no clock is input to the output terminal) terminal, and no signal is output ((shown by the broken line).

).

Now, when clock signal a is input to one shot counter 2,
When the chronograph starts up, the output of counter 2 becomes 1, and RO
The address signal to M3 also serves as an input specifying the first address. Therefore, if R O M 3 is specified as the first address, the read clock to the OE&lil child (for example, the clock to the c.k &%11 child of counter 2 is slightly less than
5 1i1 T + delayed by Igo)
As shown in the signal R OM 3 in the figure, the H level signal "1" is output to the latch 4 with a delay of intercostal T+. Here, the access time of ROM3 is excluded.

Counter 2 is also 2 according to the clock signal.

3... and Karan 1~ was uploaded, and the highest address i11+ (
For simplicity, I chose number 6. ), ROM3
Of the m bits stored at address j, the signals 1 to 1 become OJ. This signal is latched by latch 4 along with other rn-1 bit data, At the falling edge of the clock pulse, its latch 4
It is output as a signal b' falling from FF. 5 is man-powered. The Q output signal C of the FF 5 is inverted and becomes "0" by the input of the falling portion (1+ time point) of the signal b'. Therefore, at this time, the counter 2 receives the 10th signal C.
By receiving this at the U/D terminal from time t1 to time t2, it starts counting down from the rising edge of the next clock pulse, and continues counting down toward the address with the smallest number 1ub in ROM3 until it reaches 0. Address sequentially.

Therefore, if data for half of the symmetrical pattern is written in the portion corresponding to m-]bipi of ROM 3, I.no.fu. as shown in 7 sections in FIG.

Latch the signal that displays the entire symmetrical pattern with links, etc. 4
It can be removed without taking it out. The 31st ,!.

During the town count (indicated by DN), one column ()) of the broken line symmetrical to the solid line is read out in the same way.

Figure 3 (bl~(e)) shows another symmetrical pattern in the ROM
FIG. 3 is a diagram showing a case where the data is stored in 3 and read out in prints 1 to 1.

FIG. 4 shows another embodiment of the present invention, which is basically the same as the circuit shown in FIG. 1, and corresponding parts are given the same reference numerals. In this embodiment, ROM 3
' is parallel m-bi as in Figure 1.

Of these, the counter control (fr 'j) for 4 channels is stored in the 4 tenths including the MSB (first 7 digits). Therefore, the remaining r
n-4 hino 1- is used as pattern output data. Among the outputs of the latch 4', the outputs of four channels are switched by the switch 7, and the signal of the selected channel is inputted to the F F 5.

This switch 7 may be a mechanical switch or a switching element such as a Maruno breaker.

FIG. 5 shows an example of a pattern stored in the ROM 3', and FIG. 15 shows various patterns obtained from this pattern.

1? Among the parallel outputs of OM3', output 1-1 is written to the MSB from address 1g to address b11, and output [Oj is written to address b+-+11, and the next digit after MSB is A1: Responses are from address 1 to b
Output "1" is written at address 22, and output [o-1] is written at address b2+1.

Similarly, an output "1" is written to the third and fourth digits following the MSB until the address reaches addresses b33 and b44, respectively, and when the next address advances, an output "0" is written.
-1 is written.

Here, if switch 7 is connected to the launch output side and a clock pulse is applied to make it work, the counter 2 will start the amplifier count series J work until the address reaches address b11, as shown in Figure 2. Next, it stops counting at address b1, then performs a town count operation, accesses address 0, and then starts the end knob count operation again.

As a result, 18 patterns are created that repeat over time, as shown in FIG. 6+81. Similarly, b2 in FIG. Launch output b2 corresponding to address t or b44
．． b...

By selecting b, various continuous patterns can be obtained, including those shown in FIGS.

By storing half of the data of the symmetrical pattern in the ROM as shown in the figure, it is possible to retrieve the data corresponding to the entire symmetrical pattern using that half of the data. Therefore, it can be used for galactorization of symmetrical characters, galactorization of symmetrical pattern formats, or symmetrical graphic pattern or test pattern generation for printers, graphic displays, etc. can.

(Structure of the Invention) As described above, the present invention provides a memory having parallel output,
When the clock input is input to 1-, the amplifier-down type 〒(〒) for addressing the above-mentioned memory according to the count value and the parallel output of the above-mentioned memory are held. According to the clock power, each of the 11 outputs of the latch generates 12 grams of signal from each hint, and 7 of the 10 outputs of the sonar. The up/down of the counter 11 is controlled by the E number of the bit.

(Effects of the Invention) Therefore, when a symmetrical pattern signal is generated, half of the program data of the pattern need only be stored in the memory, so the capacity of the memory can be reduced.

In addition, when generating multiple program signals, conventionally a large number of counters, digital comparators, and gates were required, but in the present invention, only a number of counters, digital comparators, and gates are required.
1, which not only makes the circuit extremely compact, but also requires only changing the contents of the memory.

In addition, since the output of the memory that is addressed by the 1+llj clock and output simultaneously in parallel is used as the program signal, the time relationship or phase relationship between each signal month is extremely accurately expressed as 1F, and multiple counters This eliminates the possibility of unstable operation due to poor synchronization or uneven signal delay times that occur when using gates or gates.

Furthermore, since the various signals are generated after the output of the memory is loaded into the launch, transient malfunctions and noise will not occur when the latch cock changes or when the counter switches. , you can expect solid behavior.

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram of a signal generating device according to an embodiment of the present invention, Fig. 2 is a timing chart for explaining the operation, and Fig. 3 (a) to +e+ show examples of symmetrical patterns to be generated. Explanatory diagram, FIG. 4 is a circuit block diagram of a signal generating device of another embodiment, FIG. 5 is a diagram showing an example of a pattern stored in the ROM of FIG. 4, FIG. It is a figure which shows various patterns obtained by the apparatus of this. j...Starting device, 2...Counter, 3.3'...
ROM, 4.4'...Latch, 5...FF, 6.
7...Switch. Patent applicant: Konishiroku Photo Industry Co., Ltd. Representative patent attorney Tsuneaki Nagao

Claims (1)

[Claims] (1) a memory having parallel outputs, an up/down type counter for counting the clock inputs and addressing the memory by the count 41~, and a latch for holding the parallel outputs of the memory; generates a program grade signal from the output of each bit of the parallel output of the launch in response to the clock input, and -1 by the signal of at least one bit of the output of the launch.
- Ig ordering device characterized by controlling the amplifier down of the counter.