JP2599361B2 - Waveform reading device - Google Patents

Description

Description: TECHNICAL FIELD [0001] The present invention relates to a waveform reading device used for an electronic musical instrument and the like.

[Prior Art] When an electronic musical instrument generates a musical tone similar to a musical tone of a natural musical instrument, adding an envelope and storing all waveforms from the start to the end of the envelope are:
Because of having a very large memory, it has been conventionally used to loop and use short waveform data.

In this conventional method, the capacity of the memory can be reduced, but the read waveform data is always the same even if the envelope elapses, that is, from the attack step to the decay step and from the sustain step to the release step.

[Problems of the Related Art] However, since an actual natural musical instrument does not always output the same waveform in this way, such a conventional method generates a musical tone that is far from the musical tone of the natural musical instrument. There was fear.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide an electronic musical instrument that generates a musical sound similar to that of a natural musical instrument without increasing the memory capacity. It is intended to provide a feasible waveform reading device.

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention divides a storage means for storing a waveform into a plurality of storage areas, specifies an address section corresponding to each storage area, and When adding an envelope by repeatedly reading the waveform,
Each step of this envelope (attack, decay,
The main point is that the switching timing of (sustain, release) is detected, and before the switching timing, the address section designating the storage area is changed to another address section.

Embodiment An embodiment will be described below with reference to the drawings.

 First, a specific circuit configuration will be described with reference to FIG.

In the figure, reference numeral 11 denotes a keyboard, which comprises scale keys and various control keys (tone color selection keys and the like). The output of each key of the keyboard 11 is input to a CPU 12 (central processing unit). That is, the CPU 12 is a control unit, and detects ON / OFF of a key of the keyboard 11 and performs processing corresponding to each key.

The IF 13 is a circuit for smoothly exchanging data between the CPU 12 and other circuits, that is, an interface circuit, and controls a data transmission direction from the various latches to the CPU 12 and vice versa. The operation decoder 14 decodes the command from the CPU 12 and various latch locks CK (ONF latch 15), CK (WK latch 16), CK (RF
Latch 17), CK (RTAD latch 18), CK (STAD latch 1
9), CK (ENDAD latch 20), CK (RWAD latch 21), CK
(WDATA latch 22), CK (fSET latch 23) and gate control signal (RRAM) are output. The CPU 12 sends a command to the operation decoder 14 with the data to be set on the various latches (the data bus DB such as the RTAD latch 18, the STAD latch 19, and the ONF latch 15, etc. being input) on the data bus DB, Output the corresponding latch clock. Thus, any data can be set in any latch to which the data bus DB is input. Also, by outputting the signal RRAM to open the gate G8, the RDATA latch 24
CPU 12 can read this data.

Gates G1 to G9 are 3-state buffers. When the control input C is "1", the input is output as it is,
When "0", the output is turned off (high impedance).

The clock generator 25 is a clock generation circuit,
Two alternate pulses of φ ₁ and φ ₂ are output. CK outputted from the operation decoder 14 are all phi ₂ cycles.

The RAM 35 stores musical sound waveform data. For example, 8
FIG. 2A shows waveform data composed of eight bit data. FIG. 2B shows an output analog waveform obtained by reading the data at every time t. t is the time for determining the pitch. For example, if t is doubled, the sound will be one octave lower, and if t is halved, the sound will be one octave higher.

A circuit that adjusts the time t for determining the pitch is a circuit for generating a scale clock such as the fSET latch 23, the fCNT latch 26, and the increment circuit 27. The ONF latch 15 is a latch which is set to "1" when sound is generated and set to "0" when sound is not generated. When there is no sound, the output of ONF latch 15 is "0"
It is. And its output is inverter I2 and OR gate
In addition to being input as a control signal to gate G2 via R1, it is also input as a control signal to gate G1 via inverter I1. The output of the latch ONF15 is input to the AND gate A2 together with the output of the AND gate A1. And And Gate A2
Outputs addition to input to the AND gates A3, A4 through the inverter I3, directly input to the AND gates A7 together with the clock phi _1. The output of the AND gate A2 is directly input to the control terminal C of the gate G7 and the AND gate A5, and is applied to the increment circuit 28 as a +1 signal.
Input to the control terminal C of the gate G6 via I5.

If a certain scale key of the keyboard 11 is pressed in this state, the CPU 12 sets data corresponding to the scale in the fSET latch 23. In this case, the output of the ONF latch 15 becomes "0", and therefore, the output of the inverter I2 is "1", and therefore, the output of the OR gate R1 is "1". Therefore, the gate G2 is turned on and the gate G1 is turned off. The data is loaded.

For example, if the data of the fSET latch 23 is 80 (H) (H indicates a hexadecimal code), the output of the fCNT latch 26 is also 80 (H), and the output of the AND gate A1 is "0". Here, when the ONF latch 15 is set to “1”, the output of the OR gate R1 becomes “0”, the gate G2 is turned off, and the gate G2 is turned off.
G1 turns on. The increment circuits 27 and 28 are circuits that output the input +1 when the +1 input is 1. In the increment circuit 27, since the +1 input is always set to 1, it is always incremented by 1. ONF next φ ₁ the latch 15 becomes 1 in 81
(H) is read into fCNT latch 26 is output at the next phi _2. In the next φ ₁ 82 (H) is read and output in the following phi _2. Thereafter, this is repeated until the FF (H) is output. When FF (H) is output, the output of the AND gate A1 becomes "1", the gate G1 turns off and the gate G2 turns on, and a timer which outputs a single "1" signal again during the period from 80 (H) to FF (H). Output. The above-mentioned fCNT latch 26, and 2FF (1) latches 29 and 2FF to which the respective outputs of AND gates A3 and A4 are respectively input
(2) A two-phase flip-flop such as the latch 30 having two clock terminals CK1 and CK2 is read by CK1 and output by CK2. The 2FF (1) latch 29, 2FF
(2) Each output of the latch 30 is input to each reset input terminal R of the WF latch 16 or the RF latch 17.

The analog waveform of the output of the D / A converter 31 is such that when the ONF latch 15 is “0”, the inverter I2 output is “1” and the SOUT latch
The R input of 32 becomes “1” and the SOUT latch 32 output becomes “00 ...
… 0 ”(SOUT latch 32, WF latch 16, RF latch
R such as 17 indicates a reset input), and since the MSB input of the D / A converter 31 passes through the inverter I6, the output of the D / A converter 31 in this case has half the potential of the maximum output. And gate
A4 outputs are input to the AND gate A6 together with the clock phi _1, and each output of the AND gate A6, A7 also becomes the clock for the RDATA latch 24, SOUT latch 32. Also this SOUT
The reset signal of the latch 32 is the output of the inverter I2.

It also has a first address (start address) from which the waveform is read, a last address (end address) from which the subsequent addresses are not read, and a return address (return address) at which reading is started before the last address. Are set in the STAD latch 19, the ENDAD latch 20, and the RTAD latch 18, respectively, in that order. When the address is incremented by 1 from the start address data and read to the end address, it returns to the return address and goes to the end address again in the address order. Thereafter, this operation is repeated until the ONF latch 15 becomes "0".

When the ONF latch 15 is "0", the output of the inverter I2 becomes "1", the output of the inverter I2 and the output of the AND gate A5 are input via the inverter I4, and the NOR gate NR1 output and the NOR gate NR2 output become "0". So gate G4
ON, gates G3 and G5 off. During this time, the start address data from the STAD latch 19 is loaded into the SAD latch 33 composed of a two-phase flip-flop via the gate G4. At this time, the fSET latch is
Data from 23 has been loaded.

The matching circuit 34 is a circuit that outputs "1" when the end address data from the ENDAD latch 20 matches the start address data or the return address data from the SAD latch 33. Since the end address data do not match, the output is "0". The output of the matching circuit 34 is an AND gate.
Enter in A5.

Here, when the output of the ONF latch 15 is set to “1”, the gate G4 is turned off by the output of the inverter I2 being “0”, the output of the matching circuit 34 is set to “0”, and the output of the AND gate A5 is set to “0”. As a result, the gate G5 is turned on, the output of the inverter I4 becomes "1", and the gate G3 is turned off. As a result, the output of the SAD latch 33 returns through the increment circuit 28.

Immediately after the ONF latch 15 becomes “1”, the fCNT latch 26
Has just started incrementing, the output of the AND gate A1 is "0", the output of the AND gate A2 also becomes "0", and the "0" signal is given to the +1 input terminal of the increment circuit 28. The data in the SAD latch 33 is not incremented. The R input of the SOUT latch 32 becomes “0” at the same time when the output of the ONF latch 15 becomes “1”.
However, since the output of the AND gate A2 is "0" and the output of the AND gate A7 is "0" and the "1" signal is not supplied to the CK terminal of the SOUT latch 32, the output of the D / A converter 31 is output. Remains at half the potential of the maximum output. The D / A converter 31 is connected with an amplifier 36 and a speaker 37 in series.

When the data of the fCNT latch 26 becomes "11 ... 1",
The output of the AND gate A1 becomes "1", the output of the AND gate A2 becomes "1", and the "1" signal is given to the +1 input terminal of the increment circuit 28. At the same time, the gate G7 turns on and the data in the SAD latch 33 is transferred to the address input terminal of the RAM 35.
Sent to AD. Further, since the output of the AND gate A2 is “1”, the output of the inverter I3 becomes “0”,
The output of AND gate A3 becomes "0" and
▼ Terminal input becomes “0”. Therefore, SAD address data of RAM35 (that is, start address data at this time)
Is output from the I / O terminal of the RAM 35. The control signal for outputting data from the I / O when the terminal is "0" is input to the terminal. Here, the clock pulse signal phi ₁ to the AND gate A7 output by AND gate A2 output is "1" to read the data of one manifestation RAM35 to SOUT latch 32. This is converted into an analog signal by the D / A converter 31 and output through the speaker 37 via the amplifier 36.

On the other hand, the data +1 through increment circuit 28 is read into the SAD latch 33 upon application of a clock pulse signal phi _1. Thereafter, the data of the fCNT latch 26 is changed to "11 ...
Each time it becomes "1" (that is, every time t elapses), the data of the SAD latch 33 is input to the address input terminal AD of the RAM 35 through the gate G7, and the "0" signal is supplied to the ▲ ▼ terminal, whereby the address of the RAM 35 is given. Data is output to I / O and a pulse is input to the CK terminal of SOUT latch 32,
The data is latched in the SOUT latch 32 and the D / A converter 3
1, output through the amplifier 36 and the speaker 37. The MSB (most significant bit) of the data is transmitted via the inverter I7 to the S
Latched by OUT latch 32. Then, the data from the SAD latch 33 is incremented by one each time this series of operations is performed, and eventually the data in the SAD latch 33 becomes equal to the end address data. When the above-described series of operations is performed in this state, the output of the matching circuit 34 becomes "1" and the output of the AND gate A2 becomes "1", so that the output of the AND gate A5 is "1" and the output of the NOR gate NR2 is "1". "0", the gate G5 is turned off, the output of the inverter I4 becomes "0", the output of the NOR gate NR1 becomes "1", and the gate G3 is turned on. As a result, when the end address data is next latched by the SOUT latch 32, the return address data is read by the SAD latch 33, and the address of the RAM 35 is returned. Thereafter, the address data between the return address and the end address is repeatedly output until "0" is set in the ONF latch 15.

Next, a circuit in which the CPU 12 writes data in the RAM 35 will be described with reference to a time chart of FIG.

First, turn on the tone switch and specify the desired tone.
Address “0” to be written to RWAD latch 21, WDATA latch 2
Set the data "11000000" to be written in 2. Thereafter, when "1" is set to the WF latch 16, the output of the AND gate A3 becomes "1" in the cycle immediately after the setting. Data WDATA latch 22 by the time gate G9 is turned on RAM 35 for ▲ ▼ pin input is "1" is input to the I / O, low level active pulse phi ₁ cycle by the NAND gate NA1 is RAM 35 ▲ ▼ Input to the terminal. At this time, since the gate G7 is off and the gate G6 is on, the data of the address "0" indicated by the RWAD latch 21 is written. The write cycle of the CPU 12 to the RAM 35 is only one cycle by the 2FF (1) latch 29. Next, at address 1 of the RAM 35, the data "1110000"
"0" is written, and thereafter data is written up to address 39, and the waveform shown in FIG.

Next, the operation when the CPU 12 reads data other than the musical tone waveform data in the RAM 35 will be described in the case where the ONF latch 15 is "0", that is, no sound is generated.

When "1" is set to the RF latch 17 and "0" is set to the WF latch 16, the output of the OR gate R1 becomes "1" because the output of the ONF latch 15 is "0", and the gate G2 is turned on, so that the fCNT latch
26 contains the pitch data of the fSET latch 23, the output of the AND gate A1 is "0", the output of the AND gate A2 is also "0", the output of the inverter I3 is "1", and the output of the AND gate A4 is "1" because the clock pulse signal phi ₁ from the aND gate A6 is output, the data is taken into the register RDATA24. At this time, AND gate A2 is "0"
Therefore, the gate G7 is turned off, the gate G6 is turned on, the data from the RWAD21 is given to the address input terminal AD of the RAM 35, and the AND gate A3 is output by the "0" output of the WF latch 16.
Is "0", the ▲ ▼ input is "0", and the address data of the RWAD latch 21 is output.
Therefore, the address to be read from the RAM 35 is set in advance in the RWAD latch 21 and "0" is set in the WF latch 16 and the RF latch 17 is set.
To “1”, the data in RAM 35 is stored in RDATA latch 24
Can be read. Thereafter, the CPU 12 causes the operation decoder 14 to output the signal RRAM of “1”, and turns on the gate G8 to read the data of the RDATA latch 24 through the data bus DB. RF is set to the latch 17 "1" is reset by output in the RDATA latch 2FF (2) at the same clock pulse signal phi ₁ and read clocks to 24 is loaded into latch 30 the next clock pulse signal phi ₂ , Prevents the RDATA latch 24 from outputting more than one read clock.

On the other hand, if ONF latch 15 is "1" or in pronunciation (referred to as a cycle from this clock pulse signal phi ₂ to the next phi ₂₎ the operating cycle of SOUT latch 32 reads the data of the waveform This is performed in a cycle other than. That is, the AND gate A1 becomes "1" only in the waveform data read cycle, and otherwise is "0". Therefore, the above operation is performed when the output of the AND gate A1 becomes "0".

Next, with reference to the time charts of FIGS. 4 and 5 and the waveform chart of FIG. 6, the values of the ENDAD latch 20 and the RTAD latch 18 are rewritten with time, and these two latches 20 and
An operation in which waveform data is repeatedly and repeatedly read between addresses in the RAM 35 designated by 18 will be described.

When the tone select key of the keyboard 11 is pressed, the CPU 12 sets the ONF latch 15 to "0", and writes some waveforms characterizing the tone in the RAM 35. In this case, if there is no sound, the ONF latch is still "0". Here, a waveform as shown in FIG. 6A is written in the RAM 35. Here, addresses “0” to “7” are the first waveform, addresses “8” to “15” are the second waveform, addresses “16” to “23” are the third waveform, and “24”.
Addresses "31" to "31" are assigned a fourth waveform, and addresses "32" to "39" are assigned a fifth waveform. The first waveform and the second waveform are used at the time of attack, the third waveform is used at the time of decay, the fourth waveform is used at the time of sustain, and the fifth waveform is used at the time of release.

When the scale key is pressed, as shown in FIG.
Set the TAD latch 19 to “0”, the RTAD latch 18 to “8”, and the ENDAD latch 20 to “15” and set the data corresponding to the pitch to fSET
Set to latch 23 and set ONF latch 15 to "1". Then, the waveform data starts to be read from the address 0 of the RAM 35 every time t. Since the ENDAD latch 20 is "15", the data at the address 8 is read after the address 15, and the data at the addresses 8 to 15 are repeatedly output. The number of repetitions is controlled by the CPU 12. That is, the first waveform is output only during the attack, and then the second waveform is repeated.

Before switching from attack to decay, CPU12
Sets ENDAD latch 20 to "23" and then immediately sets RTAD
"16" is set in the latch 18. At this time, the SOUT latch 32
If it is after reading the data at address 14 of RAM 35 (point (a) in FIG. 6 (a)), then it does not return from address 15 to address 8 but goes to address 23 and returns to address 16, and the third waveform Is repeatedly output. Next, before switching from decay to sustain, set "31" in the ENDAD latch 20 at the same time as above, and then set the RTAD latch 18 to "24". The third waveform smoothly changes from the third waveform to the fourth waveform, and the fourth waveform It becomes a repetition. Before switching from sustain to release, set ENDAD latch 20 to "39", then set RTAD latch 1
When 8 is set to “32”, the fourth waveform is smoothly connected to the fifth waveform, and the fifth waveform is repeated.

When switching waveforms smoothly in this way, the CPU 12
Need not worry about the timing. Point A is second
After resetting the ENDAD latch 20 anywhere in the waveform, the RTAD latch 18 may be changed immediately. That is, it may be changed within the time for reading one waveform value. This is simple because the processing speed of the CPU 12 is sufficiently faster than the time required to output one waveform.

The example in which the waveforms are arranged in address order has been described above. However, even if the data of each waveform is far away, if the RTAD is changed and then the ENDAD is changed, any waveform can be connected.

In the above embodiment, an example using the RAM 35 has been described.
Instead, a ROM in which data has already been written may be used.

In this embodiment, a circuit for multiplying a waveform by an envelope is omitted for simplicity. To realize the envelope multiplication, an envelope latch for taking in data from the data bus DB is provided, a clock for taking in the data is output to the operation decoder 14, and the output of the envelope latch and the output of the SOUT latch 32 are input to the multiplier. The multiplication output may be input to the D / A converter 31. In this embodiment, a monophonic circuit is used for simplicity, but a polyphonic circuit may be used by using a time-division circuit or the like.

[Effects of the Invention] As described in detail above, the present invention divides a storage unit for storing a waveform into a plurality of storage areas, specifies an address section corresponding to each storage area, and stores the waveform in the storage area. Is repeatedly read to add an envelope, the switching timing of each step (attack, decay, sustain, release) of this envelope is detected, and before the switching timing, an address section for specifying a storage area is set to another address section. Since the address section is changed to the address section, there is an advantage that it is possible to realize an electronic musical instrument capable of generating a musical tone similar to that of a natural musical instrument without increasing the memory capacity as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a specific circuit diagram of the present invention, and FIG.
5 shows an example of musical tone waveform data to be written in FIG. 5, FIG. 2 (b) shows a musical tone waveform of the data in FIG. 2 (a), and FIG. 3 shows a time chart when waveform data is written in the RAM 35. FIG. 4, FIG. 4 is a diagram showing a time chart of the operation of reading waveform data from the RAM 35, FIG. 5 is a diagram showing a time chart of the operation when the repetition section is switched, and FIG. 6 is a waveform diagram of the repetition operation. And FIG. 11 ... keyboard, 12 ... CPU, 14 ... operation decoder, 18 ... RTAD latch, 19 ... STAD latch, 20 ...
... ENDAD latch, 21 ... RWAD latch, 22 ... WDATA latch, 23 ... fSED latch, 24 ... RDATA latch, 26 ... fCN
T latch, 27, 28 increment circuit, 33 SAD latch, 34 matching circuit, 35 RAM, 36 amplifier, 37
... Speaker.

Claims (1)

(57) [Claims] A storage means for storing a waveform; a storage means for dividing the storage means into a plurality of storage areas; and an address section for designating an address section corresponding to each storage area; Reading means for repeatedly accessing a corresponding storage area of the storage means to read a waveform; envelope adding means for adding an envelope comprising a plurality of steps to the waveform read by the reading means; and each of the envelopes A switching detecting means for detecting a switching timing of a step; and each time the switching timing of each step of the envelope is detected by the switching detecting means, the address section specified by the specifying means is changed to another address section. Control means for controlling the designation means so as to change it. The read-out device.