JPH0617195Y2 - Musical sound generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a musical tone generating apparatus capable of starting to generate a plurality of musical tones almost simultaneously.

[Conventional technology]

2. Description of the Related Art Conventionally, there is known a musical tone generating device which reads a waveform from a waveform memory and generates a musical tone.

FIG. 4 is a block diagram of such a conventional musical tone generating apparatus. This tone generator is composed of 8 time divisions of channels 0 to 7 by time division processing. In the figure, the musical sound generating device is composed of a shift register having eight stages, and a current address register 1, a pitch data register 2, a flag register 3 and each register 1 to which a current address, pitch data and flag data are assigned respectively. It has an instruction interpretation execution unit 4 for writing data to designated time-division channels 2, 3, and a central control unit (CPU) 5 for controlling the instruction interpretation execution unit 4 and providing write data. As will be described in detail later, the instruction interpretation execution section 4 includes start address, data WB such as pitch data, selection signals WCA, WPT, and set / set.
The clear signal FSET / FCLR is output.

The pitch data WB and the output of the pitch data register 2 are input to the selector 6, selected by the selection signal WPT, and input to the pitch data register 2 again. The set signal FSET and the output of the flag register 3 are NOR gates 7.
The clear signal FCLR and the output of the NOR gate 7 are input to the NOR gate 8, and the output of the NOR gate 8 is input to the flag register 3 again. The outputs of the pitch data register 2 and the flag register 3 are input to the AND gate 9, and the output of the AND gate 9 and the output of the current address register 1 are added by the adder 10. The start address data WB and the output of the adder 10 are input to the selector 11, selected by the selection signal WCA, and input to the current address register 1. The output of the current address register 1 is given to the waveform memory 12 as read address data, the waveform is read, and the read waveform is converted from a digital signal to an analog signal by the D / A converter 13. It is output as a musical sound from the speaker 14.

FIG. 5 is a block diagram showing the details of the instruction interpretation execution unit 4 of FIG. In the figure, the data given from the CPU 5 is sent through the data bus to the data latch register 15 and the channel latch register 1 at the timing described later.
6 and the command latch register 17. The signals AB0 and AB1 given from the CPU 5 are inputted to the decoder 18, and the chip select signal CS and the write signal WR given from the CPU 5 are also inputted to the OR gate 19. The output of the OR gate 19 is the control terminal of the decoder 18. To enter. First to the first decoder 18
The third outputs are the data latch register 15, the channel latch register 16, and the command latch register 1, respectively.
7 and the third output is given to the execution cycle signal generator 20. The data latch register 15 has a start address given from the CPU 5,
Data WB such as pitch data is stored and output to the above-mentioned selectors 6 and 11 at a predetermined timing. The channel latch register 16 stores the data given from the CPU 5, and outputs the 3-bit signals PC0, PC1 and PC2 to the one input terminals of the exclusive NOR gates 21, 22 and 23, respectively. The other input terminals of these exclusive NOR gates 21, 22, and 23 have timing signals CH0, CH1, and
CH2 enters. The execution cycle signal generating section 20 is a section for generating a high active execution cycle signal for time division channels 0 to 7 (this is called a cycle). And these exclusive NOR gates 21,
The outputs of 22 and 23 and the output of the execution cycle signal generator 20 are input to a 4-input NAND gate 24. The command latch register 17 also stores command data given from the CPU 5 and outputs a 2-bit output signal to the command decoder 25. This command decoder 25
The output of the NAND gate 24 is applied to the control terminal of the. The command decoder 25 uses the selection signal WCA,
It outputs WPT and set / clear signals FSET / FCLR.

The operation of the above-mentioned conventional musical tone generating apparatus will be described.

First, in the instruction interpretation execution unit 4, data provided from the CPU 5 is transferred to each of the registers 15 and 1 based on a predetermined control signal.
6 and 17 are written. That is, first, data to be written from the CPU 5 is prepared in the data bus, and AB1 =
0, AB0 = 0, CS = 0, low active WR
When the signal is input to the OR gate 19, a clock signal is given from the first output of the decoder 18 to the data latch register 15, the data on the data bus is stored in the data latch register 15, and WB is determined. Next, similarly, data is prepared on the data bus, and AB1 = 0, AB
By setting 0 = 1 and CS = 0 and performing the same operation,
A clock signal is applied to the channel latch register 16 from the second output of the decoder 18, data is stored in the channel latch register 16, and a 3-bit signal PC
0, PC1, and PC2 are determined. Next, similarly prepare command data on the data bus, and AB1 = 1 and AB0 =
By setting 0 and CS = 0 and performing the same operation, the third output of the decoder 18 is changed to the command latch register 17
When a clock signal is applied to the command latch register 17 and a command is written in the command latch register 17, a 2-bit signal is output to the command decoder 25. Then, the execution cycle signal generator 20 generates a high active "1" execution cycle signal for the cycles of the time division channels 0 to 7. In the exclusive NOR gates 21 to 23, the signal PC0 from the channel latch register 16 is output.
To PC2 and timing signals CH0 to CH2 are given, and when the outputs of the exclusive NOR gates 21 to 23 and the execution cycle signal generator 20 all become "1", the output of the NAND gate 24 becomes "0". The specified command is output from the command decoder 25.

Next, an operation when the execution channel 2 is designated will be described with reference to the timing chart of FIG. As shown in the figure, the timing signals CH2, CH1, and CH0 are signals that repeat inversion every four channels, every two channels, and every channel. Here, when PC2 = 0, PC1 = 1 and PC0 = 1 are output from the channel latch register 16 by the data given from the CPU 5, the exclusive NOR gate 21 outputs C
A signal obtained by inverting H0 is output, the same signal as CH1 is output from the exclusive NOR gate 22, and a signal obtained by inverting CH2 is output from the exclusive NOR gate 23. In addition, the execution cycle signal generator 20 outputs a signal that becomes “1” during the cycle. In the NAND gate 24, the exclusive NOR gates 21 to 2
3 and "0" are output to the command decoder 25 only in the time-division channel 2 in which all signals from the 3 and execution cycle signal generator 20 are "1". Therefore, by the combination of the values of 3 bits PC2 to PC0 given from the command decoder 25 at the timing of this time division channel 2,
It is possible to specify one of the execution channels of any 8 time divisions.

Next, the operation of instruction execution will be described. First, the CPU 4 writes the WB data to the instruction interpretation execution unit 4 by the above operation. The WB data is fixed unless the CPU 5 writes the next data in the instruction interpretation execution unit 4.
Next, the CPU 5 specifies to which time division channel of which register the data is to be written. For example, the operation of writing data to the time division channel 2 of the current address register 1 will be described with reference to the timing chart of FIG. As shown in the figure, the instruction interpretation execution unit 4
The output of WB is fixed, and WCA is time division channel 2
It becomes "1" only when, and WPT, FCLR, FSE
T becomes "0". Usually WCA, WPT, FCLR,
Since all the FSETs are "0", the output of the current address register 1 is added to the data of the output of the AND gate 9 by the adder 10 and passed through the selector 11 (WCA
(A input of the selector 11 is selected when = 0) is written again in the current address register 1. On the other hand, when the WCA becomes "1", the B input of the selector 11 is selected, and the WB data prepared in advance is written in the current address register 1. That is, the seventh
As shown in the figure, when the time division channel 2 is selected, WB is written in the time division channel 2.

Similarly, predetermined pitch data can be written in the time division channels of the pitch data register 2.

It is sufficient for the flag register 3 to be able to set or clear the flag.
Writing is performed by giving the SET and FCLR signals. That is, for example, the output of the instruction interpretation execution unit 4 is F
When CLR = 0 and FSET = 1, the output of NOR gate 7 is "0", the output of NOR gate 8 is "1", and the flag is set. When the output of the instruction interpretation execution unit 4 is FCLR = 1 and FSET = 0, the NOR gate 7
The output of NOR gate 8 becomes "0" regardless of the output of the flag and the flag is cleared. Normally, the output of the instruction interpretation execution unit 4 is FCLR = 0 and FSET = 0, so that the output of the flag register 3 is rotated twice by the NOR gates 7 and 8 and written to the flag register 3 again. The contents of 3 are saved.

As described above, after the data WB given from the CPU 5 is determined, the write signal or the set signal or the clear signal corresponding to the desired register is set to “1” in the desired time division channel to write the data and set the flag. Can be set / cleared. After writing the data in this way, the pitch data is given to the designated time division channel through the AND gate 9 and is given to the adder 10, and the adder 10 adds the pitch data to the output of the current address register 1. , Is again written from the selector 11 to the current address register 1. Therefore, from the current address register 1, the address data obtained by accumulating the pitch data from the start address is output to the waveform memory 12, the waveform is read, and the musical sound is output from the speaker 13 through the D / A converter 13. It

[Problems that the device tries to solve]

However, in the conventional tone generating device as described above,
When it is attempted to start the sound generation of the waveforms assigned to a plurality of time division channels at the same time, the CPU 5 sequentially outputs the instructions for the plurality of time division channels to the instruction interpretation execution unit 4. Therefore, there is a problem in that there is a time difference in the start of the operation for sound generation between a plurality of time division channels, and as a result, there is a deviation in the sound generation start time between a plurality of waveforms that are desired to start sound generation at the same time. .

Further, when the same data is to be written in different time division channels of the same register, the CPU 5 must send instructions to the instruction interpretation execution unit 4 by the number of time division channels to be written, which imposes a burden on the CPU 5. There was a growing problem.

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to start sound generation of a plurality of waveforms assigned to a plurality of time-division channels almost at the same time and to reduce the load on the CPU in the tone generator. .

[Means for solving problems]

The means of the present invention is a musical tone generating apparatus for generating a plurality of musical tones by using time division processing, wherein the musical tone generating apparatus writes to, for example, each register for a plurality of time division channels during one cycle of the time division processing. It has an instruction interpretation execution means for setting an execution instruction signal such as a signal or a set / clear signal.

[Action]

The operation of the means of the present invention is as follows. The instruction interpreting / executing means of the musical tone generating apparatus sets a write signal, a set / set signal for a plurality of time division channels during one cycle of the time division processing.
Set an execution command signal such as a clear signal.

Therefore, the sound generation of a plurality of waveforms assigned to a plurality of time divisions can be started almost simultaneously and the load on the CPU is reduced.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an instruction interpreting / executing unit of a musical sound generating apparatus according to an embodiment of the present invention. The parts corresponding to those of the conventional example are designated by the same reference numerals, and detailed description thereof will be omitted. In the figure, the channel latch register 31 is the CPU 5
Stores the data given from the 3-bit signal PC0,
In addition to PC1 and PC2, 3-bit signals CM0 and CM
A total 6-bit signal of 1 and CM2 is output. The 3-bit signal of the channel latch register 31 is the exclusive NOR gates 21 and 22, respectively, as in the conventional example.
23 to one of the input terminals. The other input terminal of each of the exclusive NOR gates 21, 22, and 23 has a timing signal C indicating a time division channel.
H0, CH1, and CH2 are input. Other 3-bit signals CM0, CM1, CM of the channel latch register 31
2 is input to one input terminal of each of the OR gates 32, 33, 34, and the outputs of the exclusive NOR gates 21, 22, 23 are input to the other input terminals, respectively. The outputs of the OR gates 32, 33, 34 and the output of the execution cycle signal generator 20 are input to the 4-input NAND gate 24. Other configurations are similar to those of the conventional example.

The operation of the musical sound generating device having the above configuration will be described. First, the 3-bit signals PC2, PC1 and PC0 of the channel latch register 31 of the instruction interpretation execution unit 4 designate the execution channel by a binary number as in the conventional case. Channel latch register 3
Since the other 3-bit signals CM2, CM1, and CM0 of 1 are input to the OR gates 34, 33, and 32, the input of the NAND gate 24 is connected to the exclusive NOR gates 21 and 2.
It has a function to forcibly set to "1" regardless of the outputs of 2 and 23. When CM1 = 0, CM0 = 0, and CM2 = 0, PC2 = CH2, PC1 = CH1, P
C0 = CH0 and the execution cycle signal generator 20
The output of the NAND gate 24 becomes "0" when the signal from "1" becomes "1", and one of the time division channels can be designated.

Here, if CM0 = 1, the input of the OR gate 32 becomes “1”, and therefore PC0 = CH0 is excluded from the condition that the output of the NAND gate 24 becomes “0”. Therefore, if CM0 = 1 and PC2 = 0 and PC1 = 1, the execution channels are binary numbers “010” and “01” in the cycle in which the execution cycle signal is “1”.
1 ”, that is, the output of the NAND gate 24 becomes“ 0 ”in the time division channels 2 and 3. Even when CM2 or CM1 is set to "1", the same execution form is obtained.

2 and 3 show an example of the execution mode.

In FIG. 2, the commands are WCA, CM2 = 1, CM1 =
1 shows a timing chart when CM0 = 1. In this case, the values of PC2, PC1, and PC0 are irrelevant. That is, the WCA signal becomes a time division value 0 to 7, that is, “1” over one cycle, and the data prepared in WB is written in the time division channels 0 to 7 of the current address register 1. Therefore, in such a case, in the conventional example, the CPU 5 had to send an instruction eight times, but here, only one instruction is required, and the time until the end of execution is one cycle, which is extremely short. Become.

In FIG. 3, the commands are FSET, CM2 = 0, CM1 =
A timing chart in the case of 1, CM0 = 1 and PC2 = 0 is shown. In this case, PC1 and PC0 are irrelevant, and the execution channel of the FSET signal is "00" in binary.
"0", "001", "010", "011", that is, "1" over the time division channels 0 to 3, and the flags of the time division channels 0 to 3 of the flag register 3 are set. Therefore, in such a case, as with the execution form of FIG. 2, the setting is completed by one instruction, and the time until the end of execution is shortened, and the flag is set within the same cycle. Therefore, there is an effect that the timing of starting the generation of the musical sound does not shift.

As described above, by setting CM2 to CM1 and PC2 to PC0, it is possible to specify a plurality of time division channels and write data in each register.

In the above embodiment, the output of the channel latch register 31 is set to 6 bits, but if it is set to 8 bits and each bit is assigned to the time division channels 0 to 7, the execution channel with a higher degree of freedom can be designated. You can

Further, in the above-described embodiment, the operation is performed by 8 time division, but the present invention is not limited to 8 time division, and the same operation can be performed when the time division is smaller or larger than this.

[Effect of device]

As described above, according to the present invention, since the commands for a plurality of time division channels can be executed substantially at the same time, it is possible to start the sound generation of a plurality of waveforms assigned to a plurality of time division channels almost at the same time. It is possible to reduce the load on the CPU and shorten the instruction execution time.

[Brief description of drawings]

FIG. 1 is a block diagram of an instruction interpretation execution unit of a musical tone generating apparatus according to an embodiment of the present invention, FIG. 2 is a timing chart showing an example of an execution form of the present invention, and FIG. 3 is an execution form of the present invention. A timing chart showing an example, FIG. 4 is a block diagram of a musical tone generating apparatus of a conventional example, FIG. 5 is a block diagram of an instruction interpretation executing section of FIG. 4, and FIG. FIG. 7 is a timing chart shown, and FIG. 7 is a timing chart showing an example of a conventional execution mode. 1 ... Current address register, 2 ... Pitch data register, 3 ... Flag register, 4 ... Instruction interpretation execution unit, 5 ... Central control unit (CPU), 6,11 ... Selector, 7,8 ... NOR gate, 9 ... AND gate, 10 ... Adder, 12 ... Waveform memory, 13 ... D / A converter, 14 ... Speaker, 15 ... Data latch register, 17 ... Command latch register, 18 ... ... decoder, 19 ... OR gate, 20 ... execution cycle signal generator, 21,22,23 ... exclusive NOR gate, 24 ... NOR gate, 25 ... command decoder, 31 ... channel latch register.

Claims (2)

[Scope of utility model registration request] 1. A musical tone generating apparatus for generating a plurality of musical tones by using time division processing, wherein a control means for outputting a control signal for controlling a mode of the musical tone, and a control signal from the control means are inputted. Time division processing 1
And a command interpreting and executing means for setting an execution command for a plurality of time division channels during a cycle. 2. The practical means characterized in that the control means outputs one kind of control signal to the instruction interpretation execution means during one cycle of the time division processing, and the same data is set in a plurality of channels. The musical sound generating device according to claim 1 of the new model registration claim.