JPS6230240Y2 - - Google Patents

Description

[Detailed explanation of the idea]

This invention relates to a memory reading device, and more specifically to a memory reading device that serially outputs data consisting of a plurality of bits stored at each address of a memory, bit by bit. Conventionally, when reading out a large amount of data stored in memory serially one bit at a time, the contents of one word of data consisting of multiple bits stored at one address are read out at once, and this is input in parallel or serially. A method was used in which the bits were registered in an output type shift register and the contents of each bit constituting one word were serially transferred from this shift register. However, with this method, if a blank bit (meaning a bit with no data) exists in the data stored at each address, even this blank bit is registered in the shift register and transferred serially. That will happen.
Therefore, the conventional memory reading device has the disadvantage that it takes a long time to output data stored in the memory. Furthermore, the apparatus for receiving serially output data also has the disadvantage that its capacity must be made larger than necessary due to the presence of the blank bits. This invention provides a completely new memory reading device that serially outputs data consisting of multiple bits stored at each address in memory one bit at a time very quickly and without increasing the capacity of the device receiving the data. The purpose is to do. According to this invention, a first memory that stores various data consisting of a plurality of bits, a selector that selects and outputs one bit of the plurality of bits of data read from the first memory, and a In order to sequentially instruct each bit of various data stored in the memory of the first memory in a predetermined order, bit support data consisting of a read address signal for the first memory and a selection command signal for the selector is sequentially applied to each address. It consists of a second memory that stores data, and a read address signal that generates a read address signal for reading out the second memory. According to the memory reading device having the above configuration, multiple bits of data stored at a specified address in the first memory are read out by the read address signal for the first memory outputted from the second memory. It will be done. Furthermore, the above selector
In response to a selection command signal for a selector output simultaneously with a read address signal for the first memory from the memory, one bit of the plurality of bits of data read from the first memory is selectively output. Therefore, according to this invention, various data consisting of a plurality of bits stored in the first memory are serially read out one bit at a time. Since information regarding the blank bits of each data in the first memory is input in advance to the second memory, if there is a blank bit in the data input from the first memory, this information is used. This is why the selector does not output this blank bit. This invention will be explained in more detail below with reference to embodiments shown in the accompanying drawings. In this embodiment, the memory reading device of this invention is applied to a parameter signal input device of an electronic musical instrument, but this invention is not limited to this, and the contents stored in the memory are serially read out one bit at a time. It can be similarly applied to other devices that require it. FIG. 1 is a block diagram showing an outline of an electronic musical instrument equipped with a parameter signal input device 4 in which this invention is implemented. In FIG. 1, a keyboard circuit 1 is provided with key switches corresponding to each key provided on the keyboard section of an electronic musical instrument, so that only the key switch corresponding to the key pressed on the keyboard section is turned on. It is composed of The key assigner 2 is one of a plurality of channels that can sequentially detect the ON or OFF operations of the key switches in the keyboard circuit 1, and can simultaneously generate a signal (hereinafter referred to as key code KC) that identifies each pressed key based on the detection result. The key codes KC assigned and stored in each channel are sequentially output in a time-division manner in synchronization with the assigned channel time.
This time-division output key code KC is input to the tone generator 5. On the other hand, the parameter selection switch 3 provided on the panel board of the electronic musical instrument outputs various parameter signals PS necessary for generating musical tones depending on its setting state.
is output to the parameter signal input device 4. This parameter signal input device will be explained in detail later, but to briefly explain its function, various parameter signals PS output from the parameter selection switch 3 according to its setting state are input to a memory that can be written to and read out (for example, a random access memory). This is stored in the tone generator 5 (memory), read out bit by bit as serial data SD, and output to the register 51 in the tone generator 5.
When all the data SD is output, the parameter signal input device 4 outputs the final address signal FA, which means that all the contents of the memory have been read out.
This final address signal FA is input to the register 51 of the tone generator 5. This register 51 sequentially registers data SD that is serially output one bit at a time, and further registers the registered data SD in response to the final address signal FA as various parameter signals PS output from the parameter selection switch 3 inside the tone generator 5. It has a function to output to. The tone generator 5 receives the key code KC and the register 51 which are time-divisionally output from the key assigner 2.
This key code KC and various parameter signals PS are output from
Based on this, a musical sound waveform MW corresponding to the pressed key is formed and output. The musical sound waveform MW is input to a sound system 6 consisting of an amplifier, a speaker, etc., and is produced as a musical tone. Next, details of the parameter selection switch 3, parameter signal input device 4, and register 51 in the tone generator 5 will be explained. As shown in Figure 2, the parameter selection switch 3
For example, the switches S1 to S20 and the encoders 301 to 301 respectively correspond to the first to 20th tone ranges.
320, timbre setting switches S21 to S23 for determining the waveform shape of the envelope waveform, and an analog/digital converter 322 ( (hereinafter referred to as an A/D converter). That is, each switch S1 to S corresponding to each sound range
The 20 movable contacts P have four fixed contacts a, b, c,
The encoder 301 to 320 is configured so that it can be set to close any one of the fixed contacts among the four setting states, and each encoder 301 to 320 outputs a 2-bit note scaling parameter signal according to these four setting states.
It is configured to output P ₁ and P ₂ . Tone setting switches S21 to S23 are switches for setting the tone of musical sounds generated by electronic musical instruments such as pianos and organs, and the switches S21 to S23 have a logical value of "1" when turned on as shown in the figure. It is configured to output 1-bit tone color setting parameter signals _P3 to _P5 , respectively. Also, depending on the setting state of the sliding terminal of the variable resistor 321, the A/
The D converter 322 is configured to output 4-bit envelope waveform _parameter signals P6 to _P9 , and these envelope waveform parameter signals _P6 to _P9 determine the initial level, attack level, and Attack time and the like are set inside the tone generator 5. As described above, the 47-bit parameter signal PS is output from the parameter selection switch 3 (the note scaling parameter signal is 40 bits (P ₁ , P ₂ ), and the tone setting parameter signal is 3 bits (P ₃ , P _{4 )} . , P ₅ ) and 4-bit envelope waveform setting parameter signals (P ₆ , P ₇ , P ₈ , P ₉ ), resulting in a total of 47 bits. The parameters are input to the parameter signal input device 4 in the same way. Next, the parameter signal input device 4 will be explained in detail. As shown in Figure 3, the 47-bit parameter signal output by parameter selection switch 3
PS is input to selector 401. The output side of the selector 401 is connected to the input side of the parameter signal storage memory 402, and the output side of the parameter signal storage memory 402 is connected to the selector 403.
connected to the input side of the The output terminal of the selector 403 is connected to a first input terminal A of a gate circuit 404, and the output terminal of the gate circuit 404 is connected to the input side of a shift register 405 consisting of 47 stages/1 bit. This shift register 4
The output terminal of 05 is connected to the second input terminal B of the gate circuit 404 and the register 5 of the tone generator 5.
1. Further, as shown in FIG. 3, the output terminal of the oscillator 406 is connected to the flip-flop 40.
7 is connected to the input terminal T of the flip-flop 4.
The output terminal Q of 07 is the write/read command signal input terminal R/ of the parameter signal storage memory 404.
W, inverter 408, and read memory 411
enable signal input terminal EA and gate circuit 40
4 gate control signal input terminals G, respectively. The output terminal of the inverter 408 is connected to an enable signal input terminal EA of a write counter 409, and a clock pulse _φ2 is input to the write counter 409. The output side of the write counter 409 is connected to the selection command signal input terminal S of the selector 401 and the write address signal input terminal AW of the parameter signal storage memory 402. The output side of the readout memory 411 described above is composed of 6 bits, the upper 3 bits of which are connected to the readout address signal input terminal AR of the parameter signal storage memory 402, and the lower 3 bits of which are used as the selection command of the selector 403. Connected to signal input terminal S. Furthermore, a read counter 410 is provided at the address signal input terminal of the read memory 411, and this read counter 410 receives a clock pulse φ ₃ (generally a clock pulse φ ₂
higher frequency) is input. Parameter signal input device 4 having the above configuration
The operation of is explained below. The operation of this parameter signal input device 4 is as follows:
The parameter signal write operation is divided into a parameter signal write operation in which the parameter signal PS is written in the parameter signal storage memory 402, and a parameter signal read operation in which the parameter signal PS stored in the parameter signal storage memory 402 is sequentially read out as serial data SD. In FIG. 3, an oscillator 406 and a flip-flop 407 have the function of specifying a parameter signal write operation and a parameter signal read operation.
That is, flip-flop 407 alternately outputs logical values "1" and "0" from its output terminal Q in accordance with clock pulse _φ1 outputted from oscillator 406. When the logical value "0" is output from the output terminal Q, this logical value "0" is input as the write command signal WS to the write/read command signal input terminal R/W of the parameter signal storage memory 402, and this Since the logical value "0" is input to the gate control signal input terminal G of the gate circuit 404 and the enable signal input terminal EA of the writing counter 409 via the inverter 408, the entire parameter signal input device 4 performs the parameter signal writing operation. Prepare for. Furthermore, when a logic value "1" is output from the output terminal Q of the flip-flop 407, this logic value "1" is transferred to the memory 40 for storing parameter signals.
2 write/read command signal input terminal R/W
This logical value "1" is inputted to the gate control signal input terminal G of the gate circuit 404 and the enable signal input terminal EA of the readout memory 411, so that the parameter signal input device 4 The whole is ready for a parameter signal read operation. Next, the operation of the parameter signal input device 4 will be explained separately into (A) a parameter signal write operation and (B) a parameter signal read operation. (A) Parameter signal writing operation When the flip-flop 407 outputs the logical value "0", the parameter signal storage memory 402 receives this logical value "0" as the write command signal WS and enters a write-enabled state, as described above. Furthermore, this logical value “0” is the inverter 40
8, the signal is inverted to a logic value "1" and input to the enable signal input terminal EA of the write counter 409. Therefore, the writing counter 40
9 starts counting operation of clock pulse _φ2 ,
The counted value is transmitted to the selection command signal input terminal S of the selector 401 and to the parameter signal storage memory 402.
The write address signal is input to the write address signal input terminal AW. Therefore, the selector 401 selects and outputs appropriate bits from among the various parameter signals PS output by the parameter selection switch 3 according to the count value of the write counter 409. In this embodiment, the selector 401 is configured to select and output each bit of the parameter signal PS as shown in Table (1).

【table】

[Table] In Table (1), when the count value of the counter 409 is 2 and 5, only a 4-bit signal is output, but the output of the selector 401 is composed of 8 bits, and in this case, the selector 401
The selected parameter signal shown in Table (1) is output to the upper four bits of the output. Furthermore, when the count value is 6, not even one bit of the parameter signal PS is selectively output. Further, when the count value is 7, only 7-bit signals are selectively output, but in this case, the selected parameter signals are output to the upper 2 to 7 bits of the output terminal of the selector 401, respectively. Parameter signal storage memory 402 receives the count value of counter 409 as a write address signal, and stores the parameter signal output by selector 401 at the designated address. Therefore, when the count value of the counter 409 is 0 as shown in FIG. be done. Further, when the count value is 1, each note scaling parameter signal P ₁ , P ₂ of the 5th to 8th range is stored in the first address of the parameter signal storage memory 402, and similarly, the second to
9th to 20th addresses as shown in Figure 4A to the 5th address.
Parameter signal for scaling each note in the range
P ₁ and P ₂ are stored. Further, as shown in FIG. 4A, the tone color setting parameter signals P ₃ to P ₅ and the envelope waveform setting parameter signals P ₆ to _{P 7} are stored at the seventh address. When the parameter signal writing operation described above is being performed, the logic value "0" is input to the gate control signal input terminal G of the gate circuit 404, so the gate circuit 404 cuts off the input terminal A and inputs Make terminal B conductive. Therefore, in this case, various parameter signals PS stored in the shift register 405 are converted into serial data SD by the parameter signal reading operation described later of the parameter signal storage memory 402.
The signal is repeatedly supplied to the shift register via the gate circuit 404. Therefore, the shift register 405 repeatedly outputs the same serial data SD. This new parameter signal PS is stored in the parameter signal storage memory 402.
This is to prevent the output of the serial data SD from being interrupted and the musical tone forming operation in the tone generator 5 shown in FIG. 1 to be interrupted when storing the data. Also, during the parameter signal write operation, the enable signal input terminal of the read memory 411 is
A logical value “0” is input to the EA. Therefore,
The read memory 411 is held in an inactive state and has no effect on the parameter signal write operation described above. Next, various parameter signals stored in the parameter signal storage memory 402 in this way are
This section describes the read operation of PS. (B) Parameter signal reading operation When the oscillator 406 outputs the clock pulse _φ1 , the flip-flop 407 is inverted and outputs a logic value "1" from the output terminal Q. This logical value "1" is input to the parameter signal storage memory 402 as the read command signal RS, and the parameter signal storage memory 402 becomes in a readable state. Furthermore, this logical value “1” is the enable signal input terminal of the read memory 411.
Input into EA. Therefore, the read memory 411 receives the count value of the clock pulse _φ3 outputted by the read counter 410 as a read address signal, and outputs the 6-bit signal stored in each address. This read memory 411 is composed of a read-only memory consisting of 1 word (6 bits) and 47 addresses, and the upper 3 of 1 word (6 bits)
The bit has a memory 402 for storing parameter signals.
A read address signal that specifies each address is stored, and the lower 3 bits specify each bit of the 8-bit data read from the address of the parameter signal storage memory 402 specified by the read address signal. A selection command signal for selectively outputting from the selector 402 is stored. Therefore, each address of the readout memory 411 stores information specifying each bit of each address of the parameter signal storage memory 402, and the counting operation of the clock pulse _φ3 of the readout counter 410 Accordingly, each bit in the parameter signal storage memory 402 is sequentially specified one by one and output from the selector 403. In this embodiment, each bit of the parameter signal storage memory 402 is specified in the order shown in FIG. memory 40
2 read address signals and a selection command signal for the selector 403 are stored. Figure 4A,
As is clear from B, in this embodiment, the note scaling parameter signal P ₁ of the 20th range is outputted from the selector 403 first, and the note scaling parameter signal P ₁ of the 19th range is outputted secondly from the selector 403. Similarly, each note scaling parameter signal _P1 of the 18th to 1st ranges is outputted from the selector 403 in the same manner. Subsequently, the note scaling parameter signal P ₂ for the 20th range is output from the selector 403 at the 21st time, the note scaling parameter signal P ₂ for the 19th range is output from the selector 403 at the 22nd time, and so on. 18th~
Each note scaling parameter signal P ₂ in the first range is output from the selector 403 . Subsequently, the envelope waveform setting parameter signals P ₉ to _{P 6} are output from the selector 403 at the 41st to 44th positions, and the timbre setting parameter signals P ₅ to _{P 3} are output from the selector 403 at the 45th to 47th positions. . As described above, various parameter signals PS (P ₁ , P ₂
~P ₉ ) is input to the input terminal A of the gate circuit 404 . At this time, since the logic value "1" described above is input to the gate control signal input terminal G of the gate circuit 404, the gate circuit 404 makes the input terminal A conductive and the input terminal B cut off.
Therefore, the gate circuit 404 outputs various parameter signals PS serially output from the selector 403 to the shift register 405. The shift register 405 has 47 stages, and sequentially registers the 47-bit various parameter signals PS (P ₁ to P ₉ ) serially outputted from the gate circuit 404 to each stage, and delays them by 47 bits. It is output as serial data SD. At this time, the serial data SD output from the shift register 405 is input to the input terminal B of the gate circuit 404, but as described above, this input terminal B is in a cut-off state during the parameter signal read operation, which causes a problem. There isn't. As mentioned above, during the parameter signal writing operation, the input terminal B of the gate circuit 404
becomes conductive, and various parameter signals PS stored in the shift register 405 are repeatedly output as serial data SD. Further, the read counter 410 is automatically reset when the count value reaches 46, and is configured to output a logic value "1" from the reset signal output terminal RO at that time. This logical value "1" is input to the register 51 of the tone generator 5 shown in FIG. 1 as the final address signal FA which means that all the signals stored in the parameter signal storage memory 402 have been read out. . Next, the register 51 in the tone generator 5 shown in FIG. 1 will be explained in detail. Serial data SD output from the parameter signal input device 4 is input to the input side of a 7-stage/1-bit shift register 501. The output side of this shift register 501 is connected to the input side of a 20 stage/1 bit shift register 502. The output side of this shift register 502 is a 20 stage/1 bit shift register 503.
connected to the input side of the shift register 50
Output terminals 1 to 7 of each stage of 1 are connected to input terminals of each stage of a latch circuit 504 having seven stages, and the shift register 50
Output terminals 1 to 20 of each stage of 2 are connected to input terminals of each stage of a latch circuit 505 having 20 stages, and further connected to a shift register 50.
The output terminals 1-20 of each of the three stages are connected to the input terminals of each stage of a latch circuit 506 having twenty stages. Further, each output terminal 1 to 20 of each stage of the latch circuit 506 is connected to the input side of each AND circuit A1 to A20 as shown in the figure, and each output terminal 1 to 20 of each stage of the latch circuit 505 is connected to the input side of each AND circuit A1 to A20, respectively, as shown in the figure. is each AND circuit A21~
Connected to the input side of A40. Also, as shown in FIG. 5, this register 51 has a key assigner 2.
A decoder 50 receives the upper 5 bits of the key code KC output from the decoder 50 and decodes and outputs the value.
7 is provided. The output terminal 1 of this decoder 507 is connected to the input sides of AND circuits A1 and A21, the output terminal 2 of the decoder 507 is connected to the input sides of AND circuits A2 and A22, and in the same way, each output terminal 3 of the decoder 507 ~20 are AND circuits A3 and A23~A20, respectively, as shown in the figure.
and is connected to the input side of A40. In addition, the output sides of AND circuits A1 to A20 are each OR circuits.
Connected to the input side of OR1, AND circuit A
The output sides of 21 to A40 are connected to the input side of the OR circuit OR2. Furthermore, latch circuits 504,5
A final address signal FA output from the read counter 410 of the parameter signal input device 4 is input to each latch command signal input terminal L of 05 and 506. This tone generator 5 having the above configuration
Next, the operation of the register 51 will be explained.
Shift register 40 of parameter signal input device 4
Serial data SD output from 5 is sequentially input to each stage of shift registers 501, 502, and 503. As mentioned above, serial data
SD is a parameter signal P ₁ for note scaling in the 20th to 1st range, a parameter signal P ₂ for note scaling in the 20th to 1st range, a parameter signal P ₉ to _{P 6} for envelope waveform setting, and a parameter signal for tone setting. They are output in the order of _P5 to _P3 . Therefore, note scaling parameter signals _P1 of the first to 20th ranges are registered in the first to 20th stages of the shift register 503, respectively, as shown in FIG. 6A. In addition, the first shift register 502
As shown in FIG. 6B, the note scaling parameter signals _P2 of the first to 20th tonal ranges are registered in the to 20th stages, respectively. Further, the first to seventh stages of the shift register 501 are provided with tone setting parameter signals P ₃ to 7, respectively, as shown in FIG. 6C.
P ₅ , parameter signal for envelope waveform setting P ₆ ~
P ₉ is registered. In addition, in FIGS. 6A and 6B, the numbers indicate note scaling parameter signals P ₁ ,
It shall indicate the range of _P2 . As shown in Figure 6A, B, and C, the shift register 5
Various parameter signals PS at 01, 502, 503
(P ₁ to _{P 9} ) are registered, the final address signal FA is sent to the parameter signal input device 4 described above.
This signal is output from the readout counter 410 and is input to the latch command signal input terminal L of each latch circuit 504, 505, 506. Therefore, each stage of latch circuit 504 is connected to shift register 50.
The contents of each stage of the latch circuit 505 are latched as they are, and each stage of the latch circuit 505 is connected to the shift register 50.
Each stage of the latch circuit 506 latches the contents of each stage of the shift register 503 as is. Therefore, each stage of the latch circuit 506 is latched with the note scaling parameter signal _P1 of the 1st to 20th range as shown in FIG. 6A, and each stage of the latch circuit 505 is latched with the note scaling parameter signal P1 as shown in FIG. 6B. Note scaling parameter signals P ₂ for the 1st _to 20th ranges are latched as _shown in FIG. Parameter signals P ₆ to _{P 9} are latched. The tone color setting parameter signals P ₃ to _{P 5} and the envelope waveform setting parameter signals P ₆ to _{P 9} latched by the latch circuit 504 are output as they are to the inside of the tone generator 5 and used for generating musical tones. Note scaling parameter signals P ₁ and P ₂ corresponding to each tone range latched by the latch circuits 505 and 506 are output as follows. That is, the decoder 507 receives the signal of the upper bit of the key code KC indicating to which range the pressed key belongs, and outputs a logical value "1" from one output terminal 1 to 20 corresponding to the range to which the pressed key belongs. for example,
If the pressed key belongs to the first tone range, the decoder 507 outputs a logical value "1" from the first output terminal 1. This logical value "1" is input to AND circuits A1 and A2, AND circuit A1 outputs the note scaling parameter signal _P1 of the first range stored in the first stage of latch circuit 506, and AND circuit A21 outputs the note scaling parameter signal P1 of the first range stored in the first stage of latch circuit 506. The note scaling parameter signal P ₂ of the first range stored in the first stage of the latch circuit 505 is output. The note scaling parameter signal _P1 output from the AND circuit A1 and the note scaling parameter signal _P2 output from the AND circuit A21 are input into the tone generator 5 via OR circuits OR1 and OR2, respectively, and are used to generate musical tones. Ru. The various parameter signals PS (P ₁ to P ₉ ) output as serial data SD from the parameter signal input device 4 as described above are used for generating musical tones inside the tone generator. In the above explanation, the case where this invention was applied to a parameter signal input device for an electronic musical instrument was explained, but this invention is not limited to this.
It can also be used in other devices that need to serially output data stored in memory one bit at a time. As is clear from the above description, according to this invention, desired bits at a desired address of a memory storing a large amount of various data consisting of a plurality of bits can be read out in a desired order. Therefore, even if there are blank bits at each address in the memory, the selector excludes such blank bits and specifies each bit to read out, so data cannot be serialized like in conventional memory reading devices. It does not take a long time to output the serial data, and the capacity of the device that receives this serial data can be configured to be small.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of the configuration of an electronic musical instrument having a parameter signal input device to which this invention is applied, Fig. 2 is a block diagram showing a parameter selection switch of the electronic musical instrument shown in Fig. 1, and Fig. 3. 1 is a block diagram showing an example of the parameter signal input device for the electronic musical instrument shown in FIG. 1, and FIG. An explanatory diagram showing an example of storing various parameter signals in each bit of an address, FIG. 4B shows various parameter signals stored in each bit of each address of the parameter signal storage memory shown in FIG. 4A. FIG. 5 is a block diagram showing an example of a register built into the tone generator of the electronic musical instrument shown in FIG. 1;
6A, B, and C are explanatory diagrams showing various parameter signals registered in the three shift registers constituting the register shown in FIG. 5. FIG. 3... Parameter selection switch, 4... Parameter signal input device, 401, 403... Selector, 402... Memory for parameter signal storage, 4
04...Gate circuit, 409...Writing counter, 410...Reading counter, 411...
...Reading memory.

Claims (1)

[Claims for Utility Model Registration] A first memory storing various data consisting of a plurality of bits; a selector for selectively outputting one bit of the plurality of bits of data read from the first memory; In order to sequentially instruct each bit of various data stored in the first memory in a predetermined order, bit instruction data consisting of a read address signal for the first memory and a selection command signal for the selector is sent to each address. A memory reading device comprising: a second memory that sequentially stores data in the second memory; and a read address signal generator that generates a read address signal for reading the second memory.