JP2586446B2 - Tone generator - Google Patents

Description

Description: TECHNICAL FIELD [0001] The present invention relates to a musical sound generator.

[Prior Art] Conventionally, some tone generators have tone waveform data stored therein. Further, in recent years, an external tone is sampled in addition to an internal tone, stored as waveform data, and a tone is generated and generated based on the waveform data of the external tone.

[Problems of the prior art] However, a desired tone cannot be obtained with a tone generator that only has internal sounds, or when an external tone is selected by a tone generator that has a sampling function, the external tone is stored in the external tone storage means. If not, no musical tone is generated. Then, there is a problem that the user mistakes it for a failure.

In some cases, automatic performance is performed only by using internal sounds stored in advance. However, with this configuration, automatic performance using external sounds cannot be enjoyed.

[Object of the Invention] The present invention has been made in view of the above-described circumstances, and an object of the present invention is to generate a musical tone even when an external sound is not stored when a tone of an external sound is selected. It is an object of the present invention to provide a musical sound generating device capable of causing a sound to be generated.

[Summary of the Invention] In order to achieve the above-mentioned object, the present invention provides a method of selecting an external sound, and if it is determined that the external sound is not stored in the external sound storage means, the waveform of the internal sound is used instead. The main point is that the data is provided to the musical tone generation instructing means to generate a musical tone.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view of a key operation unit 1 of an electronic musical instrument. In the figure, reference numerals 3 and 4 denote a lower keyboard and an upper keyboard. Above the lower keyboard 3 and the upper keyboard 4, a demonstration automatic performance key 2, A sampling key 5, an external sound key 6, and an internal sound key 7 are provided. By operating the sampling key 5, an external sound is sampled and stored as waveform data.
By operating the external sound key 6, manual performance with the sampled and stored external sound becomes possible, and the internal sound key 7
With this operation, a manual performance can be performed with the internal sound stored in the electronic musical instrument in advance. Demo automatic performance key 2
By the operation described above, if an external sound has already been stored, a demonstration automatic performance using an external sound is performed. If no external sound has been stored, a demonstration automatic performance using an internal sound is performed.

<Overall Circuit Configuration> (Configuration of Waveform Data Access Portion) At the time of the sampling process by operating the sampling key 5, the external sound signal input from the microphone 8 in FIG. Is converted into a digital signal at the same time, is sampled at predetermined intervals, and its waveform data is written to the external sound RAM 11 via the gate G1.

At the time of the external sound demonstration automatic performance processing by the operation of the demonstration automatic performance key 2, the waveform data of the external sound in the external sound RAM 11 is read for each of the sounding channel timings of the performance parts of the bass, arpeggio, obligato, and melody. The demo automatic performance sound is output by the external circuit.

At the time of the internal sound demonstration automatic performance processing by the operation of the demonstration automatic performance key 2, the waveform data of the internal sound in the internal sound ROM 12 is similarly read for each of the sounding channel timings of the bass, arpeggio, obligato and melody performance parts. The output is given to the output circuit 13 and the demo automatic performance sound is emitted by the internal sound.

(Configuration of address processing part) The automatic performance data required for these automatic performances
For each of the arpeggio, obligato and melody performance parts, the key-on code and key-off code from the music ROM 15 read out by the CPU 14 are given to the CPU 14. When a key-on code is given, the external sound RAM 11
Alternatively, various address data necessary for reading the internal sound ROM 12 are set in the return address section 17, the start address section 18, and the end address section 19 by the CPU 14 via the interface 16 at the sounding channel timing of the performance part. . Also at the time of the sampling process, various address data necessary for writing in the external sound RAM 11 are set in the start address section 18 and the end address section 19 at the timing of the first channel.

The start address section 18 has a writing start (start) address of the external sound RAM 11 or the external sound RAM 11 and the internal sound ROM in the sampling processing or the demonstration automatic performance processing.
Twelve read start addresses are set. In the end address section 19, the writing end (end) address of the external sound RAM 11, the external sound RAM 11, and the internal sound ROM 12 are also stored in the sampling processing or the demonstration automatic performance processing.
Is set. The return address section 17 contains the demo automatic performance processing
When the waveform data is repeatedly read from the external sound RAM 11 and the internal sound ROM 12, a read return address is set.

The return address from the return address section 17 or the start address from the start address section 18 is set in the address set section 20 via the gates G2 and G3, respectively, and is sequentially incremented by the increment section 21 to set the gate G4. Via the external sound RAM 11 and the internal sound ROM 12. The sequentially incremented address is also supplied to the matching circuit 22. When the address matches the end address from the end address section 19, the match signal a is inverted by the NOR gate NR1 via the AND gate A1 and output to the gate G4. G4 is closed and the output of the increment address from the increment unit 21 is blocked, and the match signal a is also output to the gate G2 via the AND gate A1, the inverter I1, and the NOR gate NR2, and the return address unit 17 Is set or reset in the address set section 20.

(Configuration of Waveform Data Access Frequency Setting Portion) The increment cycle of the above-described start address or return address and the sampling cycle at the time of the sampling process are determined by the frequency data set unit 23, the count frequency data unit 24, and the increment unit 25. In the frequency data set unit 23, frequency data corresponding to the above-described increment frequency or sampling frequency is set by the CPU 14, transferred to the count frequency data unit 24 via the gate G5, sequentially incremented by the increment unit 25, and the gate G6 Is set again in the count frequency data section 24 via. When the frequency data is incremented to “11... 1”, the AND gate A2 outputs the step signal b. This step signal b is supplied as an increment signal to the increment section 21 via the AND gate A3, and the sound emission drive signal CNT is sent to the output circuit 13.
And further supplied to the AND gate A1 as an opening signal.

The step signal b is supplied as a sampling signal c to the A / D converter 10 through a two-phase flip-flop 26 via an AND gate A4.
Is supplied as an open signal to the gate G1 and is supplied as a write command signal to the ▲ ▼ terminal of the waveform RAM 11 at the timing of the clock signal φ1 via the NAND gate NA, as well as the ▲ ▼ of the external sound RAM 11 and the internal sound ROM 12. The terminal is provided as an input / output control signal. This ▲ ▼ terminal is
When the input / output control signal is "1", data writing is possible, and when the input / output control signal is "0", data reading is possible. The AND gate A4 is opened by an output signal from the sampling flag register 27 set by the CPU 14 at the time of the sampling process. The sampling flag register 27 outputs the coincidence signal output when the sampling write process reaches the end address. Reset by a.

The step signal b is supplied to the gate G5 via an OR gate R1 as an opening signal, and is also inverted by an inverter I2 via an OR gate R1 and supplied to a gate G6 as an opening signal. The data is preset again in the count frequency data section 24.

(Configuration of Channel Assignment Part for Each Performance Part) The return address section 17, the start address section 18, the end address section 19, and the frequency data set section 23 described above are four-stage circular registers. The frequency data section 24 is a four-stage shift register,
The address and frequency data for each performance part are
It is preset to the stage corresponding to the sound channel of the performance part. In this case, the first channel is assigned a base part, the second channel is assigned an arpeggio, the third channel is assigned an obligato, the fourth channel is assigned a melody, and the first channel is used in addition to the above-mentioned base and sampling sampling processing. Also used as an external sound writing channel.

When each performance part or write external sound is assigned to each channel, the first on-flag register 28 and the second
The CPU 14 is stored in the corresponding registers of the on-flag register 29, the third on-flag register 30, and the fourth on-flag register 31.
Sets the flag "1". Each of these registers 28
To 31 store that the assignment is made to the corresponding channel, and each output of each register 28 to 31 is
The signals are output from the NOR gate NR3 via AND gates A5 to A8 which are opened by the channel timing signals TP1 to TP4 from the performance part channel counting section 32, respectively. At the time of channel assignment, this output is supplied to the gate G5 through the OR gate R1 as an open signal, and is also inverted by the inverter I2 and supplied as a close signal to the gate G6. In addition to being transferred to the data section 24, the signal is supplied to the gate G3 as an open signal, and the NOR gates NR1, N
The signal is inverted by R2 and supplied to the gates G4 and G2 as a closing signal, and the start address of the start address section 18 is transferred to the address set section 20. Furthermore, the above NOR gate NR
After the channel is allocated, the output of 3 is inverted by the inverter I3 and supplied to the AND gate A3 as an opening signal, so that the step signal b is output and the address increment and sampling are performed. .

The return address section 17, the start address section 18,
End address section 19, frequency data setting section 23, sampling flag register 27, first on-flag register 28,
Second on-flag register 29, third on-flag register 3
0, presetting of various addresses, frequency data, and flags to the fourth on-flag register 31 are performed by various latch clock signals RTL, STL, ENDL, and f from the operation decoder 33.
L, ADCCR, ONFCK1, ONFCK2, ONFCK3, ONFCK4. The operation of each circuit described above is performed in synchronization with the clock signals φ ₁ and φ ₂ from the clock generator 34.

<Structures of the external sound RAM 11 and the internal sound ROM 12> FIG. 3 shows a specific structure of the external sound RAM 11 and the internal sound ROM 12, and consecutive addresses are assigned to the external sound RAM 11 and the internal sound ROM 12. Internal sound ROM12 is 0000-7FF
It has the capacity of the address of F (hexadecimal value, same hereafter), 0000
~ 1FFF is base, 2000-3FFF is arpeggio, 4000-5FFF
Indicates an obligato, 6000 to 7FFF stores the waveform data of the internal sound of the melody, and the external sound RAM 11 has an address capacity of 8000 to 9FFF, and stores the waveform data of the external sound.
The start addresses of these performance parts are 0000, 2000,
4000, 6000, 8000, end address is 1FFF, 3FF
F, 5FFF, 7FFF, 9FFF, and return addresses are set to 1000, 3000, 5000, and 7000 in the middle.

These addresses are given to the external sound RAM 11 and the internal sound ROM 12 from the address setting section 20 while being incremented.
, The most significant bit that becomes “0” is the internal sound
The signal is supplied to the ROM 12 as a chip select signal, inverted by the inverter I4, and supplied to the external sound RAM 11 as the chip select signal セ レ ク ト.

<Configuration of Register in CPU 14> FIG. 4 shows the configuration of the built-in register 35 in the CPU 14, in which a demonstration automatic performance flag and an external sound discrimination flag are respectively stored. The demonstration automatic performance flag is set when the demo automatic performance key 2 is operated, and the tone of the automatic performance is set such that the external sound has priority over the internal sound, and the internal sound is generated only when the external sound is not stored. Become. The external sound discrimination flag indicates whether the demonstration automatic performance is to be performed with an external sound or an internal sound. When the external sound RAM11 is used to automatically perform a demo with an external sound, “1” is used, and the internal sound ROM 12 is used. It is set to "0" when the demonstration automatic performance is performed with the internal sound.

<Structure of Performance Part Channel Counting Unit 32> FIG. 5 shows a specific structure of the performance part channel counting unit 32. Three two-phase flip-flops which are fetched and output by the clock signals φ ₁ and φ ₂ are used. And 36, 37, 38 and NOR gate NR4.
The outputs of the phase flip-flops 36 to 38 are input to the two-phase flip-flop 36 via the NOR gate NR4. When all outputs of the two-phase flip-flops 36 to 38 are "0", "1" is output from the NOR gate NR4, which becomes the first channel timing signal TP1, and this signal TP1 is taken into the two-phase flip-flop 36. The signal shifted and output becomes the timing signal TP2 of the second channel.
A signal obtained by shifting P2 into the two-phase flip-flop 37 and outputting it is a third-channel timing signal TP3. A signal obtained by shifting this signal TP3 into the two-phase flip-flop 38 and outputting it is a timing signal of the fourth channel. It becomes signal TP4. When the signal TP2 is output, the signal TP1, which is the output of the NOR gate NR4, becomes "0", and this "0"
Since the signals are sequentially shifted and input after the "1" signal sequentially shifted and output as the channel timing signal, one of the channel timing signals TP1 to TP4 always becomes "1" as shown in FIG.

<Configuration of Operation Decoder 33> FIG. 7 shows a specific configuration of the operation decoder 33, in which a 13-bit command is given from the CPU 14, and the operation content of each bit is set to IN1 as shown in FIG. ~ IN5 is a flag set command to set ON flag and sampling flag of each channel.
~ IN9 is a command for specifying a channel to set various addresses and frequency data, IN10 ~ IN13 are frequency data,
It is a command for a return address, start address, and end address data set.

This command data is output via the latches 39 and 40, and the flag set command of IN1 to IN5 is generated by the AND gate A which is opened by the third channel timing signal TP3.
Output through 9 to A13. The data set commands of IN10 to IN13 are output via AND gates A18 to A21, respectively, and the channel designation commands of IN6 to IN9 are output via AND gates A14 to A17 which are sequentially opened by channel timing signals TP1 to TP4, respectively. In synchronization with the respective channel timings, the signals are given to the AND gates A18 to A21 via the OR gate R2, and various addresses and frequency data are output in synchronization with the timing of the channel to be set. Therefore, the channel designation commands of IN6 to IN9 and the data set commands of IN10 to IN13 are output simultaneously.

Latching of the command data to the latch 39 is performed by a third channel timing signal TP3 provided via an AND gate A22, and then latching to the latch 40 is performed by a first channel timing signal TP1,
Finally, the latch command data of the latch 39 is reset by the second channel timing signal TP2 provided through the AND gate A23. And gate A22 above
Is opened by the write signal W shown in Figure 6 the lower part of the CPU 14, the AND gate A23 is opened by the clock signal phi _1.

<Configuration of Output Circuit 13> FIG. 9 shows a specific configuration of the output circuit 13. The waveform data read from the external sound RAM 11 or the internal sound ROM 12 is stored in the latches 41 to 44 for each channel. The signal is latched, converted into an analog signal by the D / A converters 45 to 48, amplified by the amplifier 49 via the mixing resistors r1 to r4, and then a demo automatic performance sound is output from the speaker 50. Latching of the waveform data to the latches 41 to 44 is performed by a stepping signal b output at a frequency corresponding to the frequency data, that is, a sound emission drive signal CNT. This sound emission drive signal C
NT is applied to latches 41 to 44 via AND gates A24 to A27, respectively. The AND gate A24~A27 is opened by each channel timing signals TP1~TP4 and clock signals phi _1, latches and sound of the waveform data is synchronized between each channel is timed.

<Structures of Four-Stage Shift Register and Four-Stage Rotating Register> FIG. 10 shows the four-stage shift register and return address part of the address setting unit 20 and the count frequency data unit 24.
17 shows a specific configuration of a four-stage circular register including a start address section 18, an end address section 19, and a frequency data set section 23. 4-stage shift register 55 consists of four two-phase flip-flop 51, 52, 53, each 2-phase flip-flop, inputs the uptake at the timing of the clock signal phi _1, outputs the timing of the clock signal phi ₂ The data for four channels is held and sequentially shifted and output. The four-stage circulating register 56 is provided with a gate G7 on the input side of the four-stage shift register 55, and its output is fed back again via the gate G8 to circulate and hold data for four channels. The gate G7 has various latch signals fL, RTL, and ST from the operation decoder 33.
L and ENDL are given as they are as opening signals, and new data is taken in.The latch signal is inverted and given as an opening signal to the gate G8 by the inverter I5. The data is cyclically retained and repeatedly output.

[Operation of Embodiment] Next, the operation of this embodiment will be described.

<Preparation for automatic demonstration of demo> First, to sample and write the external sound required for automatic demonstration of external sound, turn on the power of the electronic musical instrument, turn on the sampling key 5, and record the external sound with the microphone 8. do it. Then, the CPU 14 sets the all-on flag register 28 based on the power-on as shown in the flowchart of FIG.
~ 31, sampling flag register 27, built-in register 35
Are cleared and the initialization process is performed (step A1), the ON state of the sampling key 5 is determined (steps A2 and A3), the sampling write process is performed (step A4), and the external sound determination flag is set. (Step A5).

In this process, the CPU 14 sets the start address 1
8, the start address is set in the end address section 19, the frequency data corresponding to the sampling frequency is set in the frequency data setting section 23, the sampling flag is set in the sampling flag register 27, and the first
The ON flag is set in the ON flag register 28. Then, a step-up signal b is output from the AND gate A2 at a frequency corresponding to the frequency data, and is output as a sampling signal c via the AND gates A3 and A4.
To the A / D converter 10. This allows
The external sound signal from the microphone 8 is sampled as waveform data by the A / D converter 10 and sequentially written to the external sound RAM 11.

<External Sound Demonstration Automatic Performance> Next, in order to perform a demonstration automatic performance based on the external sound thus sampled and written, the demonstration automatic performance key 2 may be turned on. Then, the CPU 14 determines whether the demonstration automatic performance key 2 is turned on (steps A2 and A3), and
After confirming that the 35 automatic demonstration performance flags have been cleared (step A6), the automatic demonstration performance flag is set and the automatic demonstration performance mode is set (step A7).

Next, since the external sound discrimination flag is set by the sampling writing, it is judged that the demonstration automatic performance of the external sound is possible (step A8), and 800 is returned to the start address section 18 as the start address and the return is performed. 9FFF as return address and end address 17
And the end address section 19 is set for all channels (step A10).

Then, the CPU 14 determines that the apparatus is in the demonstration automatic performance mode from the presence of the demonstration automatic performance flag (step A12), and starts the demonstration automatic performance processing (step A).
13).

This demonstration automatic performance process is performed based on the flowchart of FIG. That is, if the base data read from the music ROM 15 is a key-on code and an on-timing (step B1), the CPU 14 assigns the frequency data corresponding to the pitch of the bass sound to the frequency data Are set in the first on-flag register 28 corresponding to the above (step B2). Hereinafter, if the key-on code is also read for each of the arpeggio, obligato, and melody, the frequency data corresponding to each is stored in the frequency data set unit 23 in the second on-flag register 29 corresponding to each assigned channel.
Third on-flag register 30, fourth on-flag register 31
Is set to "1" (steps B3 to B8).

As a result, a step signal b is output at a frequency corresponding to each frequency data and supplied to the increment section 21. The read address for the external sound RAM 11 is stepped from the start address to the end address, and the read waveform is read. Data is provided to the output circuit 13 at each channel timing, and the sounds of the bass, arpeggio, obligato, and melody are emitted in the tone of the external sound.

In this way, a demonstration automatic performance using an external sound is performed.

If the base, arpeggio, obrigado, and melody data from the music ROM 15 are key-off codes and the timing is off, the CPU 14 sets the on-flag registers 28 and 2 corresponding to the channel to which each performance part is assigned.
Clear the flags “1” of 9, 30, and 31 (steps B9 to B
12). As a result, the sound emission drive signal is no longer supplied to the output circuit 13, and the sound emission of each performance part is terminated.

<Internal Demo Automatic Performance> If no external sound is preset in the external sound RAM 11, the external sound discrimination flag remains cleared, so that even if the demo automatic performance key 2 is operated (step A2). , A3, A6, A7), it is determined that the flag is not present (step A8), and the first channel based on the start, return, and end addresses is 0000, 100, respectively.
The second channels of 0, 1FFF and arpeggio are 2000 and 300, respectively.
The third channels of 0, 3FFF and Obligado are 4000 and 5 respectively.
The fourth channels of 000, 5FFF and melody are 6000 and 700 respectively
0, 7FFF return address section 17, start address section 1
8. Set in the end address section 19 (step A11).

Thereafter, the same processing as the external demonstration automatic performance processing described above is performed (steps A12, A13, B1 to B12), and the internal demonstration automatic performance is performed.

In the case of the internal sound demonstration automatic performance, the return address does not coincide with the end address, so that the waveform data is repeatedly read. Once the end address is read, the sound emission ends there, and no repetitive reading is performed.

In the demonstration automatic performance mode, when the demonstration automatic performance key 2 is further operated, the demonstration automatic performance flag is cleared (step A9), and the mode is released.

In the above embodiment, the type of the external sound and the type of the internal sound are each one. However, a plurality of types are provided so that each of them can be switched and selected in the automatic performance of the demonstration, or the automatic performance of the demonstration by the ensemble of plural sounds can be performed. It may be.

[Effects of the Invention] As described in detail above, if it is determined that an external sound is not stored in the external sound storage means when an external sound is selected, the internal waveform data is used instead to generate a musical sound. Since the sound is given by giving it to the instruction means,
When an external sound is selected, no sound is generated at all, and the user is not mistaken for a malfunction.

[Brief description of the drawings]

FIG. 1 is a plan view of the key operation unit 1, FIG. 2 is an overall circuit diagram of an automatic musical instrument for an electronic musical instrument, FIG. 3 is a diagram showing the configuration of an external sound RAM 11 and an internal sound ROM 12, and FIG. FIG. 5 is a specific circuit diagram of the performance part channel counting unit 32, FIG. 6 is a signal time chart of each part of the performance part channel counting unit 32, FIG.
FIG. 8 is a specific circuit diagram of the operation decoder 33, FIG. 8 is a diagram showing the operation contents of the operation decoder 33, FIG. 9 is a specific circuit diagram of the output circuit 13, and FIG.
FIG. 11 is a specific circuit diagram of the stage shift register 55 and the four-stage circulation register 56, FIG. 11 is a flowchart of an overall process including an external sound demonstration automatic performance process of the CPU 14, and FIG. FIG. 1 Key operation unit 2 Demo automatic performance key 5 Sampling key 8 Microphone 10 A / D converter 11 External sound RAM 12 Internal sound ROM 13 ... output circuit, 14 ... CPU, 35 ... built-in register.

Claims (1)

(57) [Claims] 1. An internal sound storage means for storing waveform data in advance, an input means for inputting waveform data from the outside, an external sound storage means for storing waveform data inputted by the input means, Specifying means for selectively specifying whether to read the waveform data from the internal sound storage means or to read the waveform data from the external sound storage means; and determine whether the waveform data has already been stored in the upper external sound storage means. Determining means for reading the waveform data from the internal sound storage means when the designation means has designated the waveform data to be read from the internal sound storage means, and reading the waveform data from the external sound storage means by the designation means When it is determined that data is to be read out and the determination means determines that the waveform data is stored in the external sound storage means, the external sound storage means The waveform data is read from the row, and the designation means has designated to read the waveform data from the external sound storage means, and the discrimination means has determined that the waveform data is not stored in the external sound storage means. A musical sound generating apparatus comprising: a reading means for reading waveform data from the internal sound storage means; and an instruction means for instructing generation of a musical tone based on the waveform data read by the reading means.