JPS6267596A - Rhythm performer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a rhythm performance device, and in particular, to a sound source ROM that stores a typical predetermined 8-speed source, an additional sound source is written and read out (ii). BnArvt, and data is simultaneously accessed and played from both of these memories during rhythm performance.

[Prior art and its problems] A conventional rhythm performance device uses a sound II ROM in which one typical rhythm sound source is stored in advance. This memory is usually produced by the manufacturer, so the user can use their own rare 9! I wanted a rhythm performance device that would allow me to use the same sound source as IPi't'. In order to meet such demands, the same applicant filed a patent application in 1826-1983.
In No. 88, rhythm e is natural za (e.g., loud cry) 9.
'11! Using if &> RAM that can be performed manually as 'ilQ, natural sounds etc. can be played according to the rhythm pattern via this 7'f source RAM.'11! , F instruments are proposed.

However, the device in this patent application has a configuration in which only one source, either the ROM or the RAM, can be accessed during rhythm performance;
The disadvantage was that the number of sources was limited, and therefore it was not possible to perform rhythmic performances rich in rhythm. The first thing to consider is that the device is
To provide a rhythm performance device capable of performing a rhythm performance with a wide variety by making maximum use of an fm rhythm B source signal.

[Key Points of IJ] In order to achieve the purpose of paragraph L, this invention has the following advantages:
Typical sound source signals included in the source opening OM - as well as i
(Freely written Ex
, and the fIQ signal is also accessed and outputted at the same time by providing an output control F stage.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the entire automatic rhythm performance device. 1 in FIG. 0 is a CPU that controls the entire device by interacting with peripheral devices. 2 is an address control circuit that accesses 11 times the OM4 for Minamotokawa and AM5 for j1 Ryokawa in a 1.1 power type during rhythm performance.
The T details will be explained later. 3 is an address conversion circuit for the open RAM 5, and when the signal AB1 from the CPUI specifies rRAM, access, the 7 traces generated by the CPU are transferred via the address buses AO to A15. RA for 1 key source
Once supplied to M5 4-i 1; A B
When l specifies "rRAM read", the address command from the address control circuit 2 is Internal path direction to be supplied to whale RAM5! /1m gate is controlled.

The ROM 4 for the tuner 1 source stores waveform data of typical rhythm instruments.According to the configuration illustrated in FIG.
3000 is a snare drum, 3000-4000 is Klahess, 4000-5000 is a bibat, 5000-80
Thin/Hell waveform data are stored in 00, respectively.

The sound source III RAM 5 is freely selected by the user.
The source is readable memory. According to the configuration example shown in FIG. 4, the first sample 1) is placed at address 8000 to tooooM#A, and the second sample i'T'k, l2000-1 is placed at address toooo-12000.
A third sample 1 ki can be placed at address 4000.

In the example shown in FIG. 4, the SAP Plua 7 is a rhythm instrument 11 such as a cowbell, a conca, or a bongo, but it is not limited to this, and may also include sounds of animals, the sound of a door closing, etc.
Writing/reading of this sound source RAM 5 is specified by the CPU.
This is done via A B 2.

Rhythm start/stop control switch 2 is one of the control switches JT, and is used to instruct the start and stop of automatic rhythm I:IA.

A rhythm pattern ROM (RAM) 7 is a memory that stores various rhythm patterns such as sun/<, rock, bossa nova, swing, etc. Each pattern is selected via a pattern selection switch (not shown). FIG. 6 shows an example of a rhythm pattern.

The D/A converter 8 is ;f open ROM4,;゛? Gendagawa RA
The analog signal t corresponding to the digital waveform data of M5 et al.
', and the converted analog signal (No. 1 is emitted through amplifier 12 and Nupica 13).

The microphone 11 is exemplified as one stage of external human input, and the analog signal inputted via the microphone is amplified via the amplifier IO.

The A/Df converter 9 converts the data into corresponding digital waveform data.

Address control 1+l dvol 11.4 An example of the configuration of the address control circuit 2 is shown in FIG. 2. This address control circuit 2 can control up to four rhythms at a time. , in Type 1, it can be taken out from the ROM4 for the engine source and the AM5 for the H7 source at the same time. Furthermore, there is no fixed correspondence between channels and rhythm fr IQ, and a sound source designated as an empty channel can be played as appropriate. Broadly speaking, the address control circuit 2 includes a channel number I circuit 2A, a sound source designation circuit 2B, and an address designation circuit 2C.
It is composed of an X source waveform data reading circuit 2D. The channel is designated by the CHO and CHI signals tJ from the CPUI, and the decoder loa of the channel 61 circuit 2A
decodes this signal and activates the corresponding channel. The channel operates to set the corresponding F/F (flip 70 tab) lla-1id.

Gates 12a-12d and tristate gates 13a-13d are coupled to the output of the F/F.

On the other hand, the sound source to be generated is specified by the RH from the CPUI.
This is done using O-RH3 data (4 bits). In the latches 9a to 9d in the sound source specifying circuit 2B, the latch 9
The i'' source specification code assigned to the first channel is loaded into a, the second channel is loaded into latch 9b, the third channel is loaded into latch 9C, and the sound source specification data assigned to the fourth channel is loaded into latch 9d. It has become.

11 The sound source designation code is transferred from the source designation circuit 2B to the address designation circuit 2C through the gate 14a in the sound source designation circuit 2B.
~14d and related operations”r tE timing 4.1
' Bow to -L3. The control clock oscillation circuit 26 generates these clock signals 7-;, 1o.-L.

The address designation circuit 2C first transfers the η source designation code transferred in a time-division format to the corresponding sound source ROM, i'H
The data is converted into the start address data of the corresponding rf source area of the source RAM 4.5, and later converted into the final address data of the same area by the action of the /\-fader 15 (see Figure 5), which will be described in more detail. Then, the gates 114a-14d open the latches 9a-9 according to the timing (It number to-t3).
When passing the data latched in d for the first time, the "+1" function of Half Age-15 is activated by the input If? >+i, and the 1η whale designation coat specifies the address ROM 16 as it is.

As a result, the address ROM 16 is a ROM for reading R keys.

1. Output the first 7F response of the designated rf source area in the open M4.5 for one source. +lr gate 14a
-14d is operated and the latches 9a to 9d are opened "t".
IQ #F1: jj The pass through the coat is in-ta I
Since a carry signal is generated from I, the half adder 15 adds "+1" to the source specifying code (/i).

As a result, the address ROM 16 is j”T 1!a RO
M. Outputs the final address of the designated Fi source area in the sound source RAM 4.5.

]--The operation of inverter II is channel t1'''
It is related to the operation of 1 circuit 2A. That is, in the channel;', 1 "I f" circuit 2A, the gates 12a", 12d, 13a are activated by the timing signal to -tl.
When activating ~13d, F/Flla~11d
The cent output passes only once, and the gate L2a-12d
The corresponding F/F is reset by the output, and from 2 times 11 onwards, the channel;', 1-+ The output of circuit 2A becomes °°L pa. 0For example, if 4 channels are selected, the first timing signal to-Lx becomes the output of the circuit 2A of channel I and 1. This timing output is outputted from the half adder 15 through the impark 11 in a double series.
71 is stopped and raised, and the address increment 11 control circuit 25 (31.48th
gate 27a-
27d, and thereafter a carry signal is inputted to the half-age 20 through the corresponding gates 29a to 29d at each channel timing to""t3. Further, the timing output from the channel-,1'''1 circuit 2A is sent to the j7i waveform data readout circuit 2D.
[Game]-17 is activated, and the address finger is made to take in the start address data of circuit 2C to the address increment loop. After the channel is selected 2
The addressing circuit 2C outputs nothing (output "L") when the timing signal from [1 is Lo-tj].
is used as operation 11 [moat] to output the final address of the specified area 71!1 from the address designating circuit 2C. When the final address data is generated, the gate 17 is set to 1, and the final address should be compared to the comparator 19. The data is manually entered in hours and minutes in 11 formats.

The addressing loop is composed of a cascaded shift register 18 of 16 bits x 4 stages, a half adder 20, and a gate 21 (which becomes active while the output is "L"). The address data taken out from the shift register 18 in a time-division manner is changed to "+1" by the half adder 20 each time, and is returned to the left end of the shift register 18 through the gate 21. As a result, the sound source waveform data readout circuit 2D outputs sequentially incremented address data in a single output format for each hour and minute.
The designated sound source area and address of the sound source memory, i.e., 1"f open ROM4 and the sound source R via the J detection circuit 3.
Specify the designated sound source area of AM5 sequentially from the first address. As a result, the waveform data of the specified multiple sound sources are output in time-sharing format from the ROM4 for both i-sources and the AM5 for 1f Genkawa. A plurality of signals a are simultaneously output through the D/A converter 8, amplifier 12, and speaker 13 shown in FIG.

When the address of a certain channel in the address increment/drop reaches the final address, comparator 19 produces a match output. This coincidence output is output to the corresponding F/F in the address step control circuit 25 as shown in FIG.
F28a-28d are reset via gates 30a-30d.

As a result, the address increment control circuit 25 does not output the carry signal C at the timing applied to the same channel, and the increment of the address associated with that channel is stopped.
In this way, reading of the designated 1f sources is completed for each of the 79 sources.

Note that the address control circuit 2 in FIG. 2 controls the sound source readout at the middle level of the channel, and there is no fixed correspondence between the channel and the sound source. Therefore, for example, the first
Split the channel into cymbals! While the cymbal is being used, that is, before the cymbal 6- has finished playing, another empty channel, for example the third channel, can be selected and used for the cymbal. In other words, the Opara-2 amplifier 11 of the same sound source is If function.

permission Next, the operation of the apparatus having the following configuration will be explained.

(I) Recording into the sound source RAM 5 When loading the sound source waveform data into the sound source RAM 5 (1), the machine is loaded via the -I loading or recording switch (not shown). Set to Rikikomi mode. That is, C
PUI is connected to 1 key source jl RAM 5 via ABI signal.
Connect the hess as shown by addressing A
The FF source RAM 5 is specified via the B2 signal.

Microphone 11. The analog waveform of the sound source to be recorded passes through the amplifier 10 and is guided to the A/D converter 9, where it is converted into corresponding digital waveform data. 'aWhen the size of the input data exceeds a certain value, or the synchronization signal generated by the recording rf start switch, the CPU changes the addresses of RAM5 for H'T Ia sequentially starting from the first address. Since no progress is made, the A/Df-detected waveform data is stored in the sound source RAM 5. When the address of the source RAM 5 reaches a preset address, the recording ends.

(a) Set the machine to the readout mode via the Rhythm Performance Areadout or 111 raw switch (not shown). That is, CPUI is AB
The address control circuit 3 is switched via the I signal so that the address control circuit 2 specifies the address to the sound source RAM 5. If via the AB2 signal
Next, the user operates a pattern selection switch (not shown) to specify a desired rhythm pattern (for example, samba). In response to this, cpu
t is the specified pattern as a rhythm pattern lllROM
(RAM) Select from 7. Here, when the user instructs a start using the rhythm start/stop control switch 6, the CPU controls the rhythm pattern ROM (RAM).
) 7, and select each ff I
f and the channel are specified, and the address control circuit 2 accordingly controls the j'
5 to automatically play the rhythm through the speaker 13.

Now, to explain the case of automatically playing the rhythm pattern shown in Fig. 6, the CPU assigns the first channel to the pass drum, the second channel to the high hat, and the second channel according to the ON code of the pastoral l of beat 11 and the high hat. /<The strum designation code and the high hat designation code are sent to the address control circuit 2 via channel signal lines CHO and CH1 and designation code signal j'i lines RHO to RH3, respectively.
to use human power.

The address ROM 16 in the address designation circuit 2C of the address control circuit 2 is
First number of pass drum area in Q ROM4 #Ao
The final station #A1000 is generated, and the first number Jl! ! 0 is a
It is taken into the address increment loop in the original waveform data reading circuit 2D. Further, the first address 4000 and the last address 5000 of the high hat area are generated by the address ROM 16, and the first high hat number 7114000 is taken into the address increment loop. By the timing signals (clock signals) to to t3 assigned to the channels generated by the control clock oscillation circuit 26, the address data in the 7-trace swing menotruse is incremented by 11 times and 11 methods. Then, at each final address, the address t
The address increment is stopped via the a control circuit 25. Therefore, in the rhythm pattern of FIG. 3, at the 1st beat 11 of
The waveform data of the pass trum and high hat from M4 are led at a time interval of 1, pass through an amplifier 12 and a speaker 13, and are emitted 72 as a signal j'f.

In the same way, for example, on the 8th beat [1, the ON code of the pass drum and sample l (caravelle) is input manually from the rhythm pattern ROM (RAM) 7 to the CPU
1 receives this, applies a pass drum to an empty channel, for example, the first channel, applies sample 1 to the second channel, generates a hestrum designation code and a sample 1 designation code, and supplies them to the address control circuit 2. Similarly, the address control circuit 2 selects r? The first address 0 of the Hess drum area in the source opening OMA, and the first number Jli! of the sample r area in the sound source RAM 5! 8000, and sequentially increments the address with each clock to, t. When the address of the pass drum reaches the final address 1000, the address increment is stopped, and the address of sample l becomes the final address 11! ! When the address reaches 10000, the address increment is stopped (1-). While the address control circuit 2 continues the address increment, the if Genkawa OM4 and the RF source RAM 5 specify the address of the pass drum and sample l (caravelle). The waveform data that has been processed is sequentially extracted at hour and minute intervals 1.1, and is sent to the D/A converter 8. Via the amplifier 12 and the speaker 13, the respective notes 1°t, that is, the bass trum h and the cowbell "7" are output as redirections.

In addition, in the embodiment described in ■--, the rhythm pattern ROM (RA
M) 7 is used to play an automatic rhythm, but instead of this or in combination with this, an F-move rhythm input device may be used to play a rhythm with an L-move, and a human-powered device may be used. can be realized, for example, by a group of switches or a keyboard for selecting each 1'f source. In this case, the CPU generates a corresponding 11-order specified code and determines its channel; L, 1 + in accordance with the switch operation, and transmits the results to the address control circuit 2. Below is 1. In the same manner as in the embodiment described above. The source ROM 4 and the 11 source RAM 5 are simultaneously accessed, and 81 sound sources spanning one memory are simultaneously emitted 1°1' from the 13 sources.

[Effects of the Invention] As described above, this invention provides an additional ft and access RAM that can be read and written freely in addition to the normal OM for rhythm performance. At this time, the 1It4 memory is simultaneously accessed by the output side -r stage so that a plurality of 8-'s are simultaneously output from the speakers. Therefore, (a) depending on the characteristics of the sound source RAM)
(Changing the source, (0) R, A M, !l: Direction output of multiple i'? sources in the sound source ROM (during rhythm performance)
It is possible to create a rhythm with a wide variety of rhythms.
IIrt Kanade becomes o (Noh).

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention. Figure 2 is a diagram showing an example of the configuration of the 7 trace control unit in Figure 1, Figure 3 is a configuration diagram of the address step control unit in Figure 2, and Figure 4 is for the (7) FT & i river shown in Figure 1. OM if Ha
Figure 5 is a map of the address ROM in Figure 2.
FIG. 6 is a diagram showing an example of a rhythm pattern played by the apparatus of FIG. 1. 2... Address control circuit, 4... ROM for sound source, 5... RAM for sound source. Patent Applicant Casio Computer Co., Ltd. Agent Patent Attorney Masashi Machi Machi Figure 1 Figure 3 ROM ρAM Figure 4 Figure 5 Ousu - ・ ・ ・ 4
・Mortule Figure 6 Rhythm 1-,/Ita・

Claims (1)

[Claims] A sound source ROM that stores a predetermined rhythm sound source signal, a sound source RAM that can write and read additional rhythm sound source signals, and output control that simultaneously outputs a plurality of desired sound source signals from the ROM and RAM during rhythm performance. 1. A rhythm performance device comprising: means.