JPS6253839B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument equipped with an automatic performance device, and the degree of follow-up of the tempo of automatic performance to the tempo of manual performance is variably controlled in accordance with the skill level of the performer and the content of the music. This enables tempo tracking control.

2. Description of the Related Art Conventionally, electronic musical instruments equipped with automatic performance devices that automatically generate musical tones or display key presses based on stored data have been known. Furthermore, in such electronic musical instruments, it has already been proposed to control the tempo of automatic performance by following the tempo of manual performance using a keyboard.

However, according to the conventional tempo-following control method, the tempo of automatic performance always follows the tempo of manual performance at a certain degree of follow-up, so the degree of follow-up depends on the skill level of the performer and the content of the song. I was unable to practice and enjoy my performance by changing it appropriately.

SUMMARY OF THE INVENTION An object of the present invention is to provide a novel electronic musical instrument that can perform tempo follow-up control by changing the follow-up degree as appropriate depending on the skill level of the performer and the content of the music.

The electronic musical instrument according to the present invention is provided with means for generating tempo follow-up degree designation data, and makes the tempo of automatic performance follow the tempo of manual performance at the degree of follow-up specified by the tempo follow-up degree designation data. This invention will be described in detail below with reference to embodiments shown in the accompanying drawings.

FIG. 1 shows an electronic musical instrument equipped with an automatic performance device according to an embodiment of the present invention.

A recording medium 10a such as a magnetic tape is attached to the lower margin of the musical score 10, and the recording medium 10a
Musical score data corresponding to the musical score content and tempo data indicating a standard tempo are recorded in the .

The musical score data reading control circuit 12 is connected to the recording medium 10a.
reads the musical score data and tempo data from and supplies the tempo data TED to the tempo control circuit 13, while transferring the melody data of the musical score data to the melody data memory 14 and the accompaniment data to the accompaniment data memory 16 for storage. In order to control such transfer/storage operations, a write address signal WAD, write command signals WT ₁ and WT ₂ , and address selection signals AS ₁ and AS ₂ are sent out. The memories 14 and 16 are both RAM (random access memories), and have corresponding selector circuits 18 and 20.
The address signal is supplied from The selector circuits 18 and 20 perform selection operations in response to the address selection signals AS ₁ and AS ₂ , respectively, and the selector circuit 18 operates when the selection signal AS ₁ is "1".
Then, control input SA is “1” and input A is selected,
If the selection signal _AS1 is "1", the control input SB is "1" and the input B is selected by the inverter 18a.
In addition, the selector circuit 20 has a selection signal AS ₂ of “1”.
Then, control input SA is “1” and input A is selected,
If the selection signal _AS2 is "0", the control input SB is "1" and the input B is selected by the inverter 20a.

When the musical score 10 is inserted into the receiving port of the data reader included in the musical score data reading control circuit 12 and the data reading operation is started, the memory 14 enters the write mode in response to the write command signal _WT1 , and the memory 14 is supplied with a write address signal WAD from a selector circuit 18 which is in a state of selecting input A in response to selection signal _AS1 . For this reason, the memory 14
Melody data corresponding to the melody progression of the musical score 10 is written in the format shown in FIG. 2. That is, the melody data written at this time expresses the melody tones to be generated by a combination of an 8-bit key code KC and an 8-bit length code LNG, and each key code KC is expressed as an example for the note name _C3 . The upper 2 bits are the identification code,
The lower 2 bits are the octave code, the remaining 4 bits are the note code, and each length code is
LNG is the top 2 as shown in the example for an eighth note.
The bit is an identification code, and the remaining 6 bits are a note length code. Rests are key code KC
It is expressed by setting all 6 bits other than the identification code bit to "0". After writing the last melody data, an end code FNS in which all 8 bits are "1" is written into the memory 14. Note that the upper two bits of this end code FNS are also an identification code.

After writing the end code FNS, memory 1
6 enters the write mode in response to the write command signal WT ₂ , and the memory 16 enters the input A in response to the selection signal AS ₂ .
A write address signal WAD is supplied from the selector circuit 20 which is in a state of selecting. For this reason,
Accompaniment data corresponding to the progression of accompaniment (chords or bass notes) of the musical score 10 is written in the memory 16 in a format as shown in FIG. In other words, the accompaniment data written at this time uses an 8-bit key code KC and an 8-bit length code to represent the chord to be generated.
Expressed in combination with LNG, each key code KC has the upper two bits as an identification code, the lower two bits as a chord type code, and the remaining four bits as a root note code, as shown in the example for C _major (CM). It's summery. Here, the chord type code is "00" for major, "01" for minor, and "10" for seventh. Further, in each length code LNG in the accompaniment data, the upper two bits are an identification code, and the remaining six bits are a note length code, as illustrated for a half note.

After the series of data reading/writing operations as described above, the start switch _SW0 of the start/stop control circuit 22 is turned on to operate the melody data reading circuit 24 and the accompaniment data reading circuit 26.
In other words, when you turn on the start switch SW ₀ ,
The on signal is differentiated by the differentiating circuit 28 to rise in synchronization with the system clock signal φ, and is converted into the start signal ΔSTRT. And start signal Δ
STRT causes the R-S flip-flop 30 to be set, so that the flip-flop 30 sends out a play mode signal PLAY consisting of its output Q="1". At this time, since the input signal of the inverter 32 is "0", the output signal of the inverter 32 =
“1” is passed through the OR gate 34 to the AND gate 36
is supplied to. Therefore, AND gate 36
becomes conductive when the performance mode signal PLAY="1" is generated, and outputs the clock signal φ to the address counter 38.
will be supplied to

Address counter 38 receives start signal ΔSTRT
When reset by , the read address signal RAD ₁ corresponding to the first read address is supplied to the selector circuit 18 as input B. At this time, the selector circuit 18 receives the input B by the selection signal AS ₁ =“0”.
, and supplies the read address signal RAD ₁ corresponding to the first read address to the memory 14. Therefore, the key code data corresponding to the first melody tone is read out from the memory 14, the upper 2 bits of which are sent to the identification code detection circuit 40, and the remaining 6 bits of the melody key code (octave code and note) are sent to the identification code detection circuit 40. The code signals are respectively applied to latch circuits 42 which are timed by the clock signal φ.

The identification code detection circuit 40 generates a key code detection signal MK in response to the first key code data from the memory 14, and the latch circuit 42 latches the first melody key code signal in response to this key code detection signal MK. The melody key code signal MKC from the latch circuit 42 is transmitted to the display section 44.
supplied to

The display section 44 is provided with a display control circuit 46 which receives the melody key code signal MKC as an input, and this display control circuit 46 receives the output of the display select switch _SW1 from the AND gate 48 which is conductive in response to the performance mode signal PLAY. When the enable signal EN is supplied in response to the input, the light emitting elements in the light emitting element group 52 provided along the key arrangement of the keyboard 50 are selectively controlled to light up to visually display the key to be pressed. It's summery. Therefore, the first melody key code signal MKC is the note name as shown in the example in Figure 2.
If C ₃ is indicated, the light emitting element corresponding to the C ₃ key lights up, indicating that the key should be pressed.

After the key press display corresponding to the first melody tone starts as described above, when the counter 38 counts the clock signal φ, the memory 14
Length code data corresponding to the first melody tone is read out from. Of the read data at this time, the upper 2 bits of the identification code signal are supplied to the identification code detection circuit 40, and the remaining 6 bits of the melody code length code signal are supplied to the latch circuit 54 which is timed by the clock signal φ. . Then, since the identification code detection circuit 40 generates the length code detection signal ML in accordance with the first length code data from the memory 14, the latch circuit 54 generates the length code detection signal ML according to the first length code data from the memory 14. Latch accordingly. Further, since the length code detection signal ML at this time is supplied to the inverter 32, the output signal of the inverter 32 becomes "0", thereby temporarily stopping the counting operation of the counter 38.

Thereafter, at a time delayed by about 2 bit times of the clock signal φ from the generation point of the start signal ΔSTRT, the two-stage D clock timed by the clock signal φ
- Flip-flop 56 outputs restart signal Δ
Generates STRT′. This restart signal Δ
STRT' is connected to AND gate 36 via OR gate 34.
, the counter 38 again counts the clock signal φ from the AND gate 36. Therefore, the key code data and length code data corresponding to the second melody tone are sequentially read out from the memory 14, and in response to this, the identification code detection circuit 40 outputs the key code detection signal MK and the length code detection signal MK. Generate ML sequentially. The key code detection signal MK at this time causes the latch circuit 42 to transfer the first melody key code signal to a similar latch circuit 58, and also causes the latch circuit 42 to latch the second melody key code signal. Further, the length code detection signal ML at this time causes the latch circuit 54 to transfer the first melody code length code signal to a similar latch circuit 60, and also causes the latch circuit 54 to latch the second melody code length code signal. , and as before, inverter 32
The counting operation of the counter 38 is temporarily stopped.

The melody key code signal MKC corresponding to the second melody tone from the latch circuit 42 is displayed on the display section 4.
Since the second melody tone is supplied to the second melody tone, the display section 44 displays the key depression corresponding to the second melody tone, as in the previous case. Also, at this time, a melody key code signal corresponding to the first melody tone is output from the latch circuit 58.
Since MKC' is supplied to the automatic melody sound signal forming circuit 62, this circuit 62 receives the performance mode signal.
When the enable signal EN is supplied from the AND gate 64 which is conductive in PLAY in response to the turning on of the sound generation select switch SW ₂ , a melody sound signal is electronically synthesized according to the melody key code signal MKC' and output. The signal is supplied to a speaker 68 via an amplifier 66. Therefore, the first automatic melody sound is played from the speaker 68 with a delay of one tone relative to the key press display.

On the other hand, the melody note length code signal MLG corresponding to the first melody note from the latch circuit 60 is supplied to the tempo control circuit 13. Tempo control circuit 1
3 is a melody note length code signal MLG and a melody key code signal, as will be described later with reference to FIG.
MKC, key code signal KKC based on key depression, tempo data TED, tempo clock signal based on performance mode signal PLAY and start signal ΔSTRT
It generates the TCL and readout control signal NEXT, and after the melody note length code signal MLG corresponding to the first melody tone is supplied from the latch circuit 60, the signal MKC and the readout control signal NEXT are generated for the second melody tone.
When a key is pressed so that the KKC key codes match, the first read control signal NEXT is generated.
At this time, the read control signal NEXT is sent from the AND gate 80 which is made conductive by the length code detection signal ML.
The clock signal φ from the AND gate 36 is supplied to the AND gate 36 via the OR gate 34, so that the counter 38 resumes counting the clock signal φ from the AND gate 36. For this reason,
The key code data and length code data corresponding to the third melody tone are sequentially read out from the memory 14, and the latch circuits 58 and 42 receive the second melody key code signal and the third melody key code signal, respectively. The second melody code length code signal and the third melody code length code signal are latched in the latch circuits 60 and 54, respectively. Therefore, the automatic melody sound signal forming circuit 62 forms a melody sound signal corresponding to the second melody sound, the display section 44 displays a key press corresponding to the third melody sound, and the tempo control circuit 13 produces a melody sound signal corresponding to the second melody sound. th read control signal NEXT
An operation is performed to generate the . Then, the above-mentioned operations are repeated in the same manner, thereby performing an automatic key press display based on the data stored in the memory 14 and an automatic performance of a melody tone delayed by one note with respect to this display.

Note that the end code data is finally read out from the memory 14, and in response to this, the identification code detection circuit 40 generates the end code detection signal FN. This end code detection signal FN is applied to the flip-flop 30.
As a result, the performance mode signal PLAY becomes "0" and a series of data reading from the memory 14 is completed.

The key switch circuit 82 includes a large number of key switches each linked to a large number of keys on the keyboard 50, and supplies a key code signal KKC indicating the pressed key to the manual performance sound signal forming circuit 84 and the aforementioned tempo control circuit 13. It's becoming like that. The manual performance sound signal forming circuit 84 electronically synthesizes a melody sound signal corresponding to the pressed key in response to the key code signal KKC from the key switch circuit 82, and supplies the synthesized melody sound signal to the speaker 68 via the output amplifier 66. Therefore, the speaker 68 also produces melody sounds by manual performance.

In this case, if manual performance practice is performed using the keyboard 50, it is possible to efficiently practice performance while listening to the above-mentioned automatic performance sound and/or while viewing the automatic key press display by the light emitting element group 52. When practicing this kind of performance,
Automatic accompaniment of chords or bass notes and/or automatic rhythm accompaniment as described below can also be used as appropriate.

In the accompaniment data reading circuit 26, since the input signal of the inverter 86 is "0" when the start switch SW ₀ is turned on, the output signal of the inverter 86 = "1" is ANDed through the OR gate 88.
It is supplied to the gate 90. Therefore, start switch SW ₀ is turned on and the performance mode signal is output.
When PLAY="1" is generated, AND gate 90
A clock signal φ is supplied from the address counter 92 to the address counter 92.

Address counter 92 receives start signal ΔSTRT
When reset by , the read address signal RAD ₂ corresponding to the first read address is supplied to the selector circuit 20 as input B. At this time, the selector circuit 20 receives the input B due to the selection signal AS ₂ =“0”.
, and supplies the read address signal RAD ₂ corresponding to the first read address to the accompaniment data memory 16. Therefore, the key code data corresponding to the first accompaniment tone is read out from the memory 16, the upper 2 bits of which are sent to the identification code detection circuit 94, and the remaining 6 bits of the accompaniment key code (chord type code and root chord)
The signal is a latch circuit 9 timed by a clock signal φ.
6, respectively.

Identification code detection circuit 94 generates key code detection signal AK in response to the first key code data from memory 16, and latch circuit 96 latches the first accompaniment key code signal in response to this key code detection signal AK.

Thereafter, when the counter 92 counts the clock signal φ, the length code data corresponding to the first accompaniment tone is read out from the memory 16 in the same manner as the previous time. Of the read data at this time, the upper 2 bits of the identification code signal are supplied to the identification code detection circuit 94, and the remaining 6 bits of the accompaniment note length code signal are supplied to the latch circuit 98 which is timed by the clock signal φ. . Then, since the identification code detection circuit 94 generates the length code detection signal AL in accordance with the first length code data from the memory 16, the latch circuit 98 generates the length code detection signal AL according to the first accompaniment note length code signal. Latch accordingly. Further, the length code detection signal AL at this time is supplied to the inverter 86. Therefore, the output signal of the inverter 86 becomes "0" and is passed through the OR gate 88 to the AND
Gate 90 is made non-conductive. Therefore, counter 9
The counting operation of step 2 is temporarily stopped.

After this, the restart signal ΔSTRT′ mentioned above is OR
Since AND gate 90 is made conductive through gate 88, counter 92 again counts the clock signal φ from AND gate 90. Therefore, the key code data and length code data corresponding to the second accompaniment tone are sequentially read out from the memory 16, and in response to this, the identification code detection circuit 94 outputs the key code detection signal AK and the length code detection signal AK. ALs occur sequentially. Key code detection signal at this time
AK causes the first accompaniment key code signal to be transferred from the latch circuit 96 to a similar latch circuit 100, and causes the latch circuit 96 to latch the second accompaniment key code signal. Further, the length detection signal AL at this time causes the latch circuit 98 to transfer the first accompaniment note length code signal to a similar latch circuit 102, and causes the latch circuit 98 to latch the second accompaniment note length code signal. Furthermore, as in the previous case, the counting operation of the counter 92 is temporarily stopped via the inverter 86.

As a result of the above operations, the latch circuit 100 begins to send out the first accompaniment key code signal AKC, and the latch circuit 102 comes to send out the first accompaniment note length code signal ALG. This first accompaniment note length code signal ALG is then supplied to a comparison circuit 104 and compared with the count output K of the tempo counter 106. Here, since the tempo counter 106 is configured to count the tempo clock signal TCL from the tempo control circuit 13 after being reset by the start signal ΔSTRT from the OR gate 108, the comparison circuit 104 calculates the count value of the counter 106. is the first accompaniment note length chord signal
When the value corresponding to the note length indicated by ALG is reached, a match signal EQ is generated.

Since the match signal EQ at this time resets the counter 106 via the OR gate 108, the counter 106 counts the tempo clock signal TCL again after being reset. Further, since the coincidence signal EQ is supplied from the AND gate 110, which is turned on by the length code detection signal AL, to the AND gate 90 via the OR gate 88, the counter 92 is
Counting of the clock signal φ from gate 90 is restarted. Therefore, the key code data and length code data corresponding to the third accompaniment note are sequentially read out from the memory 16, and the latch circuits 100 and 96
2nd accompaniment key code signal and 3rd accompaniment key code signal respectively.
The second accompaniment key code signal is latched, and the second accompaniment note length code signal and the third accompaniment note length code signal are latched in the latch circuits 102 and 98, respectively. As a result, the second accompaniment key code signal AKC is sent out from the latch circuit 100, and the second accompaniment note length code signal ALG is sent out from the latch circuit 102.
Comparison circuit 104 measures the note length of the second accompaniment tone. The above-mentioned operations are repeated in the same manner, so that accompaniment data is successively read out from the memory 16, so that the accompaniment key code signal AKC is sent out from the latch circuit 100 one after another. Note that the reading of data from the memory 16 ends before the end data is read from the memory 14, and the counter 92
The end data is read from 4 and the performance mode signal is sent.
When PLAY returns to "0", it stops advancing like the counter 38.

The accompaniment key code signal AKC sent out from the accompaniment data reading circuit 26 as described above is supplied to the automatic accompaniment tone signal forming circuit 112. The automatic accompaniment sound signal forming circuit 112 generates an enable signal EN from the AND gate 114 which is conductive in response to the performance mode signal PLAY in response to the turning on of the sound generation select switch _SW3 .
is supplied, the accompaniment key code signal AKC
The accompaniment tone signal is electronically synthesized based on the rhythm selection data (not shown), and the accompaniment tone signal includes a chord signal corresponding to a plurality of chord constituent notes, and a bass that matches the chord and rhythm to be generated. It is designed to generate sound signals. and,
The transmission timing of each accompaniment sound signal from the automatic accompaniment sound signal forming circuit 112 is controlled in conjunction with the rhythm according to the accompaniment timing signal AT from the rhythm pattern generation circuit 116.
The accompaniment signal from circuit 112 is supplied to speaker 68 via output amplifier 66 . Therefore, automatic accompaniment sound is also produced from the speaker 68.

The rhythm pattern generation circuit 116 is configured to generate a rhythm pattern signal RP in addition to the accompaniment timing signal AT described above in response to the tempo clock signal TCL from the tempo control circuit 13, and this rhythm pattern signal RP is generated by the rhythm sound source circuit 118.
supplied to The rhythm sound source circuit 118 drives an appropriate rhythm sound source according to the rhythm pattern signal RP to generate a rhythm sound signal, and this rhythm sound signal is also supplied to the speaker 68 via the output amplifier 66. Therefore, the automatic rhythm sound is also produced from the speaker 68.

FIG. 4 shows an example of the display and performance operations of the above-mentioned electronic musical instrument, where A indicates the note progression of the musical score,
B indicates the key press display timing, and C indicates the automatic performance timing of the melody and accompaniment. According to FIG. 4, it can be clearly seen that the key press display precedes the automatic melody tone by one note.

FIG. 5 shows the detailed configuration of the tempo control circuit 13.

The clock signal source 120 generates a first clock signal φ ₁ having a relatively high frequency and a _second clock signal φ ₂ having _a relatively low frequency. It is set several times higher than the frequency. First and second clock signals φ ₁ and φ ₂ are provided to selector circuit 122 as inputs A and B, respectively. Selector circuit 1
22 is supplied with the output Q of the R-S flip-flop 124 as a selection signal SA for selecting input A, and the output Q of the flip-flop 124 is inverted by an inverter 126 as a selection signal SB for selecting input B. A signal is provided.

Before the start signal ΔSTRT is generated, the performance mode signal PLAY is connected to the inverter 128 and the OR
Since flip-flop 124 is reset through gate 130, flip-flop 12
The output Q of 4 is “0”, and the selector circuit 122
selects the second clock signal φ2 in response to a selection signal SB="1" obtained by inverting this output Q="0" by an inverter 126 and supplies it to the counter 132. The counter 132 counts the second clock signal φ2 and supplies the count output to the comparison circuit 134 as one comparison input A.

The manual setting circuit 136 is for manually setting the standard tempo as appropriate, and sends tempo data corresponding to the set standard tempo to the selector circuit 13.
8 as input A. Further, the register circuit 140 stores tempo data TED corresponding to the reference tempo supplied in the form of serial data from the above-mentioned musical score data reading control circuit 12, and sends the tempo data TED to the selector circuit 138 in the form of parallel data. It is designed to be supplied as input B. The selector circuit 138 generates a selection signal based on the operation of the selection switch _SW4 .
If SA is "1", the tempo data from the manual setting circuit 136 is selectively transmitted, and if the selection signal SB is "1", the tempo data from the register circuit 140 is selectively transmitted.

Tempo data from selector circuit 138 is supplied as input B to arithmetic circuit 142. The arithmetic circuit 142 performs the following S1 to S5 based on inputs A and B.
Generates an output signal as shown in selector circuit 1.
44.

S1=B S2=A+3B/4 S3=A+B/2 S4=3A+B/4 S5=A The selector circuit 144 is connected to the P from the priority circuit 146.
One of the output signals S1 to S5 from the arithmetic circuit 142 is selected and sent out according to the selection signal supplied preferentially in the order of 1, P2, P3, P4, and P5, and the start signal ΔSTRT Before the generation of the performance mode signal = "0", the signal = "1" is inverted by the inverter 148 and is supplied as the selection signal P1 via the OR gate 150 and the priority circuit 146, so that the output signal S1 of the arithmetic circuit 142 (tempo data corresponding to the reference tempo) is selected and supplied to the gate circuit 152.

Gate circuit 152 is R-S flip-flop 1
The conduction or non-conduction is controlled by the output signal of the inverter 156 which receives the output Q of the flip-flop 154 as input, and the play mode signal PLAY resets the flip-flop 154 via the inverter 158 before the start signal ΔSTRT is generated. Therefore, the gate circuit 152 is in a conductive state. Therefore, the tempo data corresponding to the reference tempo from the selector circuit 144 is sent to the gate circuit 152 and the OR circuit 157.
It is supplied as the other comparison input B to the comparison circuit 134 via the comparison circuit 134.

Comparison circuit 134 compares comparison inputs A and B, and when they match, generates a match signal EQ. This match signal EQ causes the counter 132 to be reset via the D-flip-flop 160, so that the counter 132 again counts the second clock signal φ2 after being reset. Thereafter, the same operation is repeated, and the comparison circuit 134 repeatedly generates the coincidence signal EQ at a period corresponding to the reference tempo.

Inverter 1 before the start signal ΔSTRT is generated.
Since the output signal of the NAND gate 162 is "0" and the performance mode signal PLAY is also "0", the output signal of the NAND gate 164 is "1", and the AND gate 166 outputs the output signal of the NAND gate 164 = "1". ”
It is electrically conductive. Therefore, the comparison circuit 134
The coincidence signal EQ repeatedly generated from EQ is sent through an AND gate 166 as a tempo clock signal TCL. Tempo clock signal at this time
Since the TCL has a frequency corresponding to the standard tempo indicated by the tempo data from the manual setting circuit 136 or the register circuit 140, the automatic rhythm sound described above is generated at a tempo corresponding to the standard tempo.

Next, when the start signal ΔSTRT is generated,
In response to this signal ΔSTRT, the tempo data from the selector circuit 138 is transferred to the latch circuits 168 and 170.
It is preset as preset data PS. Therefore, the averaging circuit 172
The tempo data from 68 and 170 are received as inputs A and B, respectively, subjected to an averaging process of (A+B)/2, and supplied as input A to the arithmetic circuit 142. Furthermore, since the performance mode signal PLAY becomes "1" in response to the start signal ΔSTRT, the output signal of the inverter 148 becomes "0", allowing the selector circuit 144 to perform a selection operation based on the output data of the selector circuit 174.

The manual setting circuit 176 is for manually setting the tempo following degree as appropriate, and supplies 5-bit tempo following degree designation data corresponding to the set tempo following degree to the selector circuit 174 as input A. Further, a ROM (read-only memory) 178 stores multiple sets of tempo following degree designation data having different temporal change patterns of the tempo following degree. When you select whether to read data, the counter 180 starts the start signal Δ
Key-on signal after being reset by STRT
Every time KON is counted, a selected set of 5-bit tempo followability designation data is read from the ROM 178 and supplied as input B to the selector circuit 174. If the selection signal SA is "1" based on the operation of the select switch SW ₅ , the selector circuit 174 selectively sends out the tempo follow-up degree designation data from the manual setting circuit 176, and if the selection signal SB is "1", the ROM 178 Selectively sends the tempo following degree specification data from .

When all bits of the output data from the selector circuit 174 are "0", the NOR gate 182 detects the state of all bits "0" and outputs the output signal =
“1” is passed through the OR gate 150 to the priority circuit 146
is supplied as the selection signal P1. Therefore, the selector circuit 144 outputs the output signal S1 of the arithmetic circuit 142.
(tempo data corresponding to the standard tempo) is selectively transmitted. Further, when the selection signal P2, P3, P4 or P5 becomes "1" according to the output data of the selector circuit 174, the output signal S2 of the arithmetic circuit 142,
Tempo data corresponding to S3, S4, or S5 is sent from the selector circuit 144. As a result, the manual setting circuit 176 can change the degree of tempo followability arbitrarily or change the degree of tempo followability over time using data read from the ROM 178, and the manual setting circuit 176 can also select the temporal change pattern of the degree of tempo followability. It becomes possible.

When the operation mode signal PLAY becomes "1", the output signal of the inverter 158 becomes "0", so that the flip-flop 154 is released from reset. However, since flip-flop 154 is not set until the first key-on signal KON is generated, gate circuit 152
It continues to be conductive until it is set. Also,
Even if the performance mode signal PLAY becomes "1", the output signal of the inverter 162 becomes "1".
Since the output signal of NAND gate 164 does not become "0", AND gate 166
The signal TCL continues to be sent until the output signal of No. 4 becomes "0".

By the way, when the performance mode signal PLAY becomes "1", this signal resets and cancels the counter 188 via the inverter 184 and the OR gate 186. Therefore, the counter 188 counts the tempo clock signal TCL and supplies the count output to the comparison circuit 190 as one comparison input A. As the other comparison input B of the comparison circuit 190, a melody note length code signal MLG corresponding to the first melody note is supplied. Comparison circuit 190 compares comparison inputs A and B, and while A<B, output signal = "1" is supplied to inverter 162 and AND gate 192, and when A = B, output signal = "1".
“1” is connected to OR gate 130 and AND gate 19
4, 196 and 198, and the R-S flip-flop 200. Note that when the output signal corresponding to A=B becomes "1", the output signal corresponding to A<B becomes "0", the output signal of the NAND gate 164 becomes "0", and the output signal from the AND gate 166 becomes "0". Prohibits transmission of tempo clock signal TCL.

The time point at which the comparison circuit 190 generates the output signal corresponding to A=B corresponds to the time point at which the key corresponding to the second melody tone should be pressed. At almost the same time that the first melody note length code signal MLG is supplied to the comparison circuit 190, the comparison circuit 202 is supplied with a melody key code signal MKC corresponding to the second melody tone as one comparison input A. If it is assumed that a key corresponding to the second melody tone is pressed at the time when the comparison circuit 190 generates an output signal corresponding to A=B, a key code signal KKC based on the pressed key is sent to the comparison circuit 202. It is supplied as the other comparison input B. Therefore, the comparison circuit 202 compares comparison inputs A and B and generates a match signal EQ if the key codes match.
This coincidence signal EQ is an any key on signal from the OR gate 204 which receives the key code signal KKC as input.
The differential circuit 2
10. The differentiating circuit 210 differentiates the input signal at this time to generate the first key-on signal.
KON is generated, and this key-on signal KON is further passed through an AND gate 198 which is made conductive by the output signal corresponding to A=B from the comparator circuit 190.
The first read control signal via OR gate 212
Sent as NEXT. This first read control signal NEXT is sent to counter 1 through OR gate 186.
Since the counter 188 is reset, the counter 188 again counts the tempo clock signal TCL after the reset.

Note that when the melody key code MKC corresponds to a rest, the rest detection circuit 214 generates a rest detection signal and makes the AND gate 194 conductive. Then, when an output signal corresponding to A=B is generated from the comparator circuit 190, this output signal is
via AND gate 194 and further OR gate 20
8 to the differentiating circuit 210, the key-on signal KON and read control signal NEXT are generated in the same manner as described above.

On the other hand, the second
The clock signal φ2 is supplied to the variable frequency divider circuit 216, and is frequency-divided by a frequency division ratio corresponding to the note length indicated by the first melody note length code signal MLG. The frequency divided output signal from the variable frequency dividing circuit 216 is sent to the inverter 21.
The output signal of 8 is supplied to the counter 222 via the AND gate 220 which is conductive due to the output signal being “1”.
It is counted. The variable frequency divider circuit 216 is the counter 22
This is provided to ensure that the count value of 2 is approximately equal for all notes, and is configured such that the longer the note, the larger the frequency division ratio. The counter 222 is reset by the first read control signal NEXT, and the count data immediately before the reset is latched in the latch circuit 168 in response to the first key-on signal KON. At the same time, the preset data latched in the latch circuit 168 is transferred to the latch circuit 1 in response to the first key-on signal KON.
70 and latched there. Therefore, the averaging circuit 172 supplies output data obtained by averaging the count data of the latch circuit 168 and the preset data of the latch circuit 170 to the arithmetic circuit 142. In this case, the timing of the key press corresponding to the second melody note almost coincides with the end of the duration (note length) of the first melody note, so
The tempo value indicated by the output data of the averaging circuit 172 is unchanged from the previous one (corresponding to the reference tempo).

The arithmetic circuit 142 supplies the aforementioned output signals S1 to S5 to the selector circuit 144 based on the new output data from the averaging circuit 172. The selector circuit 144 is the priority circuit 14 as described above.
According to one of the selection signals P1 to P5 generated from 6, a corresponding signal from S1 to S5 is selected and supplied to gate circuit 152 and latch circuit 224. At this time, the gate circuit 152 is non-conductive because the flip-flop 154 is set by the first key-on signal KON, but the latch circuit 224 latches the tempo data from the selector circuit 144 in response to the first key-on signal KON. , is supplied as comparison input B to the comparison circuit 134 via the OR circuit 157.

Therefore, the comparison circuit 134 is connected to the selector circuit 14.
Match signal based on the tempo data selected in step 4.
Generates EQ repeatedly and uses the tempo clock signal TCL
The frequency corresponds to the tempo indicated by the tempo data selected by the selector circuit 144. For example, if the selection signal SA="1" is generated by the switch SW ₅ and the tempo following degree designation data corresponding to the selection signal P4 is generated from the manual setting circuit 176, the selector circuit 144 Since the output signal S4=(3A+B)/4 is selected, the frequency of the tempo clock signal TCL changes from the one corresponding to the previous S1=B to the one corresponding to S4. Also, select signal SB with switch SW ₅ .
= “1”, and in response to the counter 180 counting the first key-on signal KON, the ROM 178
Assuming that the tempo tracking degree designation data corresponding to the selection signal S2 is read from the selector circuit 1
44 is the output signal S2=(A+
3B)/4, the tempo clock signal
The frequency of TCL changes from that previously corresponding to S1=B to that corresponding to S2.

The above is the operation in the case of a coincident key press, where the timing of the key press corresponding to the second melody note almost coincides with the end of the duration (note length) of the first melody note. The operation when the timing is early or late is as follows.

First, in the case of a quick key press, the first key-on signal KON causes the flip-flop 124 to be set via the AND gate 192 which is rendered conductive by the output signal from the comparison circuit 190 corresponding to A<B = "1". Therefore, the selector circuit 122 outputs the low-speed second clock signal φ in response to the selection signal SA consisting of the output Q=“1” of the flip-flop 124.
2, the high-speed first clock signal φ1 is selected and supplied to the counter 132 and the variable frequency divider circuit 216. Therefore, the counting speed of the counter 132 increases, the frequency of the tempo clock signal TCL increases, and accordingly, the counting speed of the counter 188 also increases. Also, since the first key-on signal KON sets the flip-flop 200, the output Q="1" of the flip-flop 200 is passed through the D-flip-flop 226 to the AND gate 19.
6 becomes conductive. After this, the comparator circuit 190 determines that A=
When the output signal ="1" corresponding to B is generated, this output signal ="1" is output from the AND gate 196 and the OR gate 196.
The first read control signal NEXT via gate 212
Sent as . Note that the output signal ="1" from the comparison circuit 190 corresponding to A=B resets the flip-flop 200.

The first read control signal NEXT resets the counter 222, but immediately before the reset, the count data of the counter 222 is latched into the latch circuit 168 in response to the first key-on signal KON, as described above. At this time, the count data latched by the latch circuit 168 indicates a smaller count value than in the case of coincident key presses, so the output data from the averaging circuit 172 also indicates a tempo slightly faster than the reference tempo. Then, the output data from the averaging circuit 172 is transferred to the arithmetic circuit 142 and the selector circuit 144.
In the process of passing through the latch circuit 224, the tempo data is converted into tempo data having a tempo tracking degree corresponding to the output data of the selector circuit 174.
The signal is supplied to the comparison circuit 134 via. Therefore, the frequency of the tempo clock signal TCL is controlled to change so that the tempo of the automatic performance follows the tempo of the manual performance and becomes faster at the specified tempo following degree.

Next, in the case of a slow key press, when the comparison circuit 190 generates an output signal = "1" corresponding to A=B, the low speed second clock signal φ is generated as described above.
The tempo clock signal that was generated based on 2.
TCL is prohibited from being sent out through AND gate 166, and counter 188 accordingly stops counting. After this, the first key-on signal
When KON is generated, this signal KON is the output signal from the comparison circuit 190 corresponding to A=B=“1”
Through the AND gate 198 which is conductive by
Furthermore, it is sent out via OR gate 212 as the first read control signal NEXT. This read control signal
NEXT resets the counter 222, and the count data immediately before the reset is latched in the latch circuit 168 in response to the first key-on signal KON. At this time, the count data latched by the latch circuit 168 shows a larger count value than in the case of coincident key presses, so the output data from the averaging circuit 172 also comes to show a tempo slightly slower than the reference tempo. The output data from the averaging circuit 172 passes through the arithmetic circuit 142 and the selector circuit 144 and is converted into tempo data having a degree of tempo tracking corresponding to the output data of the selector circuit 174. The signal is supplied to the comparison circuit 134 via. Therefore, the frequency of the tempo clock signal TCL is controlled to change so that the tempo of the automatic performance follows the tempo of the manual performance and is slowed down at the specified tempo following degree.

Note that the count value of the counter 222 is the average value of the averaging circuit 1.
If no key is pressed even after reaching 1.25 times the average value indicated by the output data of counter 22,
The count data from 2 is used as one comparison input A, and the output data from the multiplication circuit 228 that multiplies the output data of the averaging circuit 172 by 1.25 is used as the other comparison input B.
A comparison circuit 230 with both comparison inputs A and B
When they match, a match signal EQ is generated. Since the coincidence signal EQ makes the AND gate 220 non-conductive via the inverter 218, the count value of the counter 222 never becomes larger than 1.25 times the average value indicated by the output data of the averaging circuit 172.

The operation described above regarding the key pressed corresponding to the second melody tone is performed in the same manner for each of the third and subsequent keys. In the course of such an operation, if the selection signal SA="1" is generated by the selection switch SW ₅ , the tempo tracking degree can be arbitrarily set variably by the manual setting circuit 176. If the selection signal SB="1" is generated by switch _SW5 , ROM1
The tempo following degree is automatically changed and controlled based on the data read from the 78, and the temporal change pattern of the tempo following degree is controlled by the manual setting circuit 176.
can be selected as appropriate. In the above embodiment, since the averaging circuit 172 is provided to average the manual performance tempo data, even if the output signal S5 of the arithmetic circuit 142 is selected, the tempo of the automatic performance is different from the tempo of the manual performance. can be prevented from following too closely.

As described above, according to the present invention, the degree of follow-up of the tempo of automatic performance to the tempo of manual performance is variably controlled. Depending on whether the music to be played is easy or difficult, the optimal degree of follow-up can be selected and performed.
Also, the degree of follow-up can be changed over time, so for example, you can set the degree of follow-up to a small value at the beginning of a performance, and then increase it as you get used to the performance. It is possible to perform by increasing the degree of follow-up and decreasing the degree of follow-up in areas where it is difficult to play. Furthermore, you can predetermine the temporal change pattern of the tempo tracking degree or select any one from among multiple change patterns.
As a performer, this is very convenient in terms of operating procedures.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an electronic musical instrument according to an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing the formats of melody data and performance data, respectively, and FIGS. FIG. 5, which is a diagram for explaining display and performance operations, is a detailed circuit diagram of the tempo control circuit of the electronic musical instrument. 10... Musical score, 10a... Recording medium, 12...
Score data reading control circuit, 13...Tempo control circuit, 14...Melody data memory, 22...Start/stop control circuit, 24...Melody data reading circuit, 44...Display section, 50...Keyboard,
136...Reference tempo manual setting circuit, 140
...Reference tempo data register circuit, 142...
Arithmetic circuit, 176... Tempo follow-up degree manual setting circuit, 178... Tempo follow-up degree specification data generation
ROM.

Claims (1)

[Scope of Claims] 1. A keyboard, a musical tone generating means for generating a musical tone corresponding to a key pressed on the keyboard, a tempo clock generating means for generating a tempo clock signal, and a musical tone generating means for automatically generating or generating a musical tone based on the tempo clock signal. In an electronic musical instrument, the electronic musical instrument is equipped with an automatic performance means for displaying key presses, and a data generation means for generating tempo following degree designation data, and a data generation means for generating tempo following degree designation data and a key press signal from the keyboard based on the automatic performance means. An electronic musical instrument comprising: a control circuit for controlling the frequency of the tempo clock signal so that the tempo of automatic performance follows the tempo of manual performance using the keyboard. 2. In the electronic musical instrument according to claim 1, the data generating means is configured to generate tempo following degree designation data corresponding to the set tempo following degree each time the tempo following degree is manually set. An electronic musical instrument characterized by: 3. In the electronic musical instrument according to claim 1, the data generation means includes a storage device that stores tempo tracking degree designation data corresponding to different tempo tracking degrees, and a tempo tracking degree stored from this storage device. What is claimed is: 1. An electronic musical instrument comprising: readout means for sequentially reading out the degree designation data. 4. In the electronic musical instrument according to claim 3, the storage device stores a plurality of sets of tempo following degree designation data having different temporal change patterns of the tempo following degree, and the reading means 1. An electronic musical instrument characterized in that the electronic musical instrument is configured such that a set of tempo following degree designation data can be read out or selected by manual operation.