JPS6412389B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an electronic musical instrument equipped with an automatic performance device, and aims to improve practice efficiency by preventing automatic performance from proceeding further when no keys are pressed on the keyboard for a certain period of time. It is something.

2. Description of the Related Art Hitherto, electronic musical instruments have been known that automatically generate musical tones or display keys pressed to assist manual performance using a keyboard.

However, with such electronic musical instruments, even if the practitioner becomes confused and stops pressing the keys, the automatic performance will continue automatically, and the practitioner must wait for the automatic performance to end and practice from the beginning again. Therefore, it was difficult to achieve sufficient practice results in a short period of time.

Therefore, an object of the present invention is to provide an electronic musical instrument with high practice efficiency.

The electronic musical instrument according to the present invention is characterized in that the automatic performance is prevented from proceeding further by detecting that no keys are pressed for a certain period of time on the keyboard. Describe.

FIG. 1 shows an electronic musical instrument equipped with an automatic performance device according to an embodiment of the present invention.

A recording medium 10a such as a magnetic tape is attached to the lower margin of the musical score 10, and the recording medium 10a
Musical score data corresponding to the musical score content is recorded.

The musical score data reading control circuit 12 is connected to the recording medium 10a.
The system reads the musical score data from the melody data memory 14 and the accompaniment data from the melody data memory 14 and the accompaniment data memory 16 and stores them therein. In order to control such transfer and storage operations, a write address signal is used. WAD, write command signals WT ₁ and WT ₂ , address selection signals AS ₁ and
It is set to send AS ₂ . Both memories 14 and 16 are RAM (Random Access RAM).
memory), and address signals are supplied from corresponding selector circuits 18 and 20. The selector circuits 18 and 20 perform selection operations according to the address selection signals AS ₁ and AS ₂ , respectively, and the selector circuit 18 operates according to the selection signal AS 1 and AS 2, respectively.
If AS ₁ is "1", control input SA is "1" and input A is selected, and if selection signal AS ₁ is "0", control input SB is "1" and input B is selected by inverter 18a.
Select. The selector circuit 20 also receives a selection signal.
If AS ₂ is "1", control input SA is "1" and input A is selected, and if selection signal AS ₂ is "0", control input SB is "1" and input B is selected by inverter 20a.
Select.

When the musical score 10 is inserted into the receiving port of the data reader included in the musical score data reading control circuit 12 and the data reading operation is started, the memory 14 enters the write mode in response to the write command signal _WT1 , and the memory 14 is supplied with a write address signal WAD from a selector circuit 18 which is in a state of selecting input A in response to selection signal _AS1 . For this reason, the memory 14
Melody data corresponding to the melody progression of the musical score 10 is written in the format shown in FIG. 2. That is, the melody data written at this time expresses the melody tones to be generated by a combination of an 8-bit key code KC and an 8-bit length code LNG, and corresponds to several melody tones selected in advance. The key tone code KT consisting of "11000000" is included immediately before the key code KC. Each key code KC is pitch name C ₃
As shown in the example above, the upper 2 bits are the identification code, the lower 2 bits are the octave code, and the remaining 4 bits are the identification code.
The bits are a note code, and each length code LNG has the upper two bits as an identification code and the remaining six bits as a note length code, as illustrated for an eighth note. Rests are key codes
It is expressed by setting all 6 bits other than the KC identification code bit to "0". After writing the last melody data, an end code FNS in which all 8 bits are "1" is written into the memory 14. Note that the key tone code KT is attached to specify the return position of automatic performance, and from this point of view, for example, the note at the beginning of each bar or plural bars is selected as the key tone.

After writing the end code FNS, memory 1
6 enters the write mode in response to the write command signal WT ₂ , and the memory 16 enters the input A in response to the selection signal AS ₂ .
A write address signal WAD is supplied from the selector circuit 20 which is in a state of selecting. For this reason,
Accompaniment data corresponding to the progression of accompaniment (chords or bass notes) of the musical score 10 is written in the memory 16 in a format as shown in FIG. In other words, the accompaniment data written at this time uses an 8-bit key code KC and an 8-bit length code to represent the chord to be generated.
It is expressed in combination with LNG, and like the melody data, it includes the keytone code KT. For each key code KC, as shown in the example for C major (CM), the upper two bits are the identification code, the lower two bits are the chord type code,
The remaining 4 bits are the root chord. Here, the chord type code is "00" for major, "01" for minor, and "10" for seventh. In addition, each length code in the accompaniment data
LNG is the top 2 as shown in the example for a half note.
The bit is an identification code, and the remaining 6 bits are a note length code.

After the series of data reading/writing operations as described above, the start switch _SW0 of the start/stop control circuit 22 is turned on to operate the melody data reading circuit 24 and the accompaniment data reading circuit 26. That is, when the start switch _SW0 is turned on, the on signal is differentiated by the differentiating circuit 28 in synchronization with the system clock signal φ and is converted into the start signal ΔSTRT. Then, the start signal .DELTA.STRT sets the R-S flip-flop 30, so that the flip-flop 30 sends out a performance mode signal PLY consisting of its output Q="1". At this time, since the input signal of the inverter 32 is "0", the output signal of the inverter 32 = "1" is passed through the OR gate 34 to the AND gate 3.
6. Therefore, AND gate 3
6 becomes conductive when the performance mode signal PLAY="1" is generated, and sends the clock signal φ to the address counter 3.
8.

Address counter 38 receives start signal ΔSTRT
When reset by , the read address signal RAD ₁ corresponding to the first read address is supplied to the selector circuit 18 as input B. At this time, the selector circuit 18 receives the input B by the selection signal AS ₁ =“0”.
, and supplies the read address signal RAD ₁ corresponding to the first read address to the memory 14. Therefore, the first key tone code data is read from the memory 14 and supplied to the identification code detection circuit 40. The identification code detection circuit 40 detects the first key tone code and supplies the key tone code detection signal KTM to the latch circuit 41 as the load signal L, so the latch circuit 41 detects the first key tone code from the counter 38 in response to the load signal L at this time. The address signal RAD ₁ corresponding to the first read address is latched.

Next, when the counter 38 counts the clock signal φ from the AND gate 36 by 1, the memory 14
The key code data corresponding to the first melody sound is read out, the upper 2 bits of which are sent to the identification code detection circuit 40, and the remaining 6 bits of the melody key code (octave code and note code) signal are sent to the clock. Each of the signals is supplied to a latch circuit 42 timed by a signal φ.

The identification code detection circuit 40 generates a key code detection signal MK in response to the first key code data from the memory 14, and the latch circuit 42 latches the first melody key code signal in response to this key code detection signal MK. The melody key code signal MKC from the latch circuit 42 is transmitted to the display section 44.
supplied to

The display section 44 is provided with a display control circuit 46 which receives the melody key code signal MKC as an input, and this display control circuit 46 receives the output of the display select switch _SW1 from the AND gate 48 which is conductive in response to the performance mode signal PLAY. When the enable signal EN is supplied in response to the input, the light emitting elements in the light emitting element group 52 provided along the key arrangement of the keyboard 50 are selectively controlled to light up to visually display the key to be pressed. It's summery. Therefore, if the first melody key code signal MKC indicates the note name C ₃ as in the example shown in FIG. 2, the light emitting element corresponding to the C ₃ key lights up to instruct the key to be pressed.

After the key press display corresponding to the first melody tone has started as described above, when the counter 38 counts the next clock signal φ, the length corresponding to the first melody tone is stored from the memory 14 in the same manner as before. Code data is read. Of the read data at this time, the upper 2-bit identification code signal is supplied to the identification code detection circuit 40, and the remaining 6-bit melody code length code is supplied to the latch circuit 54, which is timed by the clock signal φ. be done. Then, the identification code detection circuit 40 outputs a length code detection signal according to the first length code data from the memory 14.
ML, the latch circuit 54 converts the first melody note length code signal into the length code detection signal ML.
Latch accordingly. Also, since the length code detection signal ML at this time is supplied to the inverter 32, the output signal of the inverter 32 becomes "0",
As a result, the counting operation of the counter 38 is temporarily stopped.

Thereafter, at a time delayed by approximately 3 bit times of the clock signal φ from the generation of the start signal ΔSTRT, a three-stage D-flip-flop 56 receives the start signal ΔSTRT from the OR gate 55 and is timed by the clock signal φ. generates a delayed signal ΔDPLS. This delayed signal ΔDPLS is OR
Since AND gate 36 is made conductive via gate 34, counter 38 again counts the clock signal φ from AND gate 36. Therefore, the key code data and length code data corresponding to the second melody tone are sequentially read out from the memory 14, and in response to this, the identification code detection circuit 40 outputs the key code detection signal MK and the length code detection signal MK.
Generate ML sequentially. The key code detection signal MK at this time causes the latch circuit 42 to transfer the first melody key code signal to a similar latch circuit 58, and also causes the latch circuit 42 to latch the second melody key code signal. Also, the length code detection signal ML at this time is the latch circuit 54.
Then, the first melody note length code signal is transferred to the same latch circuit 60, and the second melody note length code signal is transferred to the latch circuit 54, and the counting operation of the counter 38 is performed via the inverter 32 as before. temporarily stop.

The melody key code signal MKC corresponding to the second melody tone from the latch circuit 42 is displayed on the display section 4.
Since the second melody tone is supplied to the second melody tone, the display section 44 displays the key depression corresponding to the second melody tone, as in the previous case. Also, at this time, a melody key code signal corresponding to the first melody tone is output from the latch circuit 58.
Since MKC' is supplied to the automatic melody sound signal forming circuit 62, this circuit 62 receives the performance mode signal.
When the enable signal EN is supplied from the AND gate 64 which is conductive in PLAY in response to the turning on of the sound generation select switch SW ₂ , a melody sound signal is electronically synthesized according to the melody key code signal MKC' and output. The signal is supplied to a speaker 68 via an amplifier 66. Therefore, the first automatic melody sound is played from the speaker 68 with a delay of one tone relative to the key press display.

On the other hand, the melody note length code signal MLG corresponding to the first melody note from the latch circuit 60 is supplied to the comparison circuit 72 as one comparison input, and the other comparison input of the comparison circuit 72 is the count output from the tempo counter 74. K ₁ is supplied. here,
Since the tempo counter 74 is reset in response to the start signal ΔSTRT from the OR gate 76 and then counts the tempo clock signal TCL supplied from the tempo oscillation circuit 78 via the AND gate 79, the comparison circuit 72 counter 7
The count value of 4 is the first melody note length code signal
When the value corresponding to the note length indicated by MLG is reached, a matching signal EQ is generated.

Since the match signal EQ at this time resets the counter 74 via the OR gate 76, the counter 74 resets the tempo clock signal again after being reset.
Count TCL. Further, the coincidence signal EQ is passed from the AND gate 80 which is turned on by the length code detection signal ML to the AND gate 36 via the OR gate 34.
, the counter 38 resumes counting the clock signal φ from the AND gate 36. Therefore, the key code data and length code data corresponding to the third melody tone are sequentially read out from the memory 14, and the latch circuits 58 and 42 receive the second melody key code signal and the third melody key code signal, respectively.
The second melody key code signal is latched, and the second melody key length code signal and the third melody key length code signal are latched in the latch circuits 60 and 54, respectively. Therefore, the automatic melody sound signal forming circuit 62 forms a melody sound signal corresponding to the second melody sound, the display section 44 displays a key press corresponding to the third melody sound, and the comparison circuit 72 produces a melody sound signal corresponding to the second melody sound. The note lengths of the melody tones are measured. Then, the above-mentioned operations are repeated in the same manner, thereby performing an automatic key press display based on the data stored in the memory 14 and an automatic performance of a melody tone delayed by one note with respect to this display.

Note that the end code data is finally read out from the memory 14, and in response to this, the identification code detection circuit 40 generates the end code detection signal FN. This end code detection signal FN is applied to the flip-flop 30.
As a result, the performance mode signal PLAY becomes "0" and a series of data reading from the memory 14 is completed.

The key switch circuit 82 includes a number of key switches respectively linked to a number of keys on the keyboard 50, and is adapted to supply a key press signal indicating the pressed key to the manual performance sound signal forming circuit 84.
The manual performance sound signal forming circuit 84 electronically synthesizes a melody sound signal corresponding to the pressed key in response to the key press signal from the key switch circuit 82, and supplies the synthesized melody sound signal to the speaker 68 via the output amplifier 66. Therefore, the speaker 68 also produces melody sounds by manual performance.

In this case, if manual performance practice is performed using the keyboard 50, it is possible to efficiently practice performance while listening to the above-mentioned automatic performance and/or while viewing the automatic key press display by the light emitting element group 52. When practicing this kind of performance,
Automatic accompaniment of chords or bass notes and/or automatic rhythm accompaniment as described below can also be used as appropriate.

In the accompaniment data reading circuit 26, since the input signal of the inverter 86 is "0" when the start switch SW ₀ is turned on, the output signal of the inverter 86 = "1" is ANDed through the OR gate 88.
It is supplied to the gate 90. Therefore, start switch SW ₀ is turned on and the performance mode signal is output.
When PLAY="1" is generated, AND gate 90
A clock signal φ is supplied from the address counter 92 to the address counter 92.

Address counter 92 receives start signal ΔSTRT
When reset by , the read address signal RAD ₂ corresponding to the first read address is supplied to the selector circuit 20 as input B. At this time, the selector circuit 20 receives the input B due to the selection signal AS ₂ =“0”.
, and supplies the read address signal RAD ₂ corresponding to the first read address to the accompaniment data memory 16. Therefore, the first key tone code data is read from the memory 16 and supplied to the identification code detection circuit 94. The identification code detection circuit 94 detects the first key tone code and outputs the key tone code detection signal KTM' to the latch circuit 95.
The latch circuit 95 latches the address signal RAD ₂ corresponding to the first read address from the counter 92 in response to the load signal L at this time. Furthermore, the key tone code detection signal KTM' at this time is also supplied to the latch circuit 97 as the load signal L, so the latch circuit 97 latches the count output of the autorhythm counter 99 according to the load signal L at this time. do. Here, the counter 99 is reset in response to the start signal ΔSTRT, and then reset to the tempo clock signal.
Since TCL is counted, the latch circuit 97 latches the count output corresponding to the count value 0 from the counter 99 when the first key tone code detection signal KTM' is generated.

Next, when the counter 92 counts the clock signal φ from the AND gate 90 by 1, the memory 16
The key code data corresponding to the first accompaniment note is read out, and the upper 2 bits of the identification code signal are sent to the identification code detection circuit 94, and the remaining 6 bits of the accompaniment key code (chord type code and root note code) signal are sent to the identification code detection circuit 94. are respectively supplied to a latch circuit 96 timed by a clock signal φ.

Identification code detection circuit 94 generates key code detection signal AK in response to the first key code data from memory 16, and latch circuit 96 latches the first accompaniment key code signal in response to this key code detection signal AK.

Thereafter, when the counter 92 counts the next clock signal φ, the length code data corresponding to the first accompaniment tone is read out from the memory 16 in the same manner as the previous time. Among the read data at this time, the identification code signal of the upper 2 bits is sent to the identification code detection circuit 94.
The remaining 6-bit accompaniment note length code signal is supplied to a latch circuit 98 timed by a clock signal φ. Then, since the identification code detection circuit 94 generates the length code detection signal AL in accordance with the first length code data from the memory 16, the latch circuit 98 generates the length code detection signal AL according to the first accompaniment note length code signal. Latch accordingly. Also, the length code detection signal AL at this time is the inverter 8.
6. Therefore, the output signal of the inverter 86 becomes "0", and the output signal of the inverter 86 becomes "0".
AND gate 90 is made non-conductive. Therefore, the counting operation of the counter 92 is temporarily stopped.

After this, the aforementioned delayed signal ΔDPLS makes the AND gate 90 conductive via the OR gate 88, so that
Counter 92 again counts the clock signal φ from AND gate 90. Therefore, the key code data and length code data corresponding to the second accompaniment tone are sequentially read out from the memory 16, and in response to this, the identification code detection circuit 94 outputs the key code detection signal AK and the length code detection signal AK. ALs occur sequentially. At this time, the key code detection signal AK is sent from the latch circuit 96 to a similar latch circuit 100.
transfers the first accompaniment key code signal and causes the latch circuit 96 to latch the second accompaniment key code signal. Also, the length detection signal at this time
AL causes the latch circuit 98 to transfer the first accompaniment note length code signal to the similar latch circuit 102, causes the latch circuit 98 to latch the second accompaniment note length code signal, and then transfers the accompaniment note length code signal via the inverter 86 as before. The counting operation of the counter 92 is temporarily stopped.

As a result of the above operations, the latch circuit 100 begins to send out the first accompaniment key code number AKC, and the latch circuit 102 comes to send out the first accompaniment note length code signal ALG. and,
This first accompaniment note length code signal ALG is supplied to a comparator circuit 104 and compared with the count output K ₂ of a tempo counter 106 . Here, the tempo counter 106 is configured to count the tempo clock signal TCL after being reset by the start signal ΔSTRT from the OR gate 108.
Comparison circuit 104 generates a coincidence signal EQ when the count value of counter 106 reaches a value corresponding to the note length indicated by the first accompaniment note length code signal ALG.

Since the match signal EQ at this time resets the counter 106 via the OR gate 108, the counter 106 counts the tempo clock signal TCL again after being reset. Further, since the coincidence signal EQ is supplied from the AND gate 110, which is turned on by the length code detection signal AL, to the AND gate 90 via the OR gate 88, the counter 92 restarts counting the clock signal φ from the AND gate 90. . Therefore, the key code data and length code data corresponding to the third accompaniment note are sequentially read out from the memory 16, and the latch circuits 100 and 96
2nd accompaniment key code signal and 3rd accompaniment key code signal respectively.
The second accompaniment key code signal is latched, and the second accompaniment note length code signal and the third accompaniment note length code signal are latched in the latch circuits 102 and 98, respectively. As a result, the latch circuit 100 outputs the second accompaniment key code signal AKC, the latch circuit 102 outputs the second accompaniment code length code signal ALG, and the comparison circuit 104 outputs the second accompaniment key code signal AKC. The note length measurement for the th accompaniment note is performed. The above-mentioned operations are repeated in the same manner, so that accompaniment data is successively read out from the memory 16, so that the accompaniment key code signal AKC is sent out from the latch circuit 100 one after another. In addition, memory 1
6 ends before the end data is read out from the memory 14, and the counter 92 increments at the same time as the counter 38 when the end data is read out from the memory 14 and the performance mode signal PLAY returns to "0". stop.

The accompaniment key code signal AKC sent out from the accompaniment data reading circuit 26 as described above is supplied to the automatic accompaniment tone signal forming circuit 112. The automatic accompaniment sound signal forming circuit 112 generates an enable signal EN from the AND gate 114 which is conductive in response to the performance mode signal PLAY in response to the turning on of the sound generation select switch _SW3 .
is supplied, the accompaniment key code signal AKC
The accompaniment tone signal is electronically synthesized based on the rhythm selection data (not shown), and the accompaniment tone signal includes a chord signal corresponding to a plurality of chord constituent notes, and a bass that matches the chord and rhythm to be generated. It is designed to generate sound signals. and,
The transmission timing of each accompaniment sound signal from the automatic accompaniment sound signal forming circuit 112 is controlled in conjunction with the rhythm according to the accompaniment timing signal AT from the rhythm pattern generation circuit 116 which receives the count output of the counter 99 as input. circuit 112
The accompaniment sound signal is supplied to a speaker 68 via an output amplifier 66. Therefore, automatic accompaniment sound is also produced from the speaker 68.

The rhythm pattern generation circuit 116 has a counter 99
The accompaniment timing signal mentioned above according to the counting output of
In addition to AT, a rhythm pattern signal RP is generated, and this rhythm pattern signal RP is supplied to the rhythm sound source circuit 118. The rhythm sound source circuit 118 generates a rhythm sound signal by driving an appropriate rhythm sound source according to the rhythm pattern signal RP, and supplies this rhythm sound signal to the speaker 68 via the output amplifier 66. Therefore, the automatic rhythm sound is also produced from the speaker 68.

The above is an operation when the melody keys on the keyboard 50 are pressed smoothly for each note in almost synchronization with the automatic melody performance. If you do not press a key, the automatic performance of the melody and accompaniment (chords, bass, and rhythm) and the automatic key press display will be temporarily stopped, and the display will return to the first note (key tone) of the phrase to which the note you did not press belongs. Automatic performance and automatic key press display will resume. Here, a phrase refers to an automatic performance section from a certain key tone to the note immediately before the next key tone.

Next, the first phrase will be explained as a representative example of the operation in such a case. Memories 14 and 1
When the key tone code data corresponding to the first key tone from 6 is read out, the latch circuit 41 sends the address signal RAD 1 corresponding to the first read address, and the latch circuit 95 sends the address signal RAD ₁ to the first read address, as described above. The latch circuit 97 latches the corresponding address signal RAD ₂ and the count output corresponding to the count value 0 from the counter 99, and thereafter automatic performance and automatic key depression display proceed. Here, it is assumed that the first phrase corresponds to the first and second bars, and that the practitioner was unable to press the key corresponding to the first note of the second bar.

The counter 120 counts the tempo clock signal TCL after being reset by the start signal ΔSTRT from the OR gate 122, and the OR gate 124 generates the any key-on signal AKO in response to the key press signal from the key switch circuit 82. It is designed to be reset by this signal AKO every time. Therefore, the counter 120
After being reset by the key pressed corresponding to the last note of the measure, the tempo clock signal TCL is being counted and even if the key corresponding to the first note of the second measure should be pressed, the key will not be pressed for a certain period of time. If the count output of the counter 120 is not inputted,
AND gate 126 generates an output signal=“1”. This output signal = “1” is the OR gate 128
Since the R-S flip-flop 130, which had been reset by the start signal ΔSTRT, is set via the start signal ΔSTRT, the output Q of the flip-flop 130
becomes “1”. This output Q="1" makes AND gate 79 non-conductive via inverter 132. Therefore, the transmission of the tempo clock signal TCL from the AND gate 79 is prohibited.

Also, the output Q of the flip-flop 130 is “1”
is supplied to the differentiating circuit 134, and is differentiated at the rising edge in synchronization with the clock signal φ, thereby being converted into the stop signal ΔPAUS. This stop signal ΔPAUS sends an address signal RAD ₁ corresponding to the first read address from the latch circuit 41 to the counter 38, an address signal RAD 2 corresponding to the first read address from the latch circuit 95 to the counter 92, and an address signal RAD ₂ corresponding to the first read address from the latch circuit 95 to the counter 38. 99
In addition to presetting the count data corresponding to the count value 0 from the latch circuit 97,
Tempo counter 74 is reset through OR gate 76 and tempo counter 106 is reset through OR gate 108. The counters 38 and 92 then receive the aforementioned start signal ΔSTRT.
The first key tone code data is read out from the memories 14 and 16 in accordance with the preset in the same way as at the time of generation, and in response, the latch circuits 41 and 95 receive an address signal corresponding to the first read address.
RAD ₁ and RAD ₂ are each latched. Also,
A count output corresponding to a count value of 0 is latched in the latch circuit 97 in accordance with the preset of the counter 99.

Next, when the counters 38 and 92 each count the clock signal φ by 2, data corresponding to the first melody tone is latched in the latch circuits 42 and 54, and data corresponding to the first accompaniment tone is latched in the latch circuits 96 and 98. The data is latched.
Then, the three-stage D-flip-flop 56 is OR
When the delay signal ΔDPLS is generated by delaying the stop signal ΔPAUS from the gate 55 by 3 bit times of the clock signal φ, data corresponding to the first melody tone is latched into the latch circuits 58 and 60 in the same way as described above. The circuits 42 and 54 contain data corresponding to the second melody note, the latch circuits 100 and 102 contain data corresponding to the first accompaniment note, and the latch circuits 96 and 98 contain data corresponding to the second accompaniment note. are each latched.

After the automatic performance and automatic key press display are temporarily stopped in this state, when you press any key on the keyboard 50, the OR gate 124 outputs the any key on signal AKO.
This signal AKO causes the counter 120 to be reset via the OR gate 122. At this time, the D-flip-flop 136, which is timed by the clock signal φ, outputs the output Q of the flip-flop 130.
="1" is supplied to AND gate 138 to make it conductive, so that any key-on signal AKO from OR gate 124 passes through AND gate 138 and further via OR gate 128 to reset flip-flop 130. Therefore, the output Q of flip-flop 130 becomes "0" and the output signal of inverter 132 becomes "1". Therefore, the tempo clock signal is output from the AND gate 79.
TCL is sent, and automatic performance and automatic key press display are restarted.

The practitioner can resume the key press practice of the first phrase by referring to the automatic performance and/or automatic key press display resumed in this way. When the key press practice for the first phrase is completed, the latch circuits 41, 95 and 9 are activated at the beginning of the second phrase.
The contents of latch 7 are updated to correspond to the second keyton code. Here, if a key corresponding to a certain note belonging to the second phrase is not pressed for a certain period of time, the automatic performance and automatic key press display will return to the first note (key tone) of the second phrase in the same way as described above. is restarted, and the same operation is performed for the third and subsequent phrases.

In the above embodiment, a keytone code is included in a series of performance data in order to make it possible to memorize the return address. It is also possible to instruct storage of the return address in response to the return address. In this case, 1
A phrase always corresponds to one bar. Further, when the automatic performance is stopped, the next phrase may be automatically performed as a model performance before returning and restarting the automatic performance. In this way, the performance assistance effect is further improved.

If the practitioner does not press a key for a certain period of time due to, for example, not knowing what to do, the data reading for automatic performance is stopped in response to the output of the detection means that detects the non-pressing of the key, and the data reading address is set to the key that is not pressed. Since the data readout is restarted after returning to the beginning of the performance section related to the detection, as a practitioner,
To prevent being left out of the automatic performance due to the automatic progression of the automatic performance, and to restart practice in accordance with the automatic performance from the beginning of the performance section without waiting for the end of the automatic performance of the performance section related to the detection of non-pressed keys. This enables efficient performance practice. In particular, if you become confused in the middle of a performance section, automatic performance will resume after returning several notes to the beginning of the performance section, making it very effective to understand the flow of the song. It is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an electronic musical instrument according to an embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing the formats of melody data and accompaniment data, respectively. 10... Musical score, 10a... Recording medium, 12...
Score data reading control circuit, 14... melody data memory, 22... start/stop control circuit, 24... melody data reading circuit, 44...
Display section, 50...keyboard, 62...automatic melody sound signal forming circuit, 84...manual performance sound signal forming circuit.

Claims (1)

[Scope of Claims] 1. A keyboard, first musical tone generation means for generating musical tones corresponding to key presses on the keyboard, a storage device for storing performance data regarding a plurality of sequential performance sections, and this storage device. a reading means for sequentially reading out the performance data from the keyboard, a second musical sound generation means for generating a musical sound corresponding to the performance data read by the reading means, and detecting that no key is pressed for a certain period of time on the keyboard. a detection means for generating a detection output in response to the detection output from the detection means, and in response to the detection output from the detection means, stopping data reading by the reading means and returning the data readout address to the beginning of the performance section related to the non-pressed key detection; An electronic musical instrument comprising readout control means for restarting data reading. 2. The electronic musical instrument according to claim 1, wherein the readout control means is configured to resume data readout in response to a key press being started on the keyboard after returning the data readout address. An electronic musical instrument characterized by: