JPH0132999B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument equipped with an automatic performance device, which automatically performs music by gradually increasing the frequency of a tempo clock signal when a key is pressed earlier than the key pressing timing indicated by musical score data. It is designed to gradually fast forward.

Conventionally, electronic musical instruments have been proposed in which the tempo of automatic performance is controlled based on musical score data read from a memory and key press signals from a keyboard.

However, in the case of such electronic musical instruments, if a key is pressed earlier than the key press timing indicated by the musical score data, the frequency of the tempo clock signal is changed stepwise from a certain value to a value several times higher, and the automatic performance is controlled. Because the tempo of the automatic performance suddenly becomes faster, the tempo of the automatic performance suddenly becomes faster, giving an unnatural feel.

An object of the present invention is to provide a new electronic musical instrument that does not give an unnatural feeling during fast-forwarding of automatic performance.

The electronic musical instrument according to the present invention is characterized in that the frequency of the tempo clock signal is controlled to gradually increase the frequency of the tempo clock signal in order to gradually fast-forward the automatic performance when a key is pressed quickly. Let us elaborate on an example.

FIG. 1 shows an electronic musical instrument equipped with an automatic performance device according to an embodiment of the present invention.

A recording medium 10a such as a magnetic tape is attached to the lower margin of the musical score 10, and the recording medium 10a
Musical score data corresponding to the musical score content is recorded.

The musical score data reading control circuit 12 is connected to the recording medium 10a.
The system reads the musical score data from the melody data memory 14 and the accompaniment data from the melody data memory 14 and the accompaniment data memory 16 and stores them therein. In order to control such transfer and storage operations, a write address signal is used. WAD, write command signals WT ₁ and WT ₂ , address selection signals AS ₁ and
It is set to send AS ₂ .

The memories 14 and 16 are both RAMs (random access memories), and are supplied with address signals from corresponding selector circuits 18 and 20. Selector circuit 18
and 20 are address selection signals AS ₁ and 20, respectively.
The selector circuit 18 performs a selection operation according to AS ₂ , and if the selection signal AS ₁ is “1”, the control input SA
is “1” and selects input A, and if selection signal AS ₁ is “0”, control input SB is selected by inverter 18a.
is “1” and input B is selected. Furthermore, if the selection signal AS ₂ is "1", the selector circuit 20 receives the control input.
If SA is "1" and input A is selected, and selection signal AS ₂ is "0", control input SB is selected by inverter 20a.
is “1” and input B is selected.

When the musical score 10 is inserted into the receiving port of the data reader included in the musical score data reading control circuit 12 and the data reading operation is started, the memory 14 enters the write mode in response to the write command signal _WT1 , and the memory 14 is supplied with a write address signal WAD from a selector circuit 18 which is in a state of selecting input A in response to selection signal _AS1 . For this reason, the memory 14
Melody data corresponding to the melody progression of the musical score 10 is written in the format shown in FIG. 2. That is, the melody data written at this time expresses the melody tones to be generated by a combination of an 8-bit key code KC and an 8-bit length code LNG, and each key code KC is expressed as an example for the note name _C3 . The upper 2 bits are the identification code,
The lower 2 bits are the octave code, the remaining 4 bits are the note code, and each length code is
LNG is the top 2 as shown in the example for an eighth note.
The bit is an identification code, and the remaining 6 bits are a note length code. Rests are key code KC
It is expressed by setting all 6 bits other than the identification code bit to "0". After writing the last melody data, an end code FNS in which all 8 bits are "1" is written into the memory 14. Note that the upper two bits of this end code FNS are also an identification code.

After writing the end code FNS, memory 1
6 enters the write mode in response to the write command signal WT ₂ , and the memory 16 enters the input A in response to the selection signal AS ₂ .
A write address signal WAD is supplied from the selector circuit 20 which is in a state of selecting. For this reason,
Accompaniment data corresponding to the progression of accompaniment (chords or bass notes) of the musical score 10 is written in the memory 16 in a format as shown in FIG. In other words, the accompaniment data written at this time uses an 8-bit key code KC and an 8-bit length code to represent the chord to be generated.
Expressed in combination with LNG, each key code KC has the upper two bits as an identification code, the lower two bits as a chord type code, and the remaining four bits as a root note code, as shown in the example for C _major (CM). It's summery. Here, the chord type code is "00" for major, "01" for minor, and "10" for seventh. Further, in each length code LNG in the accompaniment data, the upper two bits are an identification code, and the remaining six bits are a note length code, as illustrated for a half note.

After the series of data reading/writing operations as described above, the start switch _SW0 of the start/stop control circuit 22 is turned on to operate the melody data reading circuit 24 and the accompaniment data reading circuit 26.
In other words, when you turn on the start switch SW ₀ ,
The on signal is differentiated by the differentiating circuit 28 to rise in synchronization with the system clock signal φ, and is converted into the start signal ΔSTRT. The start signal .DELTA.STRT sets the RS flip-flop 30, so that the flip-flop 30 sends out a performance mode signal PLAY whose output Q is "1". At this time, since the input signal of the inverter 32 is "0", the output signal of the inverter 32 = "1" is passed through the OR gate 34 to the AND gate 3.
6. Therefore, AND gate 3
6 becomes conductive when the performance mode signal PLAY="1" is generated, and sends the clock signal φ to the address counter 3.
8.

Address counter 38 receives start signal ΔSTRT
When reset by , the read address signal RAD ₁ corresponding to the first read address is supplied to the selector circuit 18 as input B. At this time, the selector circuit 18 receives the input B by the selection signal AS ₁ =“0”.
, and supplies the read address signal RAD ₁ corresponding to the first read address to the memory 14. Therefore, the key code data corresponding to the first melody tone is read out from the memory 14, the upper 2 bits of which are sent to the identification code detection circuit 40, and the remaining 6 bits of the melody key code (octave code and note) are sent to the identification code detection circuit 40. The code signals are respectively applied to latch circuits 42 which are timed by the clock signal φ.

The identification code detection circuit 40 generates a key code detection signal MK in response to the first key code data from the memory 14, and the latch circuit 42 latches the first melody key code signal in response to this key code detection signal MK. The melody key code signal MKC from the latch circuit 42 is transmitted to the display section 44.
supplied to

The display section 44 is provided with a display control circuit 46 which receives the melody key code signal MKC as an input, and this display control circuit 46 receives the output of the display select switch _SW1 from the AND gate 48 which is conductive in response to the performance mode signal PLAY. When the enable signal EN is supplied in response to the input, the light emitting elements in the light emitting element group 52 provided along the key arrangement of the keyboard 50 are selectively controlled to light up to visually display the key to be pressed. It's summery. Therefore, if the first melody key code signal MKC indicates the note name C ₃ as in the example shown in FIG. 2, the light emitting element corresponding to the C ₃ key lights up to instruct the key to be pressed.

After the key press display corresponding to the first melody tone starts as described above, when the counter 38 counts the clock signal φ, the memory 14
Length code data corresponding to the first melody tone is read out from. Of the read data at this time, the upper 2 bits of the identification code signal are supplied to the identification code detection circuit 40, and the remaining 6 bits of the melody code length code signal are supplied to the latch circuit 54 which is timed by the clock signal φ. . Then, since the identification code detection circuit 40 generates the length code detection signal ML in accordance with the first length code data from the memory 14, the latch circuit 54 generates the length code detection signal ML according to the first length code data from the memory 14. Latch accordingly. Further, since the length code detection signal ML at this time is supplied to the inverter 32, the output signal of the inverter 32 becomes "0", thereby temporarily stopping the counting operation of the counter 38.

Thereafter, at a time delayed by about 2 bit times of the clock signal φ from the generation point of the start signal ΔSTRT, the two-stage D clock timed by the clock signal φ
- Flip-flop 56 generates restart signal ΔSTRT'. This restart signal ΔSTRT' makes the AND gate 36 conductive via the OR gate 34, so that the counter 38 starts again.
The clock signal φ from AND gate 36 is counted. Therefore, the key code data and length code data corresponding to the second melody tone are sequentially read out from the memory 14, and in response to this, the identification code detection circuit 40 outputs the key code detection signal MK and the length code detection signal MK. Generate ML sequentially. At this time, the key code detection signal MK causes the first melody key code signal to be transferred from the latch circuit 42 to a similar latch circuit 58, and the latch circuit 4
2 to latch the second melody key code signal. Also, the length code detection signal ML at this time
is a latch circuit 54 to a similar latch circuit 6.
0, the first melody code length code signal is transferred, the latch circuit 54 is made to latch the second melody code length code signal, and the counting operation of the counter 38 is temporarily stopped via the inverter 32 as in the previous case.

The melody key code signal MKC corresponding to the second melody tone from the latch circuit 42 is displayed on the display section 4.
Since the second melody tone is supplied to the second melody tone, the display section 44 displays the pressed key corresponding to the second melody tone, as in the previous case. Also, at this time, a melody key code signal corresponding to the first melody tone is output from the latch circuit 58.
Since MKC' is supplied to the automatic melody sound signal forming circuit 62, this circuit 62 receives the performance mode signal.
When the enable signal EN is supplied from the AND gate 64, which is conductive in PLAY, in response to turning on the sound generation select switch _SW2 , a melody sound signal is electronically synthesized according to the melody key code signal MKC' and output. The signal is supplied to a speaker 68 via an amplifier 66. Therefore, the first automatic melody sound is played from the speaker 68 with a delay of one tone relative to the key depression display.

On the other hand, the melody note length code signal MLG corresponding to the first melody note from the latch circuit 60 is supplied to the tempo control circuit 13. Tempo control circuit 1
3 is a melody note length code signal MLG and a melody key code signal as will be described later with reference to FIG.
MKC, key code signal by manual performance
It generates the tempo clock signal TCL and readout control signal NEXT based on the KKC, start signal ΔSTRT, and performance mode signal PLAY, and for the first melody note length code signal MLG, press the key corresponding to the second melody note. The first read control signal NEXT is generated when the button is pressed or pressed.
This first read control signal NEXT is applied to the AND gate 80 which is made conductive by the length code detection signal ML.
is supplied to the AND gate 36 via the OR gate 34, so the counter 38 is supplied to the AND gate 36 via the OR gate 34.
The counting of the clock signal φ from the clock signal φ is restarted. Therefore, the key code data and length code data corresponding to the third melody tone are sequentially read out from the memory 14, and the latch circuits 58 and 42 receive the second melody key code signal and the third melody key code signal, respectively. The code signal is latched, and the second melody code length code signal and the third melody code length code signal are latched in the latch circuits 60 and 54, respectively. Therefore, the automatic melody sound signal forming circuit 62 forms a melody sound signal corresponding to the second melody sound, and the display section 44 produces a melody sound signal corresponding to the second melody sound.
The keys to be pressed corresponding to the melody note will be displayed.
The tempo control circuit 13 performs an operation to generate a second read control signal based on the second melody note length code signal. Then, the above-mentioned operations are repeated in the same manner, thereby performing an automatic key depression display based on the data stored in the memory 14 and an automatic performance of a melody tone delayed by one note with respect to this display.

Note that the end code data is finally read out from the memory 14, and in response to this, the identification code detection circuit 40 generates the end code detection signal FN. This end code detection signal FN is applied to the flip-flop 30.
As a result, the performance mode signal PLAY becomes "0" and a series of data reading from the memory 14 is completed.

The key switch circuit 82 includes a large number of key switches each linked to a large number of keys on the keyboard 50, and supplies a key code signal KKC indicating the pressed key to the manual performance sound signal forming circuit 84 and the aforementioned tempo control circuit 13. It's becoming like that. The manual performance sound signal forming circuit 84 electronically synthesizes a melody sound signal corresponding to the pressed key in response to the key code signal KKC from the key switch circuit 82, and supplies the synthesized melody sound signal to the speaker 68 via the output amplifier 66. Therefore, the speaker 68 also produces melody sounds by manual performance.

In this case, if manual performance practice is performed using the keyboard 50, it is possible to efficiently practice performance while listening to the above-mentioned automatic performance sound and/or while viewing the automatic key press display by the light emitting element group 52. When practicing this kind of performance,
Automatic accompaniment of chords or bass notes and/or automatic rhythm accompaniment as described below can also be used as appropriate.

In the accompaniment data reading circuit 26, since the input signal of the inverter 86 is "0" when the start switch SW ₀ is turned on, the output signal of the inverter 86 = "1" is ANDed through the OR gate 88.
It is supplied to the gate 90. Therefore, start switch SW ₀ is turned on and the performance mode signal is output.
When PLAY="1" is generated, AND gate 90
A clock signal φ is supplied from the address counter 92 to the address counter 92.

Address counter 82 receives start signal ΔSTRT
When reset by , the read address signal RAD ₂ corresponding to the first read address is supplied to the selector circuit 20 as input B. At this time, the selector circuit 20 receives the input B due to the selection signal AS ₂ =“0”.
, and supplies the read address signal RAD ₂ corresponding to the first read address to the accompaniment data memory 16. Therefore, the key code data corresponding to the first accompaniment tone is read out from the memory 16, the upper 2 bits of which are sent to the identification code detection circuit 94, and the remaining 6 bits of the accompaniment key code (chord type code and root chord)
The signal is a latch circuit 9 timed by a clock signal φ.
6, respectively.

Identification code detection circuit 94 generates key code detection signal AK in response to the first key code data from memory 16, and latch circuit 96 latches the first accompaniment key code signal in response to this key code detection signal AK.

Thereafter, when the counter 92 counts the clock signal φ, the length code data corresponding to the first accompaniment tone is read out from the memory 16 in the same manner as the previous time. Of the read data at this time, the upper 2 bits of the identification code signal are supplied to the identification code detection circuit 94, and the remaining 6 bits of the accompaniment note length code signal are supplied to the latch circuit 98 which is timed by the clock signal φ. . Then, since the identification code detection circuit 94 generates the length code detection signal AL in accordance with the first length code data from the memory 16, the latch circuit 98 generates the length code detection signal AL according to the first accompaniment note length code signal. Latch accordingly. Further, the length code detection signal AL at this time is supplied to the inverter 86. Therefore, the output signal of the inverter 86 becomes "0" and is passed through the OR gate 88 to the AND
Gate 90 is made non-conductive. Therefore, counter 9
The counting operation of step 2 is temporarily stopped.

After this, the restart signal ΔSTRT′ mentioned above is OR
Since AND gate 90 is made conductive via gate 88, counter 92 again counts the clock signal φ from AND gate 90. Therefore, the key code data and length code data corresponding to the second accompaniment tone are sequentially read out from the memory 16, and in response to this, the identification code detection circuit 94 outputs the key code detection signal AK and the length code detection signal AK. AL
occur sequentially. The key code detection signal AK at this time causes the latch circuit 96 to transfer the first accompaniment key code signal to a similar latch circuit 100, and also causes the latch circuit 96 to latch the second accompaniment key code signal. In addition, the length code detection signal AL at this time causes the latch circuit 98 to transfer the first accompaniment note length code signal to a similar latch circuit 102, and causes the latch circuit 98 to latch the second accompaniment note length code signal. Further, as in the previous case, the counting operation of the counter 92 is temporarily stopped via the inverter 86.

As a result of the above operations, the latch circuit 100 begins to send out the first accompaniment key code signal AKC, and the latch circuit 102 comes to send out the first accompaniment note length code signal ALG. and,
This first accompaniment note length code signal ALG is supplied to a comparator circuit 104 and compared with the count output K ₂ of a tempo counter 106 . Here, since the tempo counter 106 is configured to count the tempo clock signal TCL from the tempo control circuit 13 after being reset by the start signal ΔSTRT from the OR gate 108, the comparison circuit 104 calculates the count value of the counter 106. is the first accompaniment note length chord signal
When the value corresponding to the note length indicated by ALG is reached, a match signal EQ is generated.

Since the match signal EQ at this time resets the counter 106 via the OR gate 108, the counter 106 counts the tempo clock signal TCL again after being reset. Further, since the coincidence signal EQ is supplied from the AND gate 110, which is turned on by the length code detection signal AL, to the AND gate 90 via the OR gate 88, the counter 92 is
Counting of the clock signal φ from gate 90 is restarted. Therefore, the key code data and length code data corresponding to the third accompaniment note are sequentially read out from the memory 16, and the latch circuits 100 and 96
2nd accompaniment key code signal and 3rd accompaniment key code signal respectively.
The second accompaniment key code signal is latched, and the second accompaniment note length code signal and the third accompaniment note length code signal are latched in the latch circuits 102 and 98, respectively. As a result, the second accompaniment key code signal AKC is sent out from the latch circuit 100, and the second accompaniment note length code signal ALG is sent out from the latch circuit 102.
Comparison circuit 104 measures the note length of the second accompaniment tone. The above-mentioned operations are repeated in the same manner, so that accompaniment data is successively read out from the memory 16, so that the accompaniment key code signal AKC is sent out from the latch circuit 100 one after another. Note that the reading of data from the memory 16 ends before the end data is read from the memory 14, and the counter 92
The end data is read from 4 and the performance mode signal is sent.
When PLAY returns to "0", the counter 38 stops advancing at the same time.

The accompaniment key code signal AKC sent out from the accompaniment data reading circuit 26 as described above is supplied to the automatic accompaniment tone signal forming circuit 112. The automatic accompaniment sound signal forming circuit 112 generates an enable signal EN from the AND gate 114 which is conductive in response to the performance mode signal PLAY in response to the turning on of the sound generation select switch _SW3 .
is supplied, the accompaniment key code signal AKC
The accompaniment tone signal is electronically synthesized based on the rhythm selection data (not shown), and the accompaniment tone signal includes a chord signal corresponding to a plurality of chord constituent notes, and a bass that matches the chord and rhythm to be generated. It is designed to generate sound signals. and,
The transmission timing of each accompaniment sound signal from the automatic accompaniment sound signal forming circuit 112 is controlled in conjunction with the rhythm according to the accompaniment timing signal AT from the rhythm pattern generation circuit 116.
The accompaniment signal from circuit 112 is supplied to speaker 68 via output amplifier 66 . Therefore, automatic accompaniment sound is also produced from the speaker 68.

The rhythm pattern generation circuit 116 is configured to generate a rhythm pattern signal RP in addition to the accompaniment timing signal AT described above in response to the tempo clock signal TCL from the tempo control circuit 13, and this rhythm pattern signal RP is generated by the rhythm sound source circuit 118.
is supplied to The rhythm sound source circuit 118 drives an appropriate rhythm sound source according to the rhythm pattern signal RP to generate a rhythm sound signal, and this rhythm sound signal is also supplied to the speaker 68 via the output amplifier 66. Therefore, the automatic rhythm sound is also produced from the speaker 68.

FIG. 4 shows an example of the display and performance operations of the above-mentioned electronic musical instrument, where A indicates the note progression of the musical score,
B indicates the key press display timing, and C indicates the automatic performance timing of the melody and accompaniment. According to FIG. 4, it can be clearly seen that the key press display precedes the automatic melody tone by one note.

FIG. 5 shows the detailed configuration of the tempo control circuit 13.

Before the start signal ΔSTRT is generated, the performance mode signal PLAY="0" is the inverter 120.
RS flip-flop 124 is reset via OR gate 122. For this reason,
The output Q="0" of the flip-flop 124 is supplied to the latch circuit 128 as a clear signal CL="1" via the inverter 126, so that all four
Data whose bit is "0" is supplied.

When the start signal ΔSTRT is generated, this signal ΔSTRT is supplied to the counter 130 as the load signal LD via the OR gate 132.
The counter 130 is loaded with all 4-bit "0" data from the latch circuit 128 in response to the load signal LD, and the counter 130 is loaded in response to this data.
The frequency division ratio is set. Therefore, the counter 13
0 divides the clock signal φ at a set frequency division ratio and generates a carry-out output CO. This carry-out output CO is supplied to the counter 130 as the load signal LD via the OR gate 132, so that the counter 130 outputs the latch circuit 1 every time it generates the carry-out output CO.
It operates to take in data from 28 and generate the next carryout output CO.

The carryout output CO generated one after another from the counter 130 in this way is output to the counter 134.
is supplied as clock input CK. For this reason,
The counter 134 counts the carry-out output CO and supplies the count output to the comparison circuit 136 as one comparison input A.

The manual setting circuit 138 is for manually setting the standard tempo as appropriate, and sends tempo data corresponding to the set standard tempo to the selector circuit 14.
0 as input B. The selector circuit 140 resets the counter 142 after the counter 142 is reset by the start signal ΔSTRT.
Since the output signal of the AND gate 144 is "0" until 2 counts 3, this output signal =
Tempo data corresponding to the reference tempo from the manual setting circuit 138 is supplied to the comparison circuit 136 as the other comparison input B in response to the selection signal SB="1" which is a signal obtained by inverting "0" by the inverter 146.

Comparison circuit 136 compares comparison inputs A and B and generates a matching signal EQ when they match. This match signal EQ causes the counter 134 to be reset via the D-flip-flop 148, so that the counter 134 again counts the carry-out output CO after being reset. Then, the same operation is repeated, and the comparison circuit 136 repeatedly generates the coincidence signal EQ at a period corresponding to the reference tempo.

The match signal EQ generated in this way is
When the output signal of NAND gate 150 is "1", it is sent out as tempo clock signal TCL via AND gate 152 which is rendered conductive. At this time, the tempo clock signal TCL is the manual setting circuit 1.
Since the tempo data from 38 has a frequency corresponding to the reference tempo, the automatic rhythm sound described above is played at a tempo corresponding to the reference tempo.

Next, when the performance mode signal PLAY becomes "1", this signal PLAY is connected to the inverter 154 and the OR
Counter 158 is reset via gate 156. Therefore, the counter 158 counts the tempo clock signal TCL and supplies the count output to the comparison circuit 160 as one comparison input A.
As the other comparison input B of the comparison circuit 160, a melody note length code signal MLG corresponding to the first melody tone is supplied.

Comparison circuit 160 compares comparison inputs A and B, and when A<B, output signal = "1" is supplied to inverter 162 and AND gate 164, and A=B.
Then, the output signal = “1” is connected to the OR gate 122,
AND gates 166, 168 and 170 and R-
S flip-flop 172. In addition,
When the output signal corresponding to A=B becomes “1”, A
<The output signal corresponding to B becomes “0”,
When the output signal of the NAND gate 150 becomes "0", the tempo clock signal from the AND gate 152 is output.
Prohibit sending TCL.

The time point at which the comparison circuit 160 generates the output signal corresponding to A=B corresponds to the time point at which the key corresponding to the second melody tone should be pressed. Almost at the same time as the first melody note length code signal MLG is supplied to the comparator circuit 160, the melody key code signal MKC corresponding to the second melody note is supplied to the comparator circuit 174 as one comparison input A. If it is assumed that a key corresponding to the second melody tone is pressed at the time when the comparison circuit 160 generates an output signal corresponding to A=B, a key code signal KKC based on the pressed key is sent to the comparison circuit 174. It is supplied as the other comparison input B.

Therefore, the comparison circuit 174 has comparison inputs A and B.
If the key code matches, a match signal is generated.
Generate EQ. This coincidence signal EQ is supplied to a differentiating circuit 182 via an AND gate 178 which is rendered conductive by an any key-on signal AKO from an OR gate 176 which receives the key code signal KKC as an input, and further via an OR gate 180. Differential circuit 18
2 differentiates the input signal at this time to generate the first key-on signal KON, and this signal KON is passed through the AND gate 170 which is conductive by the output signal corresponding to A=B from the comparator circuit 160, and further It is sent out via OR gate 184 as the first read control signal NEXT. This first read control signal NEXT causes counter 158 to be reset via OR gate 156, so that counter 158
is the tempo clock signal again after the reset.
Count TCL.

Note that when the melody key code signal MKC corresponds to a rest, the rest detection circuit 18
6 generates a rest detection signal and AND gate 166
conduction. Then, from the comparison circuit 160, A=
When the output signal corresponding to B is generated, this output signal is supplied to the differentiation circuit 182 via the AND gate 166 and further via the OR gate 180, so that the key-on signal KON and the readout control signal are generated in the same manner as described above. NEXT is generated.

The above is an operation in the case where the key press corresponding to the second melody tone is a coincident key press made almost at the same time as the output signal corresponding to A=B from the comparator circuit 160 is generated. If the key timing is early or late, the read control signal NEXT is generated as follows.

First, in the case of a quick key press, the output signal corresponding to A<B from the comparator circuit 160 causes conduction.
Since the key-on signal KON causes the flip-flop 124 to be set via the AND gate 164, the output Q="1" of the flip-flop 124 releases the clear state of the latch circuit 128 via the inverter 126. All 4-bit "0" output data of the latch circuit 128 is supplied to the adder circuit 127 as input B, and as the input A of the adder circuit 127, when the output signal of the inverter 129 is "1", the counter 130 outputs the carry-out output CO. 4-bit data "0001" is supplied each time this occurs.
Therefore, from the adder circuit 127 to the latch circuit 128
The value of data loaded into the counter 130 via the carry-out output CO is incremented by 1 each time the carry-out output CO occurs.
The generation timing of TCL becomes gradually faster, the frequency of the tempo clock signal TCL gradually becomes higher, and the tempo becomes gradually faster. Then, when the output data of the latch circuit 128 becomes "0100",
Since the MAX (maximum value) detection circuit 133 detects this data and generates an output signal = "1", the inverter 129 which inputs this output signal = "1"
prohibits the carry-out output CO from being supplied to the adder circuit 127 via the AND gate 131. Therefore, the frequency of the tempo clock signal TCL reaches its maximum value when the output data of the latch circuit 128 reaches "0100", and does not increase higher than that. Here, the output data "0100" of the latch circuit 128 corresponds to a 75% increase in the tempo, so
When the tempo clock signal TCL reaches its maximum value, the tempo increase rate is 75%. This, together with the gradual increase in the frequency of the tempo clock signal TCL, is beneficial in eliminating unnaturalness in tempo changes.

When the frequency of the tempo clock signal TCL increases, the counting speed of the counter 158 increases, and the comparator circuit 160 generates an output signal = "1" corresponding to A=B earlier than in the case of coincident key presses. Flip-flop 172 is set by key-on signal KON, and its output Q="1" makes AND gate 168 conductive via D-flip-flop 173. Therefore, the output signal ="1" from the comparison circuit 160 corresponding to A=B is sent out as the read control signal NEXT via the AND gate 168 and further via the OR gate 184. In addition,
Since the flip-flop 124 is reset in response to the output signal corresponding to A=B from the comparison circuit 160, the latch circuit 128 is also cleared in response, and the frequency of the tempo clock signal TCL returns to its original low value.

On the other hand, in the case of a slow key press, when the comparison circuit 160 generates an output signal = "1" corresponding to A=B, the output signal of the NAND gate 150 becomes "0" and the Prohibits transmission of all tempo clock signals TCL. Therefore, the counter 158 stops counting. After this, when the key-on signal KON is generated, this signal KON
is passed through the AND gate 170 which is made conductive by the output signal corresponding to A=B from the comparator circuit 160,
Furthermore, the read control signal is transmitted through the OR gate 184.
Sent as NEXT.

Next, the tempo follow-up control system will be explained. The carry-out output CO from the counter 130 is supplied to a variable frequency divider circuit 188, and is divided by a frequency division ratio corresponding to the note length indicated by the first melody note length code signal MLG. The frequency-divided output signal from the variable frequency divider circuit 188 is supplied to a counter 194 via an AND gate 192 which is rendered conductive by the output signal of an inverter 190=“1”, and is counted. The variable frequency dividing circuit 188 is provided to ensure that the count value of the counter 194 is approximately equal for all notes, and is configured such that the longer the note, the greater the frequency division ratio.

The counter 194 receives the first read control signal NEXT
The count data immediately before the reset is latched in the latch circuit 196 in response to the first key-on signal KON. That is, R
-S flip-flop 198 is OR gate 200
Since it is reset by the start signal ΔSTRT from
="0" is inverted by the inverter 202, and the first key-on signal is passed through the AND gate 204, which is turned on, and then through the OR gate 206.
KON is supplied to the latch circuit 196 as a load signal L, and in response to this, the latch circuit 196 is supplied as a load signal L, and in response, the latch circuit 196 latches the counting data from the counter 194 immediately before reset. be.

In addition, the first key-on signal KON is conductive due to the output signal = “1” of the inverter 208.
is supplied to counter 142 via AND gate 210, so counter 142 responds to 1
The count advances.

As mentioned above, the first readout control signal NEXT causes the melody data corresponding to the third melody tone to be read out from the memory 14, so the comparison circuit 160
is supplied with the note length code signal MLG corresponding to the second melody note, and the comparison circuit 174 is supplied with the key code signal MKC corresponding to the third melody note.
is supplied. After this, the comparison circuit 160 determines that A=B
Almost at the same time as generating an output signal corresponding to 3
Assuming that the key corresponding to the second melody tone is pressed, the second key-on signal KON and the second readout control signal NEXT are generated in the same way as when the key is pressed corresponding to the second melody tone. .

The second key-on signal KON is AND gate 21
Since the signal is supplied to the counter 142 via 0, the counter 142 performs the second counting operation.

The second read control signal NEXT is the counter 19
4 is reset, but the count data immediately before the reset is latched in the latch circuit 196 in response to the second key-on signal KON as before. Further, the count data corresponding to the key depression of the second melody tone, which was latched in the latch circuit 196, is latched in the latch circuit 212 in response to the load signal L consisting of the second key-on signal KON. Therefore, the averaging circuit 214 inputs the count data corresponding to the key press of the third melody tone from the latch circuit 196 and the count data corresponding to the key press of the second melody tone from the latch circuit 212, respectively. and B, are subjected to averaging processing of (A+B)/2, and are supplied to the multiplication circuit 216.

The multiplication circuit 216 multiplies the output data from the averaging circuit 214 by 0.75, and supplies the multiplication output to the comparison circuit 218 as input B. Comparison circuit 2
The counting output of the counter 194 is supplied as input A of 18, and the comparator circuit 218 compares inputs A and B and outputs an output signal of "1" while A<B.
When it is supplied to the AND gate 220 and A=B,
Output signal = “1” to D-flip-flop 222
and is further supplied to the flip-flop 198 via an OR gate 200 as a reset input R.

The second read control signal NEXT causes the melody data corresponding to the fourth melody tone to be read from the memory 14. After this, when the key corresponding to the fourth melody tone is pressed, the third key-on signal KON and the third readout control signal are activated as before.
NEXT is generated. Here, assuming that the key press corresponding to the fourth melody tone is made earlier than 75% of the average count value indicated by the output data from the averaging circuit 214, the key-on signal KON is
Flip-flop 1 through AND gate 220
98 is set, flip-flop 19
The AND gate 224 is made conductive by the output Q=“1” of the gate 8. Then, when the count value of the counter 194 reaches 75% of the above-mentioned average count value, the comparison circuit 2
18 generates an output signal = "1" corresponding to A=B, this signal = "1" is supplied as a load signal L to latch circuits 196 and 212 via an AND gate 224 and an OR gate 206. Ru. Therefore, the latch circuit 196 has the past two
The count data corresponding to 75% of the average count value regarding the number of key presses is latched, and the count data corresponding to the key press of the third melody note, which was previously latched in the latch circuit 196, is transferred to the latch circuit 212. Ru. Note that the flip-flop 198 is reset by an output signal corresponding to A=B supplied from the comparison circuit 218 via the flip-flop 222 and the OR gate 200.

Further, when the key press timing of the fourth melody tone is 75% or more of the average count value of the past two key presses, the flip-flop 198 is in the reset state, so the key-on signal KON is sent via the AND gate 204, Furthermore, it is supplied as a load signal L to latch circuits 196 and 212 via OR gate 206. Therefore, count data indicating a small or large count value is latched in the latch circuit 196 depending on whether the key press timing of the fourth melody note is early or late.
The count data corresponding to the key depression of the third melody tone, which was previously latched at 6, is transferred to the latch circuit 212.

Note that the count value of the counter 194 is the average value of the averaging circuit 2.
If the key is not pressed even after reaching 1.25 times the average count value indicated by the output data from the counter 194, the count data from the counter 194 is transferred to one comparison input A.
and the output data of the averaging circuit 214 is 1.25
A comparison circuit 228, which uses the output data from the multiplication circuit 226 as the other comparison input B, generates a match signal EQ when comparison inputs A and B match. This coincidence signal EQ is passed through an inverter 190 to AND
Since the gate 192 is made non-conductive, the counter 19
The count value of 4 is never larger than 1.25 times the average count value indicated by the output data of the averaging circuit 214.

When the count data is latched in the latch circuits 196 and 212 by any of the methods described above, the averaging circuit 214 collects the count data corresponding to the key press of the third melody note from the latch circuit 212 and the count data from the latch circuit 196. and the count data corresponding to the key depression of the fourth melody tone, and the averaged data is supplied to the selector circuit 140 as input A. At this time, the counter 142 counts the third key-on signal KON generated based on the key press of the fourth melody tone, and outputs the output signal = "1".
Supplied to AND gate 144 and inverter 208. Therefore, the inverter 208 makes the AND gate 210 non-conductive by its output signal=“0”, and thereafter prohibits the key-on signal KON from being supplied to the counter 142. Also, AND gate 1
44 supplies the output signal = "1" to the selector circuit 140 as the selection signal SA for selecting the input A, so the selector circuit 140 is connected to the averaging circuit 21.
Input the averaged data from 4 to the comparison circuit 136 B
Supply as. Therefore, at this point, comparison circuit 1
The tempo data as input B of 36 is switched from that corresponding to the reference tempo from the manual setting circuit 138 to the averaged data from the averaging circuit 214, and the frequency of the tempo clock signal TCL is changed to match the key pressed of the third melody note. It is controlled according to the average tempo data regarding the key depression of the fourth melody note.

Here, if the keys pressed for the third and fourth melody notes are both matched keys pressed corresponding to the note length indicated by the melody note length code signal MLG, the frequency of the tempo clock signal TCL will be the same as the previous one. Although it is the same as that corresponding to the standard tempo, for example, if the fourth melody note is pressed quickly or slowly, the frequency of the tempo clock signal TCL changes.

That is, in the case of a quick key press, the frequency of the output CO from the counter 130 gradually increases as described above, and the tempo data as input B of the comparator circuit 136 is smaller than that corresponding to the standard tempo. Since it indicates a numerical value, the frequency of the tempo clock signal TCL gradually increases, and the tempo of automatic performance gradually increases in accordance with the tempo of manual performance. In this case, since the tempo of the automatic performance does not suddenly increase, the person listening to the automatic performance does not feel unnatural.

In addition, in the case of a slow key press, the tempo data as input B of the comparator circuit 136 indicates a larger count value than that corresponding to the reference tempo, so the frequency of the tempo clock signal TCL becomes low, and the tempo of automatic performance is set to manual. It slows down to follow the tempo of the performance.

The tempo follow-up control operation as described above regarding the key depression for the fourth melody tone is performed in the same manner for the key depressions for each of the fifth and subsequent melody tones.

In the above embodiment, since the averaging circuit 214 is provided to average the manual performance tempo data, it is possible to prevent the automatic performance tempo from overly following the manual performance tempo. .

As described above, according to the present invention, automatic performance is gradually fast-forwarded by gradually increasing the frequency of the tempo clock signal when a key is pressed earlier than the key pressing timing indicated by the musical score data. The tempo of automatic performance does not suddenly increase,
It has the effect of giving a natural feel.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an electronic musical instrument according to an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing the formats of melody data and accompaniment data, respectively, and FIGS. FIG. 5, which is a diagram for explaining display and performance operations, is a detailed circuit diagram of the tempo control circuit of the electronic musical instrument. DESCRIPTION OF SYMBOLS 10... Music score, 10a... Recording medium, 12... Music score data reading control circuit, 13... Tempo control circuit, 14
...melody data memory, 22...start/stop control circuit, 24...melody data reading circuit,
50...Keyboard, 62...Automatic melody sound signal forming circuit, 84...Manual performance sound signal forming circuit, 112
...Automatic accompaniment sound signal forming circuit, 118...Rhythm sound source circuit, 124...R-S flip-flop for fast forward control, 127...Addition circuit, 128...Latch circuit,
130...Program counter, 133...MAX detection circuit.

Claims (1)

[Scope of Claims] 1. means for generating a tempo clock signal, means for generating an automatic performance sound based on the tempo clock signal, and a storage device storing musical score data;
a reading circuit that reads musical score data from the storage device; a keyboard; a detection circuit that detects that a key is pressed on the keyboard earlier than the key pressing timing indicated by the musical score data read by the reading circuit; An electronic musical instrument comprising: a control circuit that gradually increases the frequency of the tempo clock signal in accordance with a detection output from the circuit. 2. The electronic musical instrument according to claim 1, wherein the control circuit includes a circuit for setting an upper limit on the frequency of the tempo clock signal.