JPH0473690A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce a load on a CPU by providing a melody data storage device, a musical interval generator, a notation length generator, and an address designation device at a melody generator. CONSTITUTION:At the beginning stage, melody data is read out from the melody data memory device 106 based on an initial address signal from the CPU, and the musical interval generator 126 generates a musical interval signal based on the scale data of the melody data, and a performance operation is performed. The notation length generator 116 generates a notation signal based on the notation data of the melody data, and the address designation device 104 updates the address of the address designation device 104 based on the signal, and reads out the melody data from the melody data storage device 106 sequentially, and the musical interval generator 126 generates the musical interval signal based on the scale data, then, the performance operation is performed. Thereby, the load on the CPU can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer having a melody generation function, and particularly to control of the performance of the melody.

[Prior Art] A conventional microcomputer having a melody generation function mainly has only a pitch generation device as a melody generation device, and its control is stored in a storage device that stores a program for controlling the microcomputer.
This was done using a control program for melody generation.

[Problems to be Solved by the Invention] Therefore, this type of conventional microcomputer has the following problems.

(1) Since a large amount of control programs are required to generate a melody, a large capacity storage device that can store a large amount of programs is required, including the control of the microcomputer itself. This leads to an increase in the cost of the system.

(2) It is difficult to perform other controls while the melody is being played, and therefore it is not possible to respond immediately to requests from outside the system. That is, it is not possible to play long melodies.

The purpose of the present invention was to solve the above problems, and it is an object of the present invention to provide a low-cost microcomputer that can immediately respond to external requests even while playing a melody.

[Means for Solving the Problems] A microcomputer of the present invention includes a CPU that performs various data processing, a melody generator that outputs a melody signal, and a data bus that transfers data input and output from the CPU. .

The melody generator generates a scale based on the scale data of the melody data, a melody data storage device that stores the melody data including scale data, note length data, and end data indicating whether or not the performance melody has ended. a note length generator that generates a note length signal based on note length data of melody data; and a note length generator that inputs an initial address signal from a CPU and uses the initial address signal as a read address of a melody data storage device. and an addressing device that outputs the address following the initial address signal as an address signal of the melody data storage device at a timing based on the note length signal.

In addition to the above configuration, the melody generator also includes a song end signal generation circuit that outputs a melody end signal based on the end data of the melody data storage device and the note length signal of the note length generator; When you enter C
An interrupt generation circuit that sends a melody end interrupt signal to the PU, and a melody control signal that instructs the melody generator to start or stop playing from the CPU are input at least, a melody end signal is input, and a play start command signal is input. and a control device that starts the operation of each device constituting the melody generating device and stops the operation in response to a performance stop command signal and the melody end signal.

In addition, the addressing device has an address register in which an initial address signal is set from the CPU, and sets the initial address signal of this address register as a preset value, and counts up (or It consists of an address counter that counts down.

The control device also includes a melody control register that is set by inputting at least a melody control signal instructing the melody generator to start or stop playing from the CPU, a melody end signal, and a melody generation by inputting a play start command signal. The apparatus includes an on/off control circuit that starts the operation of each device constituting the apparatus and stops the operation in response to a performance stop command signal and the melody end signal.

Further, when the CPU receives an interrupt signal, it sends an address signal corresponding to the start address of a plurality of preset songs to the address register.

In the microphone computer of the present invention, all the above-mentioned devices including the CPU, data bus, and melody generator are
Constructed on one chip.

Incidentally, one or both of the melody control register and the address setting register may be configured as a storage device located in the same address space as a storage device controlled by the CPU.

Further, the address register stores a plurality of addresses of the melody data storage device according to the playing order of the melody,
It may also be configured to include a performance order storage device that causes an address counter to set an address according to the order as a preset value each time the end of a melody is input.

Furthermore, the microcomputer of the present invention includes a data selection device which receives input of melody data from the melody data storage device and melody data from the data bus and selects and outputs either one based on a command from a CPU; It has a temporary storage device that inputs melody data from the data selection device, temporarily stores it, then outputs the scale data to the scale generation device, and outputs note length data to the note length generation device.

[Function] In this invention, melody data is initially read from the melody data storage device based on the initial address signal from the CPU, and the pitch generator generates pitch signals based on the scale data of the melody data. , make musical movements. Then, the note length generator generates a note length signal based on the note length data of the melody data, and the addressing device updates the address of the addressing device based on the signal, and sequentially reads the melody data from the melody data storage device. The pitch generator generates a pitch signal based on the pitch data, and performs a performance operation.

Further, the song end signal generator outputs a melody end signal based on the end data from the melody data storage device and the note length signal from the note length generator, and when the interrupt generator receives the melody end signal, it sends the melody end signal to the CPU. and sends a melody end interrupt signal.

The control device starts the operation of each device constituting the melody generating device by inputting a performance start command signal from the CPU,
The operation is stopped by the performance stop command signal and the melody end signal.

In addition, in the addressing device, the address register is set with an initial address signal from the CPU, and the address counter sets the initial address signal of this address register as a preset value, and counts each time a signal based on the note length signal is input. It counts down and updates the read address of the melody data storage device.

In addition, in the control device, the melody control register is CP
A melody control signal instructing the melody generating device to start or stop playing is input and set from U, and the on/off control circuit starts the operation of each device constituting the melody generating device by inputting the playing start command signal, The operation is stopped by a performance stop command signal and a melody end signal.

Further, when the CPU receives an interrupt signal, it sends an address signal corresponding to the start address of a plurality of preset songs to the address register. As a result, a plurality of pieces of music are played in sequence.

Furthermore, if the address register has a performance order storage device, each time the end of a melody is input, an address according to that order is set in the address counter as a preset value. Therefore, although a plurality of pieces of music are played one after another, the CPU does not need to input addresses corresponding to the pieces of music to be played during that time, which reduces the burden on the CPU.

Furthermore, in the present invention, the data selection device receives melody data from the melody data storage device and melody data from the data bus and selects and outputs either one based on a command from the CPU. It outputs scale data to the generator, and outputs note length data to the note length generator. In this way, the melody data from the melody data storage device and the melody data from the data bus can be used as appropriate, so it is possible to play melodies with a high degree of freedom.

Embodiment FIG. 1 is a block diagram showing the hardware configuration of a microcomputer according to an embodiment of the present invention.

Microcomputer IO is CPU12, ROMI4
, oscillation circuit 1B, system reset control circuit 18, RA
M20, melody generator 22, interrupt generator 24,
input/output boat 26, output boat 28, data bus 30,
Address bus 32, interrupt control line 34, selection control line 3
It consists of 6 mag. Note that this microcomputer includes other components, such as an LCD driver, a clock timer, a stopwatch timer, an analog comparator, etc., but these are omitted because they are not directly related to this invention.

FIG. 2 is a block diagram showing details of the melody generating device 22. As shown in FIG. The melody address setting register (hereinafter referred to as address register) 102 is a melody data storage device (
Hereinafter, the start address of the melody stored in the melody ROM 10B is set. In other words, CPU
The start address of the melody can be written or read via the data bus 30 based on the 12 commands.

A melody address counter (hereinafter referred to as address counter) 104 is connected to the address bus 1 of the melody ROM 106.
This counter specifies the address of the melody ROM 10B through 05, and has the function of counting the address increment signal 117 and incrementing the address of the melody ROM 10B by one address for each count. Further, the melody start address set in the address register 102 is written to the address counter 104 via the melody address bus 103 as necessary. Melody ROM
If 10B is a storage device where the format of data written to one address includes the address to be executed next, then
This address counter 104 is not necessary.

The melody ROM 10G stores at least information on the scale, note length, and end of the melody among the information on the melody to be generated.

FIG. 3 is an explanatory diagram showing the data format of one note stored in the melody ROM 10B.

As shown in the figure, it is composed of end data, pitch address data, note length data, and attack data. The note length data is output to the note length data bus 115, and the scale address data is output to the scale data bus 11B.

When the song end signal generating circuit 108 inputs the end data from the melody ROM 10B and then inputs the address increment signal 117 from the note length generating circuit 11B, it assumes that the performance of the melody has ended and outputs a melody end signal of 10.
9 is generated and output to the control circuit 110 and the melody interrupt generation circuit 11B.

FIG. 4 is a block diagram showing the configuration of the control circuit 110. This control circuit 110 includes a melody control register 140 that stores various control data, such as information on the start and stop of a melody, and an on/off control circuit 142 that is controlled on/off based on a melody end signal. It is configured. The melody control register 140 is connected to the data bus 30, and writing and reading thereof are controlled by instructions from the CPU 12. Melody control register 14
The output of the MELC register 0 is input to the on/off control circuit 142 together with the melody end signal, and the on/off control circuit 142 outputs an on control signal or an off control signal. Further, a tempo control signal is output from the TEMP register, and a performance speed control signal is output from the CLKCO and CLKCI registers.

The frequency dividing circuit 112 inputs the playing speed control signal from the control circuit 110 and also receives the clock signal inputted through the gate circuit 120, and divides the frequency of this clock signal based on the playing speed control signal. Outputs a divided signal.

Here, the on/off control signal from the control circuit 110 is input to the gate circuit 120 as a gate control signal, and when the gate signal is off, no clock signal is supplied to the frequency dividing circuit 112, so that the performance cannot be performed. It will not be done.

The tempo generation circuit 114 receives the divided output from the frequency dividing circuit 112 and the tempo control signal from the control circuit 110, and
A clock signal having a frequency corresponding to the tempo control signal is generated and outputted to the note length generating circuit 1B.

The note length generation circuit 116 receives note length data and a clock signal from the note length data bus 115 and generates a note length signal. That is, the address increment signal 117 is sent to the address counter 10 every time the time corresponding to the note data elapses.
4 and the song end signal generation circuit 108. This note length generation circuit 1111 is composed of a counter (presettable counter) whose count value can be set using the note length data bus 115 as a set signal, and counts up every time the clock signal from the tempo generation circuit 114 is input. When the preset value is reached, an address increase signal 117 is output.

After detecting that the end data of the melody data is set to "1", the song end signal generation circuit 108 transmits the above-mentioned song end signal 109 to the melody interrupt generation circuit 118 and control at the timing when the address increase signal 117 is input. Output to circuit 110. Melody interrupt generation circuit 11
B receives the melody end signal 109 output from the song end signal generation circuit 108 at the end of the melody, and outputs a melody end interrupt signal 119 to the interrupt generator 24.

The scale address data stored in the melody ROM 10B is input to the scale ROM 122 as an address signal via the scale data bus 121, and various scales corresponding to the address signal are read out and sent to the scale data bus 125.
It is output to the pitch generation circuit 12B via. The pitch generation circuit 12B is composed of a counter (presettable counter) whose count value can be set using pitch data from the pitch data bus 125 as a set value. The frequency multiplier circuit 124 inputs the clock signal via the gate circuit 120, multiplies it, and outputs it to the pitch generator 12B. The melody output control circuit 128 amplifies the output of the pitch generation circuit 12B, that is, the pitch output, and outputs it as a melody output 129. This melody output 129 causes a musical instrument (not shown) to perform a musical performance.

The microcomputer of this embodiment is configured as described above, and for example, the following melodies can be controlled using C.
This can be executed with a reduced load on the PU 12.

(a) Single-song performance mode (automatically plays a series of melodies once) (b) Continuous performance mode (automatically plays a series of melodies repeatedly or plays a single melody by combining multiple series of melodies) (e) Forced Performance mode (forced melody change or stop during performance) Each performance method will be described in detail below.

(a) Single-song performance mode; FIG. 5 is a flowchart showing the operation of the CPU 12 in this performance mode. In addition, melody ROM 10
Part of B contains information on the notes that make up the melody (in continuous addresses) so that a series of melodies is composed.
(see FIG. 3) has been written (this also applies to the performance mode described later).

(1) Address register by instruction of CPU12】02
The melody start address (address where information regarding the first note of a series of melodies is written) of the melody desired to be played is set in the melody ROM 10B.

(2) MEL of the control circuit 110 according to instructions from the CPU 12
Set the melody start information “1°” in the C register. This melody start information is transmitted to the on/off control circuit 142.
is output as a performance start signal. Then, for example, by opening the gate circuit 120, the clock signal is transmitted to the division circuit 1.
12 and a frequency multiplier circuit 124. Further, the melody start address set in the address register 102 is written in the address counter 104, and as a result, the address of the melody ROM 10B is set as the start address of the melody desired to be played, and based on the melody data written in that address. The melody begins to play.

The scale address data of the specified address is stored in the scale ROM.
122, a scale signal at an address corresponding to the address data is read out from the scale ROM 122, and then sent to the pitch generation circuit 12B via the scale data bus 125.
Enter. Then, the pitch generation circuit 126 outputs the scale signal as a pitch signal, and the output is amplified by the melody output control circuit 128 and output as a melody output 129.
A performance is made.

Further, the note length data stored at the specified address is input and set to the note length generation circuit 11B, and the note length data is counted down based on the clock signal from the tempo generation circuit 114 and becomes zero. (or when it counts up and reaches a value corresponding to the note length data) it issues an address increment signal 117. In response, the address counter 104 reads the melody ROM 1.
Advance the address of 0B by one address.

By repeating this operation, a series of melodies stored in the melody ROM 10B are automatically played without the involvement of the microcomputer.

(3) By the end of the series of melodies, "0#", which is performance stop information, is set in the MELC register of the control device 110 by a command from the CPU 12.

FIG. 6 is a timing chart at this time.

At the time when this 0'' is set, the on/off control circuit 1
Since the melody end signal 109 has not yet been input to 42, the performance is not stopped.

(4) If "1" is set in the end data of the melody data in the melody ROM 10B at the address specified by the address counter 104, this data is assumed to be the last note address of a series of melodies, and a song end signal is generated. The circuit 10B generates the melody end signal 10 at the timing when the address increase signal 117 from the note generating circuit 11G is input, that is, at the timing when the final note is finished playing.
Outputs 9.

As a result, the on/off control circuit 142 generates a performance stop signal that manually inputs the melody end signal 109 to stop the performance, thereby stopping each of the above-mentioned devices included in the melody generating device 22. At the same time, the melody interrupt generation circuit 118 receives the melody end signal 109 and the CPU 1
2, a melody end interrupt signal 119 is generated to notify the end of the melody.

This melody end interrupt signal 119 is input to the CPU 12 via the interrupt generation circuit 24, and when the interrupt is permitted, the CPU 12 jumps to the melody subroutine, reads and clears the interrupt flag, then enables it and returns. .

As described above, simply by setting the start address of the melody desired to be played in the address register 102 by the command of the CPU 12 and writing the start information or stop information of the melody in the MELC register of the control circuit 110, the melody desired to be played is automatically set. Since the melody is played and finished, the load on the CPU 12 for playing the melody becomes very small.

(b) Continuous performance mode; Figure 7 shows the CPU 12 in this continuous performance mode.
3 is a flowchart showing the operation of FIG.

(b-1) When automatically playing a series of melodies repeatedly (In this performance mode, the processing of the part surrounded by the broken line in FIG. 7 is omitted.) (1) The address register 102 is The start address of the melody desired to be repeatedly played in the melody ROM 10B (the address where information regarding the first note of the repeated melody is written) is written.

(2) MEL of the control device 110 according to instructions from the CPU 12
Set "1", which is the melody start information, in the C register. By this operation, information on the start of the melody is output from the on/off control circuit 140. Then, each device of the melody generating device 22 becomes ready to start playing, and the melody start address set in the address register 102 is written into the address counter 104, and as a result, the address of the melody ROM 10G is set to the melody desired to be played. The address is set as the start address, and the melody starts playing. The operation in this melody performance is similar to the operation in the above-mentioned mode.

(3) The address of melody ROM10 automatically advances.
When the final address with "1" set in the end data is specified, the melody end signal 109 is output from the song end signal generation circuit 108 in the same manner as in the above mode, and the melody end signal 109 is output from the control device 110 and the melody interrupt generation circuit. 11
Enter 8. At this point, the control bag M 110 is set in the MELC register of the control device 110 as "1", which is the melody start information, and "O", which is the melody stop information, is not set. It outputs an on control signal to write the address set in the address counter 104 into the address counter 104.

At this time, since the same address is set in the address register 102 as when the melody start information was set in the MELC register of the control device 110, the address data on the address bus 105 sent out via the address counter 104 is repeated again. This is the start address of the desired melody. In other words, the desired repeat melody will be played repeatedly.

9 is a timing chart showing the operation at this time in FIG. 8.

Furthermore, since a melody end interrupt signal 119 is generated every time the desired repeat melody is played once and finished, the CPU 12 is interrupted in the same manner as in the above mode, and the CPU 12 increments the number of plays n.

(4) In the CPU 12, when the number of performances n reaches the set desired number of performances N-1, the CPU 12 commands to set "0°", which is the performance stop information, in the MELC register of the control device 110. As a result, After the currently played desired repeat melody is played, the melody generator 22 stops its playing operation.The operation in this case is as described in (3) and (4) of the one-song playing mode above. It is the same as the operation.

(b-2) When a single melody is played by combining a plurality of melodies.

In the above performance operation (b-1), if the address set in the address register 102 is changed after the melody end interrupt signal 119 is generated, a new melody can be continuously played instead of being played repeatedly.

In other words, as shown in Figure 7, the MELC register is set to "1".
After setting , the CPU 12 presets the address of the next performance piece in the address register 102 via the data bus 30. When the performance of the first melody is finished and the song end signal generating circuit 10g outputs the melody end signal 109, the address register 102
The address of the next performance piece set in is set in the address counter 104, the melody data of the second performance piece is read out from the ROM 10B, and the melody of the second performance piece is played.

On the other hand, the melody interrupt generation circuit 108 receives the melody end signal 109 and generates the melody end interrupt signal 119 to notify the CPU 12 of the end of the melody.

This melody end interrupt signal 119 is input to the CPU 12 via the interrupt generation circuit 24, and when the interrupt is permitted, the CPU 12 jumps to the melody subroutine, increments the number of performances n, and depending on the number of performances, for example, n -1, the address of the third piece of music to be played is set in the address register 102 via the data bus 30, and a tempo control signal is set in the TEMP register of the melody control register 140 of the control circuit 110. Then, read and clear the interrupt flag, then enable it and return.

When the number of performances n reaches a predetermined number N-1, "02" is set in the MELC register, and the next time a melody end signal is generated, an off control signal is generated from the control circuit 110, and the melody generator 22 is turned off. The movement stops and the performance ends.

That is, by storing the address of the next melody to be played in advance in the address register while a melody is being played, it is possible to play a series of long melodies by combining different melodies.

(e) Forced performance mode; FIG. 9 is a flowchart showing the operation of the CPU 12 in this performance mode. When it becomes necessary to forcibly change or stop the melody during a performance due to a request from outside the system, the request can be executed by following the steps below.

(1) Melody ROM 10B that stores information on the melody desired to be changed when a request from outside the system occurs.
The start address at is set in the address register 102.

(2) Immediately after setting the melody stop information “0°” to the MELC register of the control device 11O, write the melody start information “1” again.As a result, the address register 10
The address set to 2 is set in the melody address counter 106 upon receiving the melody start information, the address of the melody ROM 106 jumps to the start address of the melody desired to be changed, and then the melody desired to be changed is played. FIG. 1O is a timing chart showing the operation at that time.

(3) If you want to force a stop, set the melody you want to change to a silent melody such as a rest, and the melody will be forced to stop.

In FIG. 11, address register 102 is melody ROM1.
FIG. 3 is a block diagram of a case where the performance order storage device stores a plurality of addresses of 06. This address register 1
02 is a performance order storage device 1 that is connected to the data bus 30 and can be written to and read out according to instructions from the CPU 12.
44, and an address counter 14B that specifies the address of this performance order storage device 144. The address counter 14B receives the melody end signal 109 and increments the address of the performance order storage device 144 by one each time the melody end signal 109 is input. If the performance order storage device 144 is of a type in which data written to one address includes an address to be executed next, the address counter 14B is not necessary.

With such a configuration, the burden on the CPU 12 for playing the melody can be further reduced. Well, the above r
Combining multiple melodies of (b-2) to create 1
By writing the address of the melody ROM 106, which was written into the address register 102 every time the melody end interrupt signal 109 described in "Playing a Melody", into the performance order storage device 144 before starting the melody performance, a series of melodies can be played. Can be played automatically. Its operation will be explained next.

(1) Before starting a series of melody performances, enter the addresses of the melody ROM 106 necessary for the performance in the order of performance.
It is written into the performance order storage device 144.

(2) Start playing the melody using the method described above.

(3) The address to be played first is output to the melody address bus 103, and the address counter 1
04, the melody information written in that address and the addresses consecutive to that address in the melody ROM 106 is read out, and the melody is played.

(4) At the end of the series of melody performances, a melody end signal 109 is output, and as a result, the order storage device address counter 14B advances the address bus of the performance order storage device 142 by one address.

(5) The address to be played second is output to the melody address bus 103.

(6) The above (3), (4), and (5) are repeated to play a series of melodies.

(7) To end the performance, use the melody end interrupt signal 119
It can be known by counting the number of occurrences of (b-2
) The performance can be ended using the performance ending method described in the performance mode.

Figure W412 is a block diagram showing another example of the configuration of the melody generating device 22. In this embodiment, a data selection circuit 130 and a data storage device 132 are added to the embodiment of FIG. This data selection circuit 130
A data bus 30 and a data bus 134 of the melody ROM 106 are connected to the ROM 106, and the data bus 134 is composed of, for example, a two-manpower/one-output selector. Select and import the data. The data storage device 132 is composed of, for example, a register, and temporarily stores the data input through the data selection circuit 130, and then outputs the data to the note generation circuit 11B and the scale ROM 122, respectively. The subsequent operations are similar to the embodiment shown in FIG.

Therefore, the ROM 14 that stores the program of the CPU 12
Or the data stored in the RAM 20 can be transferred to the data bus 30.
The melody can be played by writing it into the data storage device 132 via the data selection device 130. As a result, control can be performed using both the melody data in the ROM 14 or RAM 20 and the melody data in the melody ROM 10B.

This means that depending on the purpose to which this microcomputer is applied, when the melody capacity of the melody ROM 10B is small, it is possible to store the missing melody in the ROM 14 or RAM 20 and perform it. .

Furthermore, if the data in the data storage device 132 is configured to be output to the data bus 30, the melody ROM
Testing time at the time of shipment of 10B is shortened.

By the way, in the above embodiment, address counter 1
04 showed an example of counting up, but Melody RO
Needless to say, depending on the method of storing M10B, the countdown may be performed.

Also, the address register 1 connected to the data bus 30
02 and the melody control register 140, or either one thereof may be configured such that, for example, the RAM 20 is responsible for the functions thereof.

Furthermore, although the term melody is used in this embodiment, it goes without saying that this includes onomatopoeic sounds of animals, sound effects in games, and the like.

[Effects of the Invention] As described above, according to the present invention, a control command from the CPU is required only when starting a melody performance, and at other times the melody generator performs signal processing to perform 'C' performance. Therefore, the load on the microcomputer can be reduced, and as a result, the storage capacity of the microcomputer can be reduced, and it can quickly respond to requests from outside the system.

In addition, the melody performance can be appropriately controlled by the melody data stored in both the storage device that stores instructions from the microcomputer and the melody data storage device that stores melody data exclusively, so the melody capacity can be reduced. It's bigger and has more freedom.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the hardware configuration of a microcomputer according to an embodiment of the present invention, Fig. 2 is a block diagram showing details of the melody generator shown in Fig. 1, and Fig. 3 shows the format of melody data. The explanatory diagram, FIG. 4, is a block diagram showing the configuration of the control circuit. Figures 5 and 6 are flowcharts and timing charts showing operations in single-song performance mode, Figures 7 and 8 are flowcharts and timing charts showing operations in continuous performance mode, and Figures 9 and 10 are forced operation. 3 is a flowchart and a timing chart showing operations in a performance mode. FIG. 11 is a block diagram showing an example of the structure of the address register, and FIG. 12 is a block diagram showing another embodiment of the melody generating device. 12...CPU, 30...Data bus, 22...
Melody generator, 10B...Melody ROM, 10
2... Address register, 104... Address counter, 110... Control circuit, 11B... Note length generation circuit, 118... Melody interrupt control circuit, 126
. . . Scale generation circuit, 128 . . . Melody output control circuit. Agent Patent Attorney Muneharu Sasaki Figure 3 Figure 1 Figure 4 Figure Interruption Occurrence Figure Figure 10

Claims (10)

[Claims] (1) Central processing unit (hereinafter referred to as C) that performs various data processing
PU), a melody generation device that outputs a melody signal, and a data bus that transfers data input and output to the CPU, and the melody generation device includes: a) at least scale data, note length data, and melody data; a) a melody data storage device that stores melody data including end data indicating the presence or absence of an end; b) an interval generator that outputs a pitch signal based on scale data of the melody data; and c) based on note length data of the melody data. d) a note length generator that receives an initial address signal from the CPU and supplies the initial address signal as a read address of the melody data storage device; and d) an address that follows the initial address signal. and an addressing device that outputs as an address signal for a melody data storage device at a timing based on the note length signal. (2) The melody generation device further includes: e) a song end signal generation device that outputs a melody end signal based on the end data of the melody data from the melody data storage device and the note length signal of the note length generation device; f) an interrupt generating device that sends a melody end interrupt signal to the CPU when the melody end signal is input; and g) an instruction from the CPU to start or stop playing the melody generating device via the data bus. inputting at least a melody control signal and the melody end signal; inputting a performance start command signal to start the operation of each device constituting the melody generating device; and a performance stop command signal and the melody end signal to start the operation of each device. 2. The microcomputer according to claim 1, further comprising a control device for stopping the microcomputer. (3) The addressing device includes an address register to which an initial address signal is set from the CPU via the data bus, and the initial address signal of this address register is set as a preset value, and a signal based on the note length signal is set. Claim 2 comprising an address counter that counts up or down each time an input is made.
The microcomputer described. (4) The control device inputs at least a melody control signal input from the CPU via the data bus to set the melody control signal instructing the melody generating device to start or stop playing, and inputs the melody end signal. ,
4. An on/off control circuit according to claim 3, further comprising an on/off control circuit that starts the operation of each device constituting the melody generating device upon input of a performance start command signal, and stops the operation upon input of a performance stop command signal and the melody end signal. microcomputer. (5) The microcomputer according to claim 4, wherein when the CPU receives an interrupt signal, the CPU sends an address signal corresponding to a preset start address of a plurality of songs to an address register via the data bus. (6) The microcomputer according to claim 5, wherein the CPU, the data bus, and the melody generating device are configured on one chip. (7) In place of the melody control register, the melody control register is configured as a storage device located in the same address space as a storage device controlled by the CPU.
The microcomputer described. (8) In place of the address setting register, the address setting register is configured as a storage device located in the same address space as a storage device controlled by the CPU.
The microcomputer described. (9) an address register stores a plurality of addresses of the melody data storage device according to the order in which the melody is played;
2. The microcomputer according to claim 1, further comprising a performance order storage device which causes an address counter to set an address according to the order as a preset value each time the melody end signal is input. (10) a data selection device that receives melody data from the melody data storage device and melody data from the data bus and selects and outputs either one based on a command from the CPU; 2. A microcomputer according to claim 1, further comprising a temporary storage device for inputting melody data, temporarily storing the scale data, and outputting the scale data to the note length generator, and outputting the note length data to the note length generator. .