JPH046958B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to an automatic performance device.

[Background of the invention]

Various automatic performance devices have been developed in the past, and automatic performance information is temporarily stored in the internal memory of the automatic performance device from a large-capacity external memory such as magnetic tape, magnetic card, ROM pack, etc.
It is common to perform automatic performance by generating musical tones based on automatic performance information stored in an internal memory.

However, with this type of automatic performance device, the number of songs that can be played is limited by the storage capacity of the internal memory, and it is often impossible to play songs that take a long time, such as classical music. Improvement was desired.

By the way, as a technology for transferring large amounts of data, there is a so-called replacement buffer technology (for example, the
No. 46089, JP 57-48798, JP 57-182246
The present invention applies this technology to an automatic performance device and further improves it.

[Purpose of the Invention] This invention was made in view of the above circumstances, and is an automatic performance control system that enables the performance of long songs that cannot be stored in memory at once, and that also enables automatic performance control to be performed in a desirable manner. The purpose is to provide musical performance equipment.

[Summary of the Invention] That is, the automatic performance device of the present invention continuously performs automatic performance by alternately writing automatic performance information into two memory means and reading it out. In particular, the control means for controlling automatic performance includes a first detection means for detecting the completion of writing of automatic performance information into one of the two memory means, and a first detection means for detecting the completion of writing of automatic performance information into one of the two memory means, and a first detection means for detecting the completion of writing of automatic performance information into one of the two memory means. a second detection means for detecting the completion of reading of the automatic performance information to the memory means; and when the first detection means detects the completion of the writing, waiting until the timing at which the second detection means detects the completion of the reading; an operation change timing control means for starting a read operation for the one memory means and a write operation for the other memory means; and an operation change timing control means for starting a read operation for the one memory means; The apparatus is characterized in that it includes an error determining means that determines that an error has occurred and stops the automatic performance if the first detecting means does not detect the completion of the writing.

Therefore, in a normal automatic performance state, the operation change timing control means switches between the read operation and the write operation for the two memory means at the optimum timing, and for some reason, the read operation for the memory means is switched over at the optimum timing. If the end of the write operation is delayed, the error determining means prevents the automatic performance from occurring unnaturally.

〔Example〕

The present invention will be explained in detail below with reference to an embodiment shown in the drawings.

FIG. 1 is a system configuration diagram of this embodiment, in which automatic performance information is transferred from an external memory and supplied to the data input device 1. As shown in FIG. For example, this automatic performance information is transferred from a computer device such as a personal computer. Of course, this automatic performance information may be directly transferred from a ROM pack, floppy disk, etc. In this embodiment, a personal computer controls the data transfer, and the personal computer can determine which part of the song the information currently being transferred corresponds to.

The data input device 1 functions as an interface, and normal automatic performance information is stored in the memory.
When the start command is input and stored in either MEMA or the memory MEMB, a start signal START is sent to the automatic performance circuit 2.

If there is change data in the input data, a signal _S1 is sent to the flag FLAG1 to invert the contents. Furthermore, this data input device 1 inputs the address at the time of writing to the memory MEMA and memory MEMB through the address input terminal.
Give to ADR/W.

In the data input device 1, a signal CS given from a read/write controller 3, which will be described later, is ON.
(“1”) state, perform the above operation,
When signal CS is OFF (“0”), data input is prohibited.

The above memory - MEMA and memory - MEMB include
Automatic performance information from the data input device 1 is commonly given, but when the signal given to the read/write terminal R/ is "0", that information is stored, and when the signal is "1"
In this state, the contents of the memory MEMA and the memory MEMB can be read. and,
The memory MEMA terminal R/ has a flag FLAG.
1's output signal F1 passes through the OR gate 4, and further outputs the read/write controller 3's output signal.
E1 is applied via the inverter 5 and via the OR gate 4.

Further, the output signal F1 of the flag FLAG1 is inverted by the inverter 6, and then the output signal of the inverter 5 is supplied to the terminal R/ of the memory MEMB via the OR gate 7. .

And this memory MEMA, memory
The contents of the MEMB are commonly sent to the data selector 8, and one of the memory outputs is selected according to the output signal F2 of the flag FLAG2 and is applied to the automatic performance circuit 2. That is, the above flag FLAG
If 2 is ON (“1”), the memory
MEMB output is selected, and conversely the above flag
When FLAG2 is in the OFF state (“0”), the output of the memory MEMA is selected and supplied from the data selector 8 to the automatic performance circuit 2.

After the start signal START is transferred from the data input device 1, the automatic performance circuit 2 performs the performance according to the automatic performance information given from the data selector 8, and performs the performance for a time period corresponding to the length of the musical note. Then, the address signals are sequentially changed, and the addresses at the time of reading the memory-MEMA and memory-MEMB are applied to the address input terminal ADR/R.
If there is change data in the automatic performance information, the signal _S2 and the flag FLAG2 are inverted.

The above-mentioned automatic performance circuit 2 is activated when the signal CS given from the read/write controller 3, which will be described later, is ON.
(“1”) state, perform the above operation,
When the signal CS is OFF (“0”), automatic performance in response to input data is prohibited.

The musical tone signal outputted from the automatic performance circuit 2 is outputted from the speaker 10 via the amplifier 9.

The read/write controller 3 receives the signal F1 from the flag FLAG1 and the flag FLAG2,
F2 is supplied, outputs the output signals E1 and E2, outputs the above signal E1 to the inverter 5 and gives it to the data input device 1 as the signal CS, and also outputs the above signal E1 to the inverter 5.
E2 is sent to the automatic performance circuit 2 as a signal CS.

Input signal of this read/write controller 3
The relationship between F1, F2 and the output signals E1, E2 has six states, as shown in FIG.

That is, while writing data to memory MEMA, reading data from memory MEMB,
This is a state in which the automatic performance circuit 2 generates musical tones.

Conversely, while writing data to memory MEMB, reading data from memory MEMA,
This is a state in which the automatic performance circuit 2 generates musical tones.

is the memory MEMB transferred from data selector 8 while inputting data to memory MEMA.
Since the previous information was change data, the signal E2 was turned OFF (“0”) and the automatic performance was forcibly stopped.

When automatic performance is being performed according to the contents of the memory MEMB, when data has been stored in the memory MEMA and change data is given to the data input device 1, automatic performance is performed according to the contents of the memory MEMB. This is a state in which input of information from the outside is stopped while the system continues.

is the memory MEMA transferred from the data selector 8 while inputting data to the memory MEMB.
Since the previous information was change data, the signal E2 was turned OFF and the automatic performance was forcibly stopped.

When automatic performance is being performed according to the contents of the memory MEMA, data has been stored in the memory MEMB and change data has been given to the data input device 1, and the automatic performance is being performed. This is a state in which information input from the outside is stopped while continuing.

Next, the operation of this embodiment will be described in the case where automatic performance information for the musical score shown in FIG. 3 is inputted from a personal computer to perform automatic performance.

In this case, one measure is the memory - MEMA,
This corresponds to data input information to MEMB once (basic unit), but of course, depending on the capacity of memory-MEMA and memory-MEMB, multiple measures or multiple notes (rests) can be input as one unit. , this unit information may be alternately transferred and inputted to the memory MEMA and the memory MEMB.

In Figure 3, if four characters are one word, for example "D500", the first character is the scale code, and the next character (hexadecimal)
is an octave and its most significant bit is a code that instructs whether to pronounce or mute the sound, and the next two characters represent the time until the next data is processed. In this case, "00" indicates that the next data will be processed immediately. It will have to be processed.

Further, "/y" is a change command, and "S" is a start command.

In the initial state, all the circuits shown in FIG. 1 are initialized, flags FLAG1 and FLAG2 are off, the memory MEMA is in a write state, and the memory MEMB is in a readable state. Also, read/write controller 3
The output E1 is in the ON state, and the output E2 is in the OFF state.

When the information shown in Fig. 3 is transferred from the personal computer, data for one measure is first written to the memory MEMA, and by inputting change data "/y", flag FLAG1 is written.
The contents of are reversed and the state is turned on. As a result, the memory MEMB enters the write state, and the memory
MEMA enters the read state. After that, the automatic performance information for the second measure is written to the memory MEMB, and the contents of the flag FLAG1 are inverted by the change data to turn it into an off state, and then a start command is given to the data input device 1. , a start signal START for starting automatic performance is given to automatic performance circuit 2.

Therefore, in the read/write controller 3, the signal F1 from the flag FLAG1 changes from the ON state to the OFF state, and the signal F2 from the flag FLAG2 changes from the ON state to the OFF state.
As a result, the state shown in FIG. 2 is maintained, so the signal E1 is turned OFF to prohibit data input from the outside, and the signal E2 is turned ON to enable automatic performance. Therefore, first, the first bar is played based on the contents of the memory MEMA.

When the change data "/y" is read from the memory MEMA, the automatic performance circuit 2 outputs a signal _S2 , inverts the contents of the flag FLAG2, and turns it into an ON state. As a result, the signals F1 and F2 input to the read/write controller 3 are turned on and off, respectively, so as shown in FIG.
In addition to executing automatic performance based on the contents of the memory MEMB, it is also possible to input automatic performance information for the third measure into the memory MEMA.

Normally, data is stored in one memory while automatic performance is performed according to the information stored in the other memory, and when the contents of the memory being automatically played are completed, the state is reversed. , continues automatic performance based on the contents of one memory.

By the way, if, for example, while writing data to the memory MEMA, automatic performance according to the contents of the memory MEMB ends and change data is read out, that is, in the state shown in Figure 2, the signal
The read/write controller 3 turns E2 into an OFF state and stops automatic performance. This means that the data input was not in time for automatic performance, resulting in an error condition and the entire performance being stopped.

Of course, the speed at which data is written into memory is much faster than the speed at which data is sequentially read from memory during automatic performance, and such an error condition does not normally occur.

In this way, according to this embodiment, the memory
By temporarily storing the performance information alternately in MEMA and the memory MEMB, and at the same time automatically playing according to the contents of the other memory, there is an advantage that it is possible to realize the automatic performance of a long performance piece.

In the above embodiment, two memories, MEMA and MEMB, are provided, but this means that the storage area of one memory, for example, RAM, is divided into two.
For convenience, it may be configured to serve two memory functions.

Furthermore, although the above embodiments relate to automatic performance when generating scale sounds, the present invention can be widely applied to those generating rhythm sounds (percussion instrument sounds), sound effects, and even human voice sounds. .

In addition to a stand-alone automatic performance device, this invention also provides
It is also applicable to electronic keyboard instruments and other electronic devices.

〔Effect of the invention〕

As described in detail above, this invention enables automatic performance of long pieces regardless of memory capacity, easily realizes orchestra-like performances, and enables automatic performance control to be performed in a desirable manner. It has the effect of becoming.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention; FIG. 1 is a system configuration diagram, FIG. 2 is a diagram for explaining its operating state, and FIG. 3 is a diagram for explaining automatic performance information. 1...Data input device, 2...Automatic performance circuit,
3...read/write controller, 8...data selector, MEMA, MEMB...memory,
FLAG1, FLAG2...Flag.

Claims (1)

[Scope of Claims] 1. Two memory means for temporarily recording transferred automatic performance information; and 2. While writing the automatic performance information into one of the two memory means, The already stored automatic performance information is read from the other memory means, and when the read operation for the other memory means is completed, the write operation and the read operation for the one and the other memory means are performed. a control means for reversing the motion and continuing each motion; and an automatic performance means for performing an automatic performance in accordance with the automatic performance information continuously read from the two memory means under the control of the control means. In an automatic performance apparatus comprising: a first detection means for detecting completion of writing of automatic performance information into one of the two memory means; A second memory means for detecting the end of reading out automatic performance information from the other memory means.
and when the first detection means detects the end of the write, waits until the second detection means detects the end of the read, and then starts a read operation for the one memory means. ,
an operation change timing control means for starting a write operation for the other memory means; and when the second detection means detects the end of the read, the end of the write has not yet been detected by the first detection means. An automatic performance device comprising: error determining means for determining an error and stopping the automatic performance if there is no error.