JPH06160474A - Integrated circuit testing device - Google Patents

Abstract

PURPOSE:To provide an IC tester which can remarkably shorten the total processing time of a waveform digitizer and DSP calculating section required at every test item and can highly efficiently test the analog characteristic of an IC to be tested at a high speed at the time of testing the analog characteristic. CONSTITUTION:The title testing device is provided with a waveform inputting section 12 which generates the testing input of an IC 10 to be tested and supplies the input to the IC 10, memory 14a for storing output data, waveform digitizer 15a which converts the analog output of the IC 10 into digital data and writes the digital data in the memory 14a, DSP calculating section 18a which reads out data from the memory 14a, processes the data, and writes processed data in the memory 14a, and arithmetic and control section 19a which controls the operation of the section 18a so that the section 18a can read out data from the memory 14a and process the data while the digitizer 15a processes the analog output of the IC 10 at every test item.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit tester, and more particularly to an integrated circuit tester for testing an analog output of an integrated circuit under test such as an analog integrated circuit or an analog / digital mixed integrated circuit.

[0002]

2. Description of the Related Art FIG. 9 shows an integrated circuit tester (IC) for testing an analog output of an integrated circuit under test (test IC).
A conventional example of a tester) is shown. This IC tester includes a reference clock generator 11 that generates a clock having a reference frequency.
And the test input of the test IC 10 is generated based on the clock signal from the reference clock generator 11.
A waveform input device 12 to be supplied to one or more input terminals of 0, an output data storage memory 14 for storing data relating to an analog output waveform of the IC under test 10,
Waveform digitizer 15 for converting the analog output of the sample IC 10 into digital data and writing this into the memory 14.
A write pulse generating circuit 16 for generating a write pulse for the memory 14 based on the clock signal from the reference clock generator 11 and supplying the write pulse to the memory 14, and a clock signal from the reference clock generator 11 are appropriate. A write address control circuit 17 which generates a write address of the memory 14 and supplies the write address to the memory 14 in a cycle divided into
A DSP (digital signal processor; digital signal processing) operation unit 1 for reading out data from the memory 14 for arithmetic processing, and writing the data of the processing result in the memory.
8 and an arithmetic control unit 19 that controls the operation of the DSP arithmetic unit 18.

In the DSP computing section 18, the waveform digitizer 15 stores data in the memory 14 for each test item of the sample IC 10.
After all the data has been written into, that is, after the writing of all the data by the waveform digitizer 15, the calculation operation is started.

Therefore, the DSP computing unit 18 for each test item
If the processing time of 1 is not negligible compared with the processing time of the waveform digitizer 15, there is a problem that the total processing time for each test item becomes long. For example, if the processing time of the waveform digitizer 15 for each test item is 5 mS and the processing time of the DSP computing unit 18 is 5 mS, the total processing time for each test item is 10 mS.

FIG. 10 shows another conventional example of the IC tester. The same parts as those of the IC tester shown in FIG. 9 are designated by the same reference numerals. This IC tester is based on the DSP operation unit 18
A CPU (Central Processing Unit) 20 is interposed between the CPU 20 and the memory 14, and the CPU 20 and the DSP arithmetic unit 18
By performing various arithmetic processing by
Of the analog characteristics and the judgment whether the analog characteristics are normal or not are performed.

As the waveform input device 12, the C
An arbitrary waveform data storage memory 22 for storing the arbitrary waveform data calculated by the PU 20 and the DSP calculation unit 18, and an arbitrary analog waveform (for example, a sine wave) generated from the data read from this memory. IC10
It has an arbitrary analog waveform generating section 23 for inputting to.

Further, the digital section 21 includes the CPU 20.
Is provided for transmitting and receiving digital data between the input terminal and the output terminal of the test IC 10, and has a function of determining whether the operation of the test IC 10 is normal.

FIG. 11 shows the waveform input device 1 shown in FIG.
11 shows a conventional example of the arbitrary analog waveform generator included in 2 and the arbitrary analog waveform generator in FIG. Here, 61 is a digital-analog converter for converting the digital data read from the arbitrary waveform data storage memory into an analog waveform signal, and 621 to 62n are selectively provided on the output side of the digital-analog converter 61. Inserted,
An analog filter having different characteristics, 63 is an amplifier that amplifies the input signal from any of the analog filters 621 to 62n, and 64 is an attenuator to which the output signal of the amplifier 63 is input.

FIG. 12 shows a conventional example of the waveform digitizer 15 shown in FIGS. 9 and 10. Where 7
Reference numeral 1 is an amplifier for amplifying the analog output signal of the IC under test 10, 721 to 72n are analog filters selectively inserted in the output side of the amplifier 71 and have different characteristics, and 73 is an analog filter of the analog filters 721 to 72n. It is an analog-to-digital converter that receives a signal from either and converts it into digital data.

However, the conventional arbitrary analog waveform generator shown in FIG. 11 has analog filters 621 to 62n having different characteristics, and the signal-to-noise ratio (S / N) of the test input of the IC 10 under test. , Frequency characteristics, etc. are almost determined by the selection of the analog filters 621 to 62n. Therefore, the analog filters 621 to 62n used in the arbitrary analog waveform generator that requires highly accurate characteristics.
Is expensive, and since many analog filters 621 to 62n are used, the entire IC tester is expensive.

Also in the conventional waveform digitizer shown in FIG. 12, the characteristics of the test output of the IC under test 10 are mostly controlled by the selection of the analog filters 721 to 72n, and many expensive analog filters 721 are used. ~ 7
When 2n is used, there is a problem that the entire IC tester becomes expensive.

Further, in the IC tester shown in FIG. 10, normally, the numerical data stored in the output data storage memory 14 or the arbitrary waveform data storage memory 22 is expressed in an integer format, and the CPU 20 or the DSP arithmetic unit 18 is used. Numerical data processed in is expressed in floating point format.

For this reason, the memory 14 to C has been conventionally used.
At the time of data transfer to the PU 20, the conversion between the integer format and the floating point format is processed by software on the CPU 20 side, so that the processing time becomes long when the transfer data amount is large, and accordingly, the data transfer is performed. Longer times, longer test times.

Further, in the IC tester shown in FIG. 10, when a test that requires a data amount that cannot be stored in the arbitrary waveform data storage memory 22 is performed, the CPU 2
It is necessary to rewrite the stored data in the arbitrary waveform data storage memory 22 by the 0 and the DSP calculation unit 18. When data is transferred from the CPU 20 to the arbitrary waveform data storage memory 22, the conversion between the integer format and the floating point format is processed by software on the CPU 20 side. Longer time, longer data transfer time, longer test time.

Such a problem also exists when data is transferred between the memory 14 and the DSP arithmetic unit 18 in the IC tester shown in FIG. In addition, the IC shown in FIG.
In the tester, the floating point format of the numerical data processed by the CPU 20 and the floating point format of the numerical data processed by the DSP computing unit 18 (floating point number)
Are usually determined by giving priority to the high speed of the arithmetic processing, and thus are often different from each other.

Therefore, conventionally, when data is transferred between the CPU 20 and the DSP operation unit 18, format conversion between different floating point formats is processed by software, so that there is a problem that the data transfer time becomes long. is there.

[0017]

As described above, in the conventional IC tester, after writing the output for each test item of the analog characteristics of the test IC in the memory of the digitizer, the DS
Since the calculation operation of the P calculation unit is started, there is a problem that the total processing time in the digitizer and the DSP calculation unit for each test item becomes long.

Further, since the conventional IC tester uses many expensive analog filters in each of the arbitrary analog waveform generator and the waveform digitizer, there is a problem that the entire IC tester becomes expensive.

Further, the conventional IC tester has a memory and a CP.
When transferring data to or from U or DSP
Since the conversion between the integer format and the floating point format is processed by software, there is a problem that the data transfer time becomes long.

The present invention has been made to solve the above-mentioned problems, and in testing the analog characteristics of a test IC,
It is an object of the present invention to provide an integrated circuit test apparatus capable of testing characteristics at high speed and with high efficiency, by significantly reducing the total processing time required by the waveform digitizer and the DSP computing section for each test item.

It is another object of the present invention to provide an integrated circuit test apparatus capable of reducing the cost of each of the arbitrary analog waveform generator and the waveform digitizer, and the cost of the entire tester. The present invention also provides C
An object of the present invention is to provide an integrated circuit test device capable of speeding up data transfer between the PU and the DSP arithmetic unit and shortening the test time.

[0022]

SUMMARY OF THE INVENTION An integrated circuit test apparatus according to the present invention comprises a waveform input device for generating a test input for an integrated circuit under test and supplying it to the integrated circuit under test, and an analog output waveform of the integrated circuit under test. An output data storage memory for storing data relating to the data, a digitizer for converting the analog output of the integrated circuit under test into digital data and writing the digital data in the memory, and reading the data written in the memory. A digital signal processing arithmetic unit for performing arithmetic processing and writing processing result data to the memory, and an analog output for each test item of the integrated circuit under test provided for controlling the operation of the digital signal processing arithmetic unit. An arithmetic control that controls the digital signal processing arithmetic unit to read and process data from the memory in parallel while the digitizer is processing. Characterized by comprising a device.

[0023]

[Function] The analog output for each test item of the IC under test is processed by the digitizer and the DSP calculation unit for each test item because the DSP calculation unit reads the data from the memory in parallel while the digitizer is processing the analog output. The total processing time required to do this is significantly reduced.

[0024]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an IC tester according to the first embodiment of the present invention. In FIG. 1, the waveform input device generates a test input of the sample IC 10 and supplies it to the input terminal of the sample IC 10.

The output data storage memory 14a has a structure capable of writing the write end information of 1 bit or more together with the data for each address. The waveform digitizer 15a converts the analog output of the sample IC 10 into digital data, and when writing this into the designated address of the memory 14a,
It has a function of adding write end information and writing simultaneously.

The DSP operation unit 18a reads out data with write end information from the memory 14a in parallel while the analog output for each test item of the test IC 10 is being processed by the waveform digitizer 15a, and performs the operation processing, It has a function of writing the processing result data to the memory 14a. That is, the DSP operation unit 18a
The write end information of each address of the memory 14a is checked, and if the content indicates the end of write, the data of the address is read out and the operation step is advanced. However, the reading of the data with the write end information is performed by the waveform digitizer 1.
When it becomes the same as the writing of the data with the writing end information by 5a in time, this writing is prioritized and the reading is performed after the writing is completed.

The arithmetic control unit 19a includes the DSP arithmetic unit 1
8a provided to control the operation of the test IC 1
Analog output for each test item 0
In parallel with the processing by 5a, the DSP operation unit 1
8a has a function of controlling to read and process the data with the write end information from the memory 14a.

That is, in the IC tester shown in FIG. 1, as compared with the conventional IC tester described with reference to FIG. 9, the output data storage memory 14a, the waveform digitizer 15a, the DSP operation section 18a and the operation control section 19a are included. Different, the other parts are the same, and therefore the same reference numerals as in FIG. 9 are given.

Next, as an example of the operation of the IC tester shown in FIG. 1, the DSP operation unit performs an operation for obtaining an average value of data written in, for example, 8192 addresses of the memory 14a for each test item of the test IC 10. The case where 18a performs will be described with reference to FIG.

The DSP computing section 18a is a waveform digitizer 1
During the processing of 5a, the data of the addresses for which writing has been completed among the 8192 addresses is sequentially read, and the sum Σ of the data of each address (data of each address) is obtained. Then, when the writing of the data of all the addresses is completed, Σ (data of each address) / the number of data, that is, Σ (data of each address) / 81
Ask for 92.

Therefore, if the partial operation for obtaining Σ (data of each address) for the data other than the last written data is completed by the time the writing of the data of all the addresses is completed, the data is stored in the memory 14a. The processing of the DSP operation unit 18a after all the data writing is completed only needs to read the last write data for one time, add the read data, and perform one division (÷ 8192).

Such an operation is performed by the conventional DSP arithmetic unit 1 after all the data writing to the memory 14 is completed.
As compared with the operation that requires reading of data for 8192 times, addition of read data, and division of once (÷ 8192) as the processing of 8, the processing time of the waveform digitizer 15a for each test item and the DSP computing unit 18a The total processing time together with the processing time will be greatly reduced.

In the DSP operation unit 18a, an operation for obtaining the effective value of the data written in the 8192 addresses is performed instead of the average value operation or in parallel with the average value operation. In this case, during the processing of the waveform digitizer 15a, the data of the addresses for which the writing has been completed are sequentially read, and the sum Σ (data of each address) ² of the data of each address is obtained. Then, when the writing of data in all addresses has been completed, sigma (data of each address) ^2/81
Find the square root of 92.

Therefore, if the partial calculation for obtaining Σ (data of each address) ² for the data other than the last written data is completed by the time the writing of the data of all the addresses is completed, it is stored in the memory 14a. Processing of the DSP operation unit 18a after all the data writing is completed, the read operation for the last write data is performed once, the read data is squared and added, the division is performed once (÷ 8192), and the square root operation is performed once. It will be enough.

Furthermore, the calculations required to evaluate the characteristics of the analog output of the test IC 10 are not limited to the average value calculation and the effective value calculation as described above, and other various calculations (the peak value is obtained). Etc.) are required, these calculations are also performed in parallel during the processing of the digitizer 15a.
It suffices if the calculation unit 18a performs partial processing.

FIG. 3 is a block diagram showing an IC tester according to the second embodiment of the present invention. As in the IC tester shown in FIG. 3, the waveform digitizer 15b is configured to convert the analog output of the sample IC 10 into digital data and write the same data into the plurality of memories 14a, respectively. Correspondingly, a plurality of DSP arithmetic units 18a and arithmetic control units 19a are provided, and a plurality of memories 14a are provided.
Therefore, if each of the data is read out to the DSP operation unit 18a and a function of performing a plurality of types of operation processing in parallel is provided, it becomes possible to perform more various operations in parallel.

FIG. 4 is a block diagram showing an IC tester according to the third embodiment of the present invention. As in the IC tester shown in FIG. 4, the waveform digitizer 15a, the write pulse generation circuit 16, the write address control circuit 17, the DSP operation unit 18a, and the operation control unit 19a are respectively provided corresponding to the analog outputs of a plurality of systems of the test IC 10. If provided, the above parallel arithmetic processing can be performed for each analog output of each system.

FIG. 5 is a block diagram showing an IC tester according to the fourth embodiment of the present invention. In this IC tester, 14 is an output data storage memory, 15c is a waveform digitizer, 18 is a DSP operation unit, 20 is a CPU, 21 is a digital unit, 22 is an arbitrary waveform data storage memory, and 23c.
Is an arbitrary analog waveform generator.

The CPU 20 and the DSP computing section 18
Is for performing various arithmetic processes in order to evaluate the analog characteristics of the test IC 10 and determine whether the characteristics are correct or not.
The DSP calculation unit 18 uses an FFT (Fast Fourier Transform), DF, etc. which cannot be realized in a practical time by the CPU 20.
The processing such as T (Discrete Fourier Transform) is executed at high speed.

The digital section 21 is controlled by the CPU 20 and is provided for exchanging digital data with the input terminal / output terminal of the sample IC 10, and whether the operation of the sample IC 10 is normal or not. It has the function of making a judgment.

The arbitrary waveform data storage memory 22 is a CP
The arbitrary waveform data arithmetically processed by the U20 and the DSP arithmetic unit 18 is stored. Arbitrary analog waveform generator 23
c has a function of generating an arbitrary analog waveform (for example, a sine wave) from the data read from the arbitrary waveform data storage memory 22 and inputting it to the IC under test 10.

An integer / floating point conversion circuit 24 or a digital filter 25 can be selectively inserted between the CPU 20 and the output data storage memory 14 / arbitrary waveform data storage memory 22. There is.

The integer / floating point conversion circuit 24 has a C
A control signal from the PU 20 can reversibly control conversion of integer → floating point and conversion of floating point → integer. Further, the digital filter 25 is the CPU 20.
The filter operation is performed by arithmetically processing the digital data sampled in time under the control of, that is, the filter characteristic is controlled by the CPU 20 (the low-pass characteristic is set in this example).

An input switching circuit 261 and an output switching circuit 262 for selecting the integer / floating point conversion circuit 24 or the digital filter 25 are provided. The floating point format of the numerical data processed by the CPU 20 and the floating decimal point format of the numerical data processed by the DSP arithmetic unit 18 (floating decimal point number) are determined by giving priority to the high speed of the arithmetic processing. Cage,
In this example, they are different. Therefore, CPU 20 and D
At the time of data transfer with the SP operation unit 18, a floating-point format conversion circuit 27 is inserted to process the format conversion between different floating-point formats by hardware.

This floating point format conversion circuit 27
Is controlled by a control signal from the CPU 20 and is capable of bidirectional conversion of two types of formats.
It is realized by SI.

Since the digital filter 25 as described above is inserted, the number of analog filters used in each of the arbitrary analog waveform generator 23c and the waveform digitizer 15c in FIG. 5 is reduced to one. Is used.

FIG. 6 shows an example of the arbitrary analog waveform generator in FIG. Here, 61 is a digital-analog converter that converts the digital data read from the arbitrary waveform data storage memory 22 into an analog waveform signal, and 62 is inserted at the output side of the digital-analog converter 61 and is a predetermined value. An analog filter with the characteristics of
Reference numeral 63 is an amplifier for amplifying the input of the signal from the analog filter 62, and 64 is an attenuator for receiving the output signal of the amplifier 63.

FIG. 7 shows an example of the waveform digitizer 15c shown in FIG. Here, 71 is an amplifier for amplifying the analog output signal of the IC under test 10, and 72 is this amplifier 71.
An analog filter 73 having a predetermined characteristic is selectively inserted on the output side of the analog input terminal 73, and an analog-digital converter 73 receives the signal from the analog filter 72 and converts it into digital data.

The basic operation of the IC tester of FIG. 5 is as shown in FIG.
The operation is similar to that of the conventional IC tester described above with reference to 0, but the following points are different. That is, when the integer format data is transferred from the CPU 20 to the arbitrary waveform data storage memory 22, the input switching circuit 261 and the output switching circuit 26 are used.
3 is controlled so as to form a path of CPU 20 → digital filter 25 → arbitrary waveform data storage memory 22. At this time, the digital filter 25 is
The filter characteristics are appropriately controlled by the.

When the floating point data is transferred from the CPU 20 to the arbitrary waveform data storage memory 22, the input switching circuit 261 and the output switching circuit 262 use the CPU.
It is controlled so as to form a path of 20 → integer / floating point conversion circuit 24 → arbitrary waveform data storage memory 22.
At this time, the integer / floating-point conversion circuit 24 is controlled by the CPU 20 to perform conversion from floating-point to integer,
Real-time processing becomes possible.

Output data storage memory 14 to CPU 2
When transferring the integer format data to 0, the input switching circuit 261 and the output switching circuit 262 are controlled so as to form a path of the memory 14 → digital filter 25 → CPU 20. At this time, the digital filter 25 is C
The PU 20 appropriately controls the filter characteristics.

Output data storage memory 14 to CPU 2
When the floating point data is transferred to 0, the input switching circuit 261 and the output switching circuit 262 are operated by the memory 14
-> Integer / floating point conversion circuit 24-> CPU 20 is controlled to form a path, and conversion can be performed in real time. At this time, the integer / floating point conversion circuit 24 is controlled by the CPU 20 so as to perform conversion from integer to floating point.

As described above, the integer / floating point conversion circuit 24 or the digital filter 25 is selectively inserted between the CPU 20 and the output data storage memory 14 / arbitrary waveform data storage memory 22. So the CPU
Even if the transfer data amount between the memory 20 and the memories 14 and 22 is large, the data transfer can be speeded up.

Further, since the desired filter characteristic can be realized by using the digital filter 25 which can be realized relatively cheaply as compared with the analog filter, the waveform digitizer 15c can be realized.
Also, the cost of the arbitrary analog waveform generator 23c can be reduced.

In bidirectional data transfer between the CPU 20 and the DSP operation unit 18, the floating point format conversion circuit 27 performs format conversion between different floating point formats in real time.
Data transfer can be speeded up.

In the IC tester shown in FIG. 5,
Between the CPU 20 and the output data storage memory 14 / arbitrary waveform data storage memory 22, in addition to the integer / floating point conversion circuit 24 or the digital filter 25, various data processing circuits are selectively inserted. Modifications are possible as well.

Examples of the above various data processing circuits include a bit inverter for performing code conversion corresponding to a digital-analog conversion / analog-digital conversion code system, a data demodulation circuit, a data compression circuit, and the like.

Also, in the IC tester of the fourth embodiment shown in FIG. 5, in accordance with the IC tester of the first embodiment shown in FIG. 1, the DSP is operated in parallel with the operation of the waveform digitizer 15c.
By controlling the arithmetic unit 18 to perform arithmetic processing,
It goes without saying that the effects similar to those of the IC tester of the first embodiment can be obtained.

FIG. 8 is a block diagram showing an IC tester according to the fifth embodiment of the present invention. This IC tester is shown in Figure 1.
Compared with the IC tester of the first embodiment described above with reference to FIG. 1, the following points are different, and the other points are the same, so the same reference numerals as in FIG.

That is, similar to the IC tester of the fourth embodiment described above with reference to FIG. 5, the DSP arithmetic unit 18a and the memory 1 are used.
An integer / floating-point conversion circuit 24 or a digital filter 25 can be selectively inserted between 4a and 4a.

The integer / floating point conversion circuit 24 can reversibly control the conversion of integer → floating point and the conversion of floating point → integer by the arithmetic control unit 19a. Also,
The filter characteristics of the digital filter 25 are appropriately controlled by the arithmetic control unit 19a.

Then, the above integer / floating point conversion circuit 2
An input switching circuit 261 and an output switching circuit 262 for selecting the digital filter 25 or the digital filter 25 are provided, and these are controlled by the arithmetic control unit 19a.

Since the digital filter 25 as described above is inserted, the test input device 1 in FIG.
The arbitrary analog waveform generator included in 2 is the same as the arbitrary analog waveform generator shown in FIG.
As the waveform digitizer 15a, the same one as the waveform digitizer shown in FIG. 7 is used. It goes without saying that the IC tester of the fifth embodiment shown in FIG. 8 can also obtain the effects similar to those of the IC tester of the fourth embodiment shown in FIG.

[0064]

As described above, according to the IC tester of the present invention, when the analog characteristics of the test IC are tested, the total processing time required by the waveform digitizer and the DSP computing section for each test item is significantly shortened. The characteristics can be tested at high speed and with high efficiency. In addition, the cost of each of the arbitrary analog waveform generator and the waveform digitizer can be reduced, and the cost of the entire tester can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an IC tester according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation example of the waveform digitizer and the DSP arithmetic unit in FIG.

FIG. 3 is a block diagram showing an IC tester according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing an IC tester according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing an IC tester according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram showing an example of an arbitrary analog waveform generating section in FIG.

7 is a block diagram showing an example of the waveform digitizer in FIG.

FIG. 8 is a block diagram showing an IC tester according to a fifth embodiment of the present invention.

FIG. 9 is a block diagram showing an example of a conventional IC tester.

FIG. 10 is a block diagram showing another example of a conventional IC tester.

FIG. 11 is a block diagram showing a conventional example of an arbitrary analog waveform generator in FIGS. 9 and 10.

FIG. 12 is a block diagram showing a conventional example of the waveform digitizer shown in FIGS. 9 and 10.

[Explanation of symbols]

10 ... Test IC, 11 ... Reference clock generator, 12 ... Waveform input device, 13 ... Analog-digital converter, 14,
14a ... Output data storage memory, 15, 15a, 15
b, 15c ... Waveform digitizer, 16 ... Write pulse generation circuit, 17 ... Write address control circuit, 18, 18a ...
DSP operation unit, 19a ... Operation control unit, 20 ... CPU, 2
1 ... Digital section, 22 ... Memory for storing arbitrary waveform data,
23, 23c ... Arbitrary analog waveform generator, 24 ... Integer
Floating point conversion circuit, 25 ... Digital filter, 26
1 ... Input switching circuit, 262 ... Output switching circuit, 27 ... Floating point format conversion circuit.

Claims (9)

[Claims] 1. A waveform input section for generating a test input of an integrated circuit under test and supplying it to the integrated circuit under test, an output data storage memory, and converting an analog output of the integrated circuit under test into digital data. A waveform digitizer that writes this to the memory, and while the waveform digitizer is processing the analog output of each test item of the integrated circuit under test, the data is read from the memory in parallel and arithmetic processing is performed. An integrated circuit test apparatus, comprising: a digital signal processing operation unit for writing the data of 1. into the memory; and an operation control unit provided for controlling the operation of the digital signal processing operation unit. 2. The integrated circuit test device according to claim 1, wherein the digital signal processing operation unit performs a plurality of types of operation processes in parallel. 3. The integrated circuit test apparatus according to claim 1, wherein a plurality of the memories are provided, and the waveform digitizer has a function of writing output data of the integrated circuit under test into the plurality of memories, respectively. A plurality of digital signal processing operation units are provided corresponding to the plurality of memories, and read out output data of the integrated circuit under test from the plurality of memories to perform a plurality of kinds of operation processes in parallel. An integrated circuit test apparatus, wherein a plurality of arithmetic control units are provided corresponding to the plurality of digital signal processing arithmetic units. 4. The integrated circuit test apparatus according to claim 1, wherein the integrated circuit under test has a plurality of analog outputs, and the waveform digitizer and the digital signal processing operation unit ,
A plurality of integrated circuit test devices are provided corresponding to a plurality of analog outputs of the integrated circuit under test. 5. The integrated circuit test apparatus according to claim 1, wherein the waveform input section stores an arbitrary waveform data storage memory for storing arbitrary waveform data, and an arbitrary analog waveform from the data read from the memory. An arbitrary analog waveform generating section for generating and inputting to the integrated circuit under test, the digital signal processing operation section has a function of generating the arbitrary waveform data, the arbitrary waveform data storage memory and output The numerical data stored in the data storage memory is in integer format, the numerical data processed by the digital signal processing operation section is floating point format numerical data, and the digital signal processing operation section and the arbitrary waveform data storage It is inserted between the memory for output and the memory for storing output data, and performs conversion from integer to floating point and from floating point to integer. IC test apparatus characterized by comprising a integer-floating point conversion circuit which processes E A manner. 6. The integrated circuit test apparatus according to claim 1, wherein the waveform input section stores an arbitrary waveform data storage memory for storing arbitrary waveform data and an arbitrary analog waveform from the data read from the memory. An arbitrary analog waveform generating section for generating and inputting to the integrated circuit under test, the digital signal processing operation section has a function of generating the arbitrary waveform data, the arbitrary waveform data storage memory and output The numerical data stored in the data storage memory is in integer format, the numerical data processed by the digital signal processing operation section is floating point format numerical data, and the digital signal processing operation section and the arbitrary waveform data storage Digital memory that is inserted between the memory for output and the memory for storing output data and whose filter characteristics are controlled by the arithmetic control unit. IC test apparatus characterized by comprising a filter. 7. The integrated circuit test apparatus according to claim 1, wherein the waveform input section stores an arbitrary waveform data storage memory for storing arbitrary waveform data, and an arbitrary analog waveform from the data read from the memory. An arbitrary analog waveform generating section for generating and inputting to the integrated circuit under test, the digital signal processing operation section has a function of generating the arbitrary waveform data, the arbitrary waveform data storage memory and output The numerical data stored in the data storage memory is in integer format, the numerical data processed by the digital signal processing operation section is floating point format numerical data, and the digital signal processing operation section and the arbitrary waveform data storage Is selectively inserted between the memory for output and the memory for storing output data, converting from integer to floating point, floating point to integer An integer / floating-point conversion circuit that processes by hardware, and is selectively inserted between the digital signal processing operation unit and the arbitrary waveform data storage memory and output data storage memory, and is operated by the operation control unit. A digital filter whose filter characteristics are controlled, and the integer / floating point conversion circuit or the digital filter are selectively provided between the digital signal processing arithmetic unit and the arbitrary waveform data storage memory and output data storage memory. And a switching circuit for controlling the insertion into the integrated circuit. 8. The integrated circuit test apparatus according to claim 7, wherein the arbitrary analog waveform generator converts digital data read from the arbitrary waveform data storage memory into an analog waveform signal. An analog filter having a predetermined filter characteristic inserted on the output side of the digital-analog converter, an amplifier for amplifying the input of the signal from the analog filter, and an attenuation for the output signal of the amplifier. The waveform digitizer includes an amplifier for amplifying an analog output signal of the integrated circuit under test, an analog filter having a predetermined filter characteristic inserted on the output side of the amplifier, and the analog filter. It is equipped with an analog-digital converter that inputs the signal from and converts it to digital data. An integrated circuit testing device characterized by: 9. The integrated circuit test device according to claim 5, wherein the digital signal processing arithmetic unit and the arithmetic control unit have different floating point format of numerical data. A floating point format conversion circuit is inserted between the digital signal processing operation section and the operation control section, and a format conversion circuit for processing format conversion between different floating point formats is inserted by hardware. An integrated circuit test apparatus characterized by the above.