JPH01308978A - Pattern data generation circuit - Google Patents

Abstract

PURPOSE:To achieve a reduction in switching time between a parallel output and a 1 bit serial output by using a buffer memory with a variable output port to allow the selection of the 1 bit serial output without altering a port width. CONSTITUTION:A port variable buffer memory 1 is so arranged that an internal memory is divided in (n) according to the specified number (n) of output terminals to be allotted to independent I/Os (input/output terminals) and an n-bit input data is outputted in (n) bits. A 1-bit selector 3 receives various stages of count data 9 in parallel from a divided-by (m) notation counter 2 to select and output an output by 1 bit from a corresponding memory 1 connected to a specified gate circuit and produces an output as serial data 11 through an OR circuit. An output switching circuit 4 selects and outputs any one of a parallel output 8 of the memory 1 and the data 11. When the data 11 is selected, it is outputted at specified one terminal adapted to output one bit out of the output 8 while other terminal outputs are fixed at an L level.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern data generation circuit, and more specifically, to a pattern data generation circuit that uses a video RAM (hereinafter referred to as VRAM) in an IC tester.
), etc. This invention relates to an improvement in a pattern data generation circuit suitable for testing a memory having a serial data output such as a serial data output circuit.

[Prior Art] In an IC testing system, a multi-bit test waveform pattern required for two-function testing of IC performance is
A test is performed by automatically generating a test pattern according to a test pattern program, etc., and comparing the output from the IC with an expected value.

In such a case, the test waveform pattern is generated for each pin of tC from the pattern data obtained from the pattern generator and the phase clock signal with multiple phases generated by the timing signal generation circuit. The test pattern is selected and combined to generate a predetermined waveform pattern.The generated test pattern is sent to a drive circuit, and its output is level-converted and supplied to a predetermined IC bin. The resulting IC pin output waveform is then compared with the expected value output from the pattern generator. In this case, when the n1 constant device to be tested is a VRAM, its input data is bit parallel, and its output is bit serial.

Therefore, in a pattern generator, it is necessary to generate an expected value by converting manually generated parallel data into serial data.

[Problem to be solved] As a conventional pattern generator that generates a bit-serial expected value, a ROM pattern generator (ROMPG) is used.
) or serial PG are used, but such pattern generators usually have an output port width of 1.
．． 2,4. ....

A buffer memory that can be changed to 16, . . . is used. However, buffer memory configuration 1:
To generate a 1-bit serial expected value, the data must be configured by +1 so that the boat width becomes 1 bit. To do this, the bit-parallel data in the buffer memorandum is deleted by -1 to generate 1-bit serial data. It is necessary to perform the process of re-storing the .

Therefore, when testing the pattern data generator by changing from parallel data output to serial data output, or when testing while changing from serial data output to +If and parallel data output, etc. The disadvantage is that switching processing takes time and high-speed test processing cannot be performed. In particular, the larger the size of the VRAM, the more time it takes for such switching processing, which becomes a problem.

The present invention solves the problems of the prior art, and allows easy processing of data from various parallel storage data.
It is an object of the present invention to provide a pattern data generation circuit that can generate bit-serial output and can easily perform switching processing between parallel output and 1-bit serial output in a short time.

[To solve the problem - L stage] The configuration of the pattern data generation circuit of the present invention to achieve the first objective is to use a buffer memory whose output port width is variable and a bit parallel configuration of the buffer memory. a 1-bit selection circuit that receives the output and cyclically selects one bit from among the bit outputs of the set output port width; and a 1-bit selection circuit that receives the bit parallel output of the buffer memory and the output of the 1-bit selection circuit and selects one of them. The same address is successively accessed a number of times corresponding to the number of bits of the output port width set in the buffer memory.

[Operation] Using a buffer memory with a variable output port like this, for its 1-bit serial output, you can select 1 bit from the n-bit parallel output (n is a configurable integer) without changing the port width. It is possible to obtain 1-bit serial data by providing a selection circuit that allows the same n-pin parallel data to be output from the buffer memory multiple times in correspondence with the boat width.

As a result, the data in the buffer memory can be changed in real time between n-bit parallel data and 1-bit serial data required for testing, and the switching does not take much time and is fast. Test processing becomes possible.

[Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a pattern data generation circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining its operation.

In FIG. 1, ■ is a port variable width variable buffer memory (hereinafter referred to as buffer memory) in which the number of input/output terminals (the number of I10) is variable and can be set from the outside. This buffer memory 1 is managed so that the internal memory is divided into n parts according to the specified output I10 number H, and each of these n divided memory areas is allocated to an independent I10 port.

As a result, large data of n bits can be received in parallel and output in n bits without changing the total memory capacity.

The buffer memory 1 is accessed from a controller 5 having a CPU (microprocessor), etc. at address 45 and 6.
It operates in response to the operation clock signal 7, and operates in response to the operation clock signal 7.
The bit parallel output 8 is inputted to the 1-bit selector 3 and also inputted to the output switching circuit 4.

The 1-bit selector 3 includes, for example, a gate circuit connected to each output of the buffer memory 1, a decoder, and an OR
It receives count data 9 of each stage in parallel from an m-ary counter 2 whose base number can be set. The output of each stage of the m-ary counter 2 is decoded by the decoder, and a gate circuit at a position specified by the count value is opened. As a result, one bit of the output of the corresponding buffer memory 1 connected to that gate circuit is selected and output. The 1 bit selected by the gate circuit in this way is
It is output as serial data 11 via the R circuit and supplied to the output switching circuit 4. In this case, the m-adic counter 2 receives and counts the operating clock signal 7, and the m-adic counter 2 is set in advance by the controller 5 by a program or the like to correspond to the output width of the buffer memory l. be.

The output switching circuit 4 has an input terminal that receives each output of the buffer memory 1 in parallel and an input terminal that receives the serial output of the 1-bit selector 3.
The parallel output of the 1-bit selector 3 and the output of the serial data 11 of the 1-bit selector 3 are switched, and either the parallel output 8 or the serial data 11 is selected and output. Then, when the output is switched to the serial data 11 side, the serial data 11 is output from a specific terminal that outputs one bit of the parallel output 8, and the output from the other terminals is at a LOW level ( It is fixed at "L" below.

Here, the data stored in buffer memory 1 is 4 bits
) Taking the case of parallel pattern data as an example, the second
The operation will be explained according to the diagram.

First, suppose that the controller 5 sets the output of the buffer memory 1 to 4 bits, and the controller 5
4-bit parallel (4 is 2.4.8.16・φ
It is assumed that the pattern data (selected as one of φ, etc.) is transferred to the buffer memory l and stored in advance at each address.

When the operation clock signal 7 and the access address signal 6 are applied from the controller 5 in the conical shape fi, the buffer memory 1 increments the access address signal 6 (1, 2,
3,...), the stored pattern data (a+
b+ C+ dt...11) is read out, and the output from the 4th bit [1 to n-1 pin 11 is zero level (“L”) tonal.

Therefore, when the output switching circuit 4 is switched to the output side of the buffer memory 1, this is output from the output switching circuit 4 as is.

On the other hand, when generating a 1-bit serial output,
In the above embodiment, the base number of the m-base counter 2 is set to 4 in advance by the controller 5, and the base number of the m-base counter 2 corresponds to the number of bit parallel outputs of the buffer memory l corresponding to the set port width, and the output switching circuit 4 is switched to the serial output 1-bit selector 3 side. In this state, the controller 5 sends the same access address 4 times in response to the generation of the operation clock signal 7.
(corresponding to the output port width of buffer memory 1) and accesses buffer memory 1 each time.

As a result, the pattern data stored at the timing shown in FIG. 2(b) is applied four times in parallel from the buffer memory 1 to the 1-bit selector 3.

The 1-bit selector 3 receives the count data 9 of the m-ary counter 2 counted up in accordance with the operation clock signal 7.
As a result, the parallel data (a
s b, Ct d*・φ・), the data a is sequentially bit by bit from the 0th bit.

Byes... is selected and output.

Therefore, the output selection circuit 4, as shown in FIG.
For example, 1-bit serial pattern data a* b+ Cg d, . . . is sequentially generated at the O-th bit output. Note that since the m-ary counter 2 is in quaternary form in this case, its count value cycles between "0" and "3". As a result, the output of the buffer memory 1 is also sequentially selected so that bits from the 0th bit to the 3rd bit are rotated.

When obtaining 1-bit serial output in this way,
Even if you do not configure the pattern data in Panzer memory l, you can directly transfer the base number of m-adic counter 2 to buffer 1 memory l.
It is possible to generate 1-bit serial pattern data by setting the output selection circuit 4 to correspond to the number of output bits and switching the output selection circuit 4 to the 1-bit serial side. Furthermore, if the switching state is returned to its original state, the pattern data output can be changed back to parallel data output and returned to 11.

As described above, the above embodiment uses 4 bits as an example, but the same effect can be achieved even if the I10 number of the buffer memory is set to 2 bits, 8 bits, 1θ bits, etc. Further, the present invention can be similarly applied by using a buffer memory in which the input setting value and the output setting value can be selected differently. Note that, since a buffer memory in which the number of outputs I10 can be set is used, the configuration of the data manually input to the buffer memory 1 or the data outputted can be freely set from the controller 5 side.

In the embodiment, the selection circuit that selects 1 bit is composed of an m-ary counter and a 1-bit selector, but any circuit that cyclically selects 1 bit from multiple parallel bit outputs may be used. (for example,
The counter may be a shift register.

[Effects of the Invention] As can be understood from the explanation below, this invention uses a buffer memory with a variable output port, and only its 1-bit serial output can be processed without changing the port width. By providing a selection circuit that can select 1 bit from the n-bit parallel output and outputting the same n-bit parallel data from the buffer memory multiple times depending on the port width, 1-bit serial data can be obtained. .

As a result, it is possible to switch between n-bit parallel data and 1-bit serial data required for testing in real time without rewriting data in the buffer memory, and the switching does not take much time, allowing for high-speed testing. processing becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a pattern data generation circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining its operation. 1... Buffer memory, 2... N-ary counter, 3.
...1 bit selector, 4...output switching circuit, 5...
·controller.

Claims (2)

[Claims] (1) Buffer memory with variable output port width,
a 1-bit selection circuit that receives the bit-parallel output of the buffer memory and cyclically selects one bit from among the bit outputs of the set output port width; and the bit-parallel output of the buffer memory and the 1-bit selection circuit. and an output selection circuit that receives an output from the circuit and selects one of the outputs, and the buffer memory is configured such that the same address is successively accessed a number of times corresponding to the number of bits of the set output port width. A pattern data generation circuit featuring: (2) The 1-bit selection circuit includes a 1-bit selector and a counter in which a base number can be set, and the 1-bit selector selects parallel bits of the buffer memory corresponding to the base number according to the count value of the counter. 2. The pattern data generation circuit according to claim 1, wherein one bit of the output is selected cyclically, and the buffer memory is accessed successively to the same address as many times as the base number.