JPH0225567B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a pattern generator that generates high-speed digital patterns with a variable number of bits (bit width).

[Background of the invention]

Digital (logic) pattern generators are used to test logic circuits such as random logic integrated circuits (ICs) and logic memory ICs.

One conventional pattern generator stores predetermined digital patterns required for testing in memory and sequentially reads out the stored digital patterns.
Therefore, the frequency of the pattern is limited to the read speed of the memory IC. However, as logic circuits have become more complex, they have required a greater number of patterns, and as the operating speed of logic circuits has become faster, high-speed patterns have become necessary. However, since large-capacity, high-speed memory does not exist, when generating high-speed patterns using this conventional pattern generator, it is necessary to use a large number of small-capacity, expensive, high-speed memories, making the entire pattern generator expensive and It became large.

Some conventional pattern generators employing an interleave method solve these drawbacks. This sequentially reads out a plurality of memories storing predetermined digital patterns at different phases, and selects output signals from the plurality of memories according to the phase. Thus, the frequency of the final digital pattern will be higher than the readout frequency of each memory, allowing the use of low speed memories to generate high speed patterns. but,
This interleaving method uses slower memory to generate faster digital patterns.
The number of memories must be increased, making the pattern generator large and expensive. Furthermore, it is not possible to change the bit width of the digital pattern, that is, the number of bits, depending on the application.

[Purpose of the invention]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital pattern generator that improves the drawbacks of the interleaving method and generates digital patterns with a variable number of bits at higher speed.

[Summary of the invention]

The digital pattern generator of the present invention employs an interleaving method to obtain parallel digital patterns of multiple bit numbers from a selected one of first and second memories storing predetermined digital patterns. Also, by loading this parallel digital pattern into a shift register and operating the shift register as a parallel input/serial output type, the digital pattern is made even faster. Furthermore, when parallel digital patterns from memory are converted from parallel to serial by a shift register, the number of bits of the digital pattern is controlled by how many times the shift operation is performed per one load operation. Therefore, using a low-speed memory, a digital pattern with a variable number of bits can be obtained faster than the interleaving method.

[Embodiments of the invention]

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a first embodiment of the present invention, and FIG. 2 is a timing diagram for explaining the operation of the block diagram of FIG. A first address counter 10 and a second address counter 12 count clock signals 0/1 and 0/2, respectively, from a timing and control circuit (hereinafter simply referred to as control circuit) 14, which is a control means. Since the phases of these clock signals 0/1 and 0/2 differ by 180 degrees, the phases of the first and second address signals AD1 and AD2 (4 bits) from address counters 10 and 12 also differ by 180 degrees. . The first memory 16 and the second memory 18 each store a predetermined 4-bit parallel digital pattern, and according to the address signals AD1 and AD2, the 4-bit digital patterns DT1 and DT1 and the second memory 18, which are 180 degrees different in phase, are stored.
DT2 is supplied to multiplexer 20. This multiplexer 20 outputs the digital patterns DT1 and DT2 in response to a control signal from the control circuit 14.
The second half of each is selected and the output signal MUX is generated. Therefore, the multiplexer 20 is digital
The response time of the memories 16 and 18 (from receiving the address signal to the digital
(time until the pattern is generated), so low-speed memory can be used. Since there are two memories in this embodiment, the switching frequency of multiplexer 20 is twice the frequency of clock signals 0/1 and 0/2. The configuration and operation up to this point are similar to the conventional interleaving method. In FIG. 1, each numbered connection line is composed of a plurality of connection lines, and the number indicates the number of connection lines. Also the second
In the figure, each of D1 to D12 represents each bit of the digital pattern, and the response time of each block is also considered.

In the present invention, a parallel digital pattern MUX from memory 16 or 18 selected by multiplexer 20 is provided to shift register 22 . In this example, the digital pattern MUX
is 4 bits, so the shift register 22 is composed of four flip-flops F1 to F4, etc.
The parallel outputs are connected to output terminals 24-30.

If the output digital pattern is 1 bit,
Using output terminal 24, shift register 22 performs three shifts while multiplexer 20 switches between memories 16 and 18 to generate digital pattern S/R1. That is, when the multiplexer 20 selects the memory 16 under the control of the control circuit 14, the shift register 22 loads the 4-bit pattern MUX (D1 to D4) (F1
~Load D1 to D4 into F4, respectively). After the response time of shift register 22 has elapsed, output terminal 2
4, D1 occurs. Next, shift register 22
The output terminal 24 is sequentially shifted.
D2, D3, and D4 occur sequentially. Then,
The operating frequency of the shift register 22 is four times the switching frequency of the multiplexer 20 (since the MUX is 4 bits), i.e. 8 times the clock frequency 0/1 and 0/2.
4 clocks constitutes one operation cycle (load operation at the first clock, shift operation at the second to fourth clocks). When multiplexer 20 selects memory 18, MUX becomes D5-D8, and shift register 22 loads MUX, then
Performs a shift operation and outputs D5 to D8 to the output terminal 24.
Output sequentially. Thereafter, the above-mentioned operation is repeated. Therefore, the number of bits of the digital pattern at terminal 24 is
It is one quarter of MUX, but its frequency is MUX
4 times as much. Also, the bit length of this digital pattern can be expanded to the full storage capacity of memories 16 and 18.

If the output digital pattern is 2 bits,
Using output terminals 24 and 28, multiplexer 2
0 switches between memories 16 and 18.
The register performs one shift and places the digital patterns S/R2 and S/R3 on terminals 24 and 28.
occur respectively. That is, the operating frequency of the shift register 22 is four times the clock frequencies 0/1 and 0/2, and there are two clocks, 1 and 2, in which a load operation is performed at the first clock and a shift operation is performed at the second clock.
This is the operating cycle. The frequency of the output digital pattern is thus twice that of the MUX.

When the output digital bits are 4 bits, shift register 22 performs only a load operation synchronized with the switching of multiplexer 20, and acts as a simple buffer. Therefore, output terminals 24 to 3
The digital pattern generated at 0 is the same as MUX. In addition, the multiplexer 20 and the shift
Note that the control signal for register 22 takes into account the response time of each preceding stage. Therefore, according to the present invention, the digital pattern can be produced faster than in the interleaving method, and the number of bits (width) can be easily controlled.

FIG. 3 is a block diagram of a second embodiment of the invention. Timing and control circuit (control means) 14
a clock generator 34 whose oscillation frequency is controlled by a bus (including data lines, address lines, and control lines) 32; a 1/2 frequency divider 36 that divides the frequency of the clock signal from the clock generator 34; 38 and 40, a counter 42 for controlling the load and shift operations of shift register 22, and a latch circuit 44 for latching the control signal on bus 32 and supplying it to a preset terminal P of counter 42.
The bus 32 includes a central processing unit (CPU) 52 such as a microprocessor, and a read-only memory (ROM) 5 that stores control programs and the like.
4. A random access memory (RAM) 56 serving as a temporary storage circuit and a keyboard 58 for various control inputs are connected, and the above-mentioned clock frequency is also controlled by the keyboard 58. Further, since the carry-out C of the counter 42 is connected to the load terminal L thereof, the cycle of occurrence of carry-out can also be controlled by the keyboard 58.

Address counter 10 counts the output signal of frequency divider 40 and supplies the count output to latch circuits 46 and 48 as an address signal (4 bits).
On the other hand, since the carry-out C of the counter 10 is supplied to its load terminal L, the output signal (4 bits) of the latch circuit 50 is latched every time a carry-out occurs. Therefore, the range of address signals generated by the counter 10 can be controlled by the keyboard 58. The output signal of frequency divider 38 is provided through a delay circuit 60 to a differential output buffer 62 whose non-inverted output signal is applied to NOR gates 64 and 66.
It also provides an inverted output signal to NOR gate 68. NOR gate 64 acts simply as an inverter to compensate for the delay times of NOR gates 66 and 68 and controls the latching of latch circuit 46. NOR gates 66 and 68 receive control signals C1 and C2, respectively, from bus 32, and their output signals are wired-ORed to control the latching of latch circuit 48. Since the output clock frequency of amplifier 62 is twice the input clock frequency of counter 10, control signals C1 and C2 are each "high".
and "low", the latch circuits 46 and 48 latch the output signals of the counter 10 with a phase difference of 180 degrees. Therefore, address signals having a phase difference of 180 degrees can be generated. Also, control signals C1 and C2
are "low" and "high" respectively, the latch circuit 46
and 48 simultaneously latch the address signals from counter 10. Note that the delay device 60 adjusts the timing of the output signal of the counter 10 and the latch signal in the latch circuits 46 and 48.

Memories 16 and 18 receive 4-bit address signals from latch circuits 46 and 48, respectively, on address terminals A, 4-bit data from bus 32 on input data terminals I, and 4-bit data from bus 32 on write/read control terminals W/R. A write/read control signal is received from the bus 32, and an output signal from the frequency divider 38 is received at an enable terminal E as an enable signal. Delay device 7
0 adjusts the timing of the address and enable signals provided to memories 16 and 18, and inverter 72 causes memories 16 and 18 to be enabled alternately in synchronization with the address signals. 4-bit digital memory for memories 16 and 18
The pattern is wired-ORed and provided to shift register 22. This shift register 22 receives the carry-out C of the counter 42 via a timing adjustment delay device 74 at a load shift control terminal L/S, and receives the carry-out C of the counter 42 via a timing adjustment delay device 76 at a clock terminal.
4 output clock is received. The embodiment shown in FIG. 3 differs from the embodiment shown in FIG. 18).

To store a predetermined pattern in the memories 16 and 18 in accordance with the control of the keyboard 58, these memories are placed in a write mode and the clock signal from the bus 32 is applied to the output of the frequency divider 38 via a wired-OR connection. do. Every two clocks from bus 32, counter 10 changes the address signal, and memories 16 and 18 are enabled every two clocks. Therefore, it is sufficient to supply digital data from bus 32 to memories 16 and 18 every clock.

To output the digital patterns stored in memories 16 and 18, these memories are placed in read mode and control signals C1 and C2 are set high and low. Further, the keyboard 58 is used to select 1-bit output, 2-bit output, or 4-bit output. In the case of a 1-bit output, CPU 52 loads latch 44 with 1, so counter 42 generates a pulse every four cycles of the clock signal from clock generator 34 and supplies it to shift register 22 as a load signal. For 2-bit output and 4-bit output, latch 2 and 4, respectively.
4, 2 cycles of the clock signal and 1
Shift the load signal to register 22 every cycle
supply to. Other operations are similar to the embodiment shown in FIG. Note that the latch signals supplied to the latch circuits 46 and 48 and the enable signals to the memories 16 and 18 are obtained by frequency-dividing the clock signal of the clock generator 34, so it is assumed that the clock frequency is changed to change the impulse coefficient of the clock signal. (Duty/
Even if the factor) changes to other than 50%, the control signal C
When C1 and C2 are "high" and "low", the operation of the latch circuit and memory will always be 180 degrees out of phase.

In this embodiment, open collector type comparators 78 and 80 are used to perform self-diagnosis.
It includes a circuit 82 that provides a threshold level to the zero inverting input. The non-inverting input of comparator 78 is connected to output terminal 24 and the outputs of comparators 78 and 80 are commonly connected to resistor and bus 32. To test the contents of memories 16 and 18, the pattern generator is placed in 1-bit output mode and the optimal threshold is applied to comparator 78. Further, the threshold value of the comparator 80 is set such that the output stage transistor of the comparator 80 is always in an off state. Therefore, only the logic state of the output terminal 24 is transmitted to the CPU 52 via the bus 32.
Diagnosed by. Note that even though the output signals of memories 16 and 18 total 8 bits, the entire contents of these memories can be diagnosed by taking the test signal from only one location. In this diagnosis, a repeating pattern of a predetermined rule, for example, a repeating pattern of "1" and "0" is stored in a memory, and the diagnosis is made based on whether or not the outputs comply with the predetermined rule. Alternatively, the predetermined patterns may be stored in the memories 16 and 18 and the RAM 56, and the stored contents may be compared. The non-inverting input terminal of the comparator 80 is connected to another appropriate circuit such as the counter 10 and is used for diagnosing that part.

〔Effect of the invention〕

As described above, according to the present invention, the output digital pattern can be produced at a higher speed than the interleaving method, and the number of bits (width) of the output digital pattern can be easily varied.

[Changes to Examples]

Although preferred embodiments of the invention have been described above, those skilled in the art will recognize that various modifications can be made without departing from the spirit of the invention. For example, the third
In the figure, a plurality of pattern generators 84 including memories 16, 18 and shift registers 22 are provided, and these are combined into a single timing and control circuit 14.
The number of bits in the digital pattern may be increased under control. At this time, the upper output bit (MSB) of the shift register 22 of each pattern generation section 84 may be connected to the lower input bit (LSB) of the shift register of the next pattern generation section.
Furthermore, the number of bits in the memory and shift register can be arbitrary, and RAM or the like can be used as the memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a timing diagram for explaining the operation of the block diagram of FIG. 1, and FIG. 3 is a block diagram of a second embodiment of the present invention. be. 14: Control means, 16, 18: Memory, 22:
shift register.

Claims (1)

[Scope of Claims] 1. first and second memories storing predetermined digital patterns; and a shifter provided with a multi-bit parallel digital pattern from a sequentially selected one of the first and second memories. - a register; and control means for controlling load and shift operations of the shift register and selection operations of the first and second memories, the control means controlling one of the first and second memories; Select sequentially,
said shift register repeatedly controls the loading of parallel digital patterns from said selected memory, or sequentially selects one of said first and second memories and said shift register controls said selected memory; loading a parallel digital pattern from a stored memory, repeatedly controlling the operation in which the shift register shifts by a predetermined number of bits less than the number of bits in the shift register, and the shift register does not perform a shift operation; or depending on the number of bits of the shift operation when the shift register performs the shift operation.
A digital pattern generator characterized in that it controls the number of bits of the width of a digital pattern from a register.