JPH1027497A - Memory test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable making simply a program for testing a memory which can read and write data at high speed by providing an address generation function in a memory and generating addresses of the number decided by set burst length. SOLUTION: In a memory test device in which a test pattern is given from a pattern generator 1 to a memory to be tested which is provided with an address generating function inside, its response output is compared with an expected value pattern in a logic comparator 2, a signal indicating defect is stored in the same address as a defect occurrence address of a defect analyzing memory 3 whenever discord is detected and it is used for defect analysis, an address generation section 30 generating the same address as an address generated in the memory is provided in the defect analyzing memory 3, the defect analyzing memory 3 and a memory 4 to be tested can be accessed with the same address without depending on a program for generating a test pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test apparatus for testing a semiconductor memory, and more particularly, to a memory under test having an address generating function inside, and internally providing initial addresses provided from the outside. The present invention relates to a memory test apparatus for testing a memory of a type capable of continuously accessing a memory space by interpolating using an address generation function.

[0002]

2. Description of the Related Art FIG. 5 shows a schematic configuration of a general memory test apparatus. A general memory test apparatus includes a pattern generator 1, a logical comparator 2, and a failure analysis memory 3 that stores a comparison result of the logical comparator 2. The pattern generator 1 supplies a test pattern signal to the memory under test 4,
The test pattern signal is written into the memory under test 4.

The logical comparator 2 compares the read output of the memory under test 4 with the expected value pattern output from the pattern generator 1, detects the occurrence of the mismatch, and detects the presence of a defective memory cell. Then, the presence of the defective cell is stored in the failure analysis memory 3. The failure analysis memory 3 has the same address area as the address area of the memory under test 4, and every time the same address as the memory under test 4 is accessed and a mismatch occurs, for example, “1” is assigned to the address where the mismatch occurs. "A signal indicating a logic failure is stored. Therefore, by reading out the data stored in the failure analysis memory 3, the address of the memory under test where the failure cell exists can be known and used for failure analysis.

By the way, in order to enable high-speed operation, the memory has a built-in address generation function in the memory, and an address (hereinafter referred to as an initial address) which is generated between addresses given one after another (hereinafter referred to as an initial address). A memory (hereinafter referred to as a synchronous DRAM) capable of interpolating by means of an interpolation address and reading and writing a continuous address space.
There is).

In testing this synchronous DRAM, conventionally, an initial address given to a memory under test in a failure analysis memory address signal output from the pattern generator 1, an interpolation address generated inside the memory, and The same address is added and generated, the failure analysis memory is accessed by this address signal, and failure detection data is stored.

Here, the synchronous DRAM will be briefly described. A synchronous DRAM is a synchronous DRAM that inputs an address, data, and a control signal in synchronization with a clock. Compared with a conventional asynchronous DRAM, a synchronous DRAM is used.
Data can be input and output at high speed. 6 and 7
Shows the operation timing. FIG. 6 shows the timing during the write operation. During the write operation, the row address R
0 is fetched into the memory, the column address C0a and the write data Da are fetched by the clock, and the data Da + 1, Da + 2, D
Load a + 3 into memory. Write data Da, Da + 1,
Da + 2 and Da + 3 are continuously written by the number indicated by the burst length (4 in FIG. 6). At this time, the data Da + 1
, Da + 2, Da + 3 need not be input. The addresses for these are automatically generated inside the memory. The burst length is determined by a value written to a register in the memory, and 2, 4, and 8 can be selected.

FIG. 7 shows the timing of the read operation. During a read operation, the row address R0 is fetched into the memory by a clock, and the column address C0a is fetched by a clock. The read data Qa is output in synchronization with the clock with a delay of the number of clocks specified by the CAS latency (3 in FIG. 7) from the clock. Read data Qa + 1, Qa +
2 and Qa + 3 are also successively read out by the number indicated by the burst length (four in the figure) in synchronization with the clock following the clock, similarly to the read data Qa. Also at this time, it is not necessary to input the column addresses for the data Qa + 1, Qa + 2, and Qa + 3. The addresses for these are automatically generated inside the device.

[0008] The address movement is synchronous DRAM
Depends on the type. That is, it differs depending on the burst type. The burst type includes a sequential mode and an interleave mode. The address movement in each mode is shown in FIGS. FIG. 8 shows the address movement of the synchronous DRAM operating in the sequential mode, and FIG. 9 shows the movement of the synchronous DRAM operating in the interleave mode. The movement of these addresses is I
C is predetermined by the manufacturer.

FIG. 10 shows a conventional synchronous DR of this kind.
A test apparatus for testing AM is shown in a configuration focusing on the address of a failure analysis memory. How the address is generated and the fail is stored in this circuit configuration will be described below.
It is assumed that the specifications of the synchronous DRAM to be tested are as follows. Row addresses are X0 to X1 as shown in FIG.
1, 12 bits, column address is Z0, Z1, Y0
12 bits of Y9, burst length 4, CAS latency 3.

The multiplexer 3A includes a pattern generator 1
Has the function of selecting an arbitrary address from the X, Y, and Z addresses given from the memory and setting the same address space as the memory under test 4. In this example, an address signal is selected as shown in FIG. The portion to which the Z addresses Z0 and Z1 are assigned is an address automatically generated inside the memory under test 4.

The cycle delay circuit 3B has a function of delaying an address by an arbitrary cycle. Since the CAS latency is assumed to be 3, the read data Qa is output three cycles after the column address C0a is given to the memory under test 4 as shown in FIG. The fail data corresponding to the read data Qa is also input to the memory section 3C three cycles after the output of the column address C0a by the pattern generator 1, so that the cycle delay circuit 3B delays the address by three cycles, and The cycle with the address of the test memory 4 is matched. If the CAS latency changes, the number of delay cycles here is changed to cope with the change. The memory unit 3C writes fail data to the input address.

[0012]

The pattern generator 1 must generate an interpolation address as shown in FIGS. As is apparent from a comparison between FIG. 8 and FIG. 9, the addresses generated differ between the sequential mode and the interleave mode. The creator who creates the program for generating the test pattern, in addition to programming the address generation program for the failure analysis memory,
Two types of test patterns, one for the sequential mode and one for the interleave mode, must be created, which places a heavy burden on the test pattern creator, and this burden is a major obstacle in testing this type of memory. .

An object of the present invention is to generate an interpolation address generated in a memory under test by hardware to simplify the creation of a program for generating a test pattern and an expected value pattern. is there.

[0014]

According to the present invention, an address generation function is provided in a memory, and this address generation function enables continuous access between externally applied initial addresses by an interpolation address. In the memory test apparatus configured to test the memory configured as described above, an address generation unit that generates the same address as the interpolation address generated inside the memory under test is provided in the failure analysis memory of the memory test apparatus. In this case, an address to be performed is given to the failure analysis memory, and the failure analysis memory is accessed at the same address as the memory under test.

More specifically, according to the present invention, when an address is generated in the memory under test in a sequential mode or an interleave mode, in the sequential mode, the output of all bits is 0.
Or a first counter which is fixed to a state of outputting one of the logics of 1, a second counter which changes a value to be output by +1 each time a clock is supplied from a given initial address, and The address generator is constituted by a gate group for obtaining an exclusive OR for each bit of the output of the second counter and a multiplexer for extracting a signal obtained by the gate group in accordance with a set burst length.

On the other hand, in the interleave mode, the first counter outputs a value which increases by one every time a clock is supplied from a predetermined value, and the second counter is fixed at a state of storing and outputting a given initial value, An exclusive OR operation is performed on the outputs of the first counter and the second counter for each bit, and a signal obtained as a result of the exclusive OR operation according to the set burst length is extracted and output as an address.

Therefore, according to the present invention, the same address as the access operation in the memory under test can be automatically generated in both the sequential mode and the interleave mode. As a result, the creation of a program for generating a test pattern is simplified because it is not necessary to consider the address for accessing the failure analysis memory, and the advantage that this type of memory can be easily tested is obtained.

[0018]

FIG. 1 shows a schematic configuration of a memory test apparatus according to the present invention. Parts corresponding to those in FIG. 10 are denoted by the same reference numerals. A feature of the present invention is that the failure analysis memory 3 is provided with an address generation unit 3D. In this example, the column address (Y address) shown in FIG. 11 is given to the address generator 3D, and the lower 2 to 3 bits of the Y address are fetched as an initial address. Generates the same address as the interpolation address generated inside the.

The address generated by the address generator 3D is transmitted through a multiplexer 3A and a cycle delay circuit 3B.
The address is supplied to the memory unit 3C together with the address.
To the same address as the address of the memory under test 4. FIG. 2 shows a specific embodiment of the address generator 3D. This example shows a case where the burst length is set to a maximum of 8. Therefore, the lower 3 bits of the 12-bit Y address are fetched into the address generator 3D, and the 3-bit Y address is set in accordance with the burst length setting. In the case of 4, the lower 2 bits are changed and output in the same way as the interpolation address, and in the case of 8, all 3 bits are changed in the same way as the interpolation address. An example is shown in which the output is performed after the output.

In FIG. 2, reference numeral 11 denotes a first counter which takes in all three zeros as an initial value, 12 denotes a second counter which takes in the lower 3 bits of a Y address as an initial value, 13 denotes a burst type setting device, and 14 denotes a first type. A group of gates for taking out the outputs of the respective bits of the counter 11 and the second counter 12 by performing an exclusive OR operation.
Numeral 6 denotes an output taken out from the gate group 14 and a multiplexer which takes out the signal of the lower 3 bits of the Y address by dividing the number of bits according to the set burst length.

[0021] The first counter 11 and second counter 12 is used a counter can each presetting the initial value has a data input terminal D _i. That is, the data input terminal D _i of the first counter 11 gives the initial value of all zeros. Thus all zeros of 3 bits per given load instruction pulse P _L to the load terminal LOAD to the first counter 11 is preset.

[0022] The data input terminal D _i of the second counter 12 supplies a signal AD _Y of the lower 3 bits of the Y address. Thus the lower 3 bits of the Y address per this the second counter 12 applied load command pulse P _L is preset. Each of the clock input terminals EN of the first counter 11 and the second counter 12 has the clock C shown in FIGS.
Give LK.

A burst type setting signal WCMD from a burst type setting device 13 is input to each enable terminal EN of the first counter 11 and the second counter 12. The burst type setting unit 13 can be constituted by, for example, a flip-flop. The output terminal Q ₁ on the set side of the flip-flop is connected to the enable terminal E of the first counter 11.
N, and the reset-side output terminal Q ₂ is connected to the enable terminal EN of the second counter 12. Therefore, when the flip-flop constituting the burst type setting unit 13 is set to the reset state, “0” logic is given to the enable terminal EN of the first counter 11 and “1” logic is given to the enable terminal EN of the second counter 12. Can be

The first counter 11 and the second counter 12 are fixed to the loaded state without counting when the enable terminal EN is supplied with "0" logic, and are supplied with the "1" logic when the clock CLK is supplied. The count value changes in a direction of increasing the count value by one from the value loaded in the. As a result, in the above-described example, the first counter 11 is fixed to an all-zero state, and the value of the second counter 12 increases by one from the value of the Y address every time the clock CLK is supplied. FIG.
Shows the situation. The example of FIG. 3 shows a case where the burst length is set to 8 and address 5 is specified as the initial value of the Y address. In this case, the output of the lower three bits “0, 0, 0” of the first counter 11 and the output of the lower three bits of the second counter 12 are exclusive-ORed by the gate group 14 and taken out. As shown in FIG. 3, the contents of the second counter 12 are outputted as they are, and the Y address is outputted from the initial address 5 to the values of 5, 6, 7, 0, 1, 2, 3, and 4. Therefore, it is possible to generate an address that moves in the same manner as the address when the burst length is 8 in the sequential mode shown in FIG. FIG. 3 shows a case where "5" is set as the initial address, but the same operation is performed in other cases. Although the case where the burst length is set to 8 is shown, when the burst length is 2 and 4, the number of bits loaded to the first counter 11 and the second counter 12 is 1 bit when the burst length is 2, and the burst length is 1 bit. Is 4, the operation is the same as that shown in FIG.

FIG. 4 shows an operation state of the address generator 3D in the interleave mode in which the burst length is set to 8. In the interleave mode, 1 logic is input to the enable terminal EN of the first counter 11 and 0 logic is input to the enable terminal EN of the second counter 12. Therefore, the first counter 11 is in a state capable of performing a counting operation, and the second counter 12
Is fixed in the loaded state. The example shown in FIG. 4 shows a case where 5 is initially set in the second counter 12 as an initial address.

The first counter 11 is set to an all-zero value as an initial value, and the count value increases by one each time the clock CLK is input from the all-zero state. When the exclusive OR corresponding to each bit of the first counter 11 and the second counter 12 is calculated, the initial values 5 to 5, 4, 7, 6, 1 are obtained as shown in the output column and the Y address column of the gate group 14. , 0, 3, 2 in this order, and an address in the interleave mode similar to that described with reference to FIG. 9 can be generated.
FIG. 4 shows a case where the burst length is 8 and the initial address is 5, but in other conditions, an interleave mode address can be generated in the same manner as described with reference to FIG.

The output of the gate group 14 is the multiplexer 16
A is input to each input terminal A of A to 16C. Each of the input terminals B of the multiplexers 16A to 16C is supplied with an address signal of the lower 3 bits of the Y address signal. A burst length setting unit 15 is connected to each control terminal of the multiplexers 16A to 16C.
To give a burst length setting signal. When the burst length is 8, "1, 1, 1" is output as the burst length setting signal.
When the logic "1" is applied to the control terminals, the multiplexers 16A to 16C connect the input terminal A to the output terminal C and supply the output of the gate group 14 to the multiplexer 3A. When the burst length is 4, the burst setting unit outputs "0, 1, 1", selects the output of the gate group 14 for the lower 2 bits, and inputs it to the multiplexer 3A. When the burst length is 2, the burst setting unit 15 outputs "0, 0, 1", selects only the lower one bit of the output of the gate group 14, and inputs it to the multiplexer 3A. For the other bits, the Y address signal is selected and input to the multiplexer 3A.

In the multiplexer 3A, the signal is synthesized with the upper bits of the Y address, further synthesized with the X address, and supplied to the cycle delay circuit 3B. Cycle delay circuit 3B
In the example, a delay time corresponding to the delay time of the memory under test 4 is given to the X address signal and the Y address signal, and the delayed address signal is given to the memory section 3C to provide the memory 4 under test.
And access the same address.

The first counter 11 and the second counter 12
In the above-described embodiment, the case where the number of bits to be loaded into the memory is 3 bits has been described. However, the number of bits may be appropriately selected according to the maximum value of the burst length, and the number of bits is not limited. That is, in order to provide versatility, all the bits of the Y address (or the X address) may be loaded into the first counter 11 and the second counter 12, and the count output may be output to the gate group 14 and the multiplexer 16. It is also conceivable to adopt a configuration for taking out by using

[0030]

As described above, according to the present invention, the same address as that generated in the memory is generated by the address generator 3D provided in the failure analysis memory 3, so that the synchronous DRAM test is performed. Can greatly simplify the operation of creating a pattern generation program for performing the above. Therefore, the effect is extremely large for practical use.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an outline of the present invention.

FIG. 2 is a block diagram for explaining a specific embodiment of a main part of the present invention.

FIG. 3 is a diagram for explaining the operation of the main part of the present invention.

FIG. 4 is a diagram for explaining the operation of the main part of the present invention.

FIG. 5 is a block diagram for explaining an outline of a general memory test apparatus.

FIG. 6 is a waveform chart for explaining the operation of the synchronous DRAM.

FIG. 7 is a waveform chart similar to FIG. 6;

FIG. 8 is a diagram for explaining an address generation function of a memory having an address generation function therein;

FIG. 9 is a view similar to FIG. 6;

FIG. 10 is a block diagram for explaining a conventional test apparatus for testing the memory having the address generation function described in FIGS. 6 and 7;

FIG. 11 is a diagram for explaining an example of an address signal handled by the conventional test device described in FIG.

[Explanation of symbols]

 Reference Signs List 1 pattern generator 2 logic comparator 3 failure analysis memory 3A multiplexer 3B cycle delay circuit 3C memory unit 3D address generation unit 4 memory under test 11 first counter 12 second counter 13 burst type setting device 14 gate group 15 burst length setting device 16 multiplexer

Claims (2)

[Claims] 1. A memory test apparatus for testing a memory capable of generating the number of addresses following a given address within an integrated circuit by a number determined by a set burst length, wherein a defective portion of a memory under test is stored. An address generator is provided in the failure analysis memory to be generated, and the same address as the interpolation address generated inside the memory under test is generated by the address generation unit, and the failure analysis memory and the memory under test are made identical by this address. A memory test apparatus characterized in that it can be accessed by an address. 2. The memory test according to claim 1, wherein the address generator sets how many lower bits of the Y address or the X address given to the failure analysis memory correspond to the interpolation address of the memory under test. A burst length setting unit, a burst type setting unit for setting an address generation mode, and a state in which the count value is incremented by one in synchronization with a clock and a state fixed to an all-zero initial setting value by the setting state of the burst type setting unit A first counter which is switched to a state, and a signal of lower-order bits corresponding to the number of bits set in the burst length setting device of the Y address or the X address are initialized, and depending on the setting state of the burst type setting device. The second counter is switched between a state fixed to the initial set value and a state increased by one in synchronization with the clock. , A gate group that takes the exclusive OR of the outputs of the first and second counters in a bit-by-bit manner, and a multiplexer that takes out the output taken out by this gate group by the number of bits set by the burst length setting device. A memory test device, comprising: