JP2008243323A - Semiconductor test device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform high-speed data transfer by fully utilizing a burst property of collection memory in collecting fail data of DUT by memory tester. <P>SOLUTION: A semiconductor test device 100 determines pass/fail by applying a test signal from a data generator 12 to a DUT 40 and comparing the output signal and an expected value at a comparator 51, and improves testing efficiency by performing burst transfer of the fail data obtained at this time to a collection memory 18. Although an address generator 13 generates addresses in accessing the DUT 40 at random seeing form a physical configuration, burst transfer of the fail data can be achieved by fully utilizing the burst property, since this address data is changed into an incremental sequence in address translation section 52. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus for testing a semiconductor device such as a semiconductor memory or an LSI (Large Scale Integration).

  This type of semiconductor test apparatus is used as a memory tester for testing an initial failure of a semiconductor device such as an LSI having a semiconductor memory or an internal memory. A semiconductor test apparatus generally gives a test pattern and an address to which the test pattern is applied to a semiconductor device as an object to be tested (hereinafter referred to as DUT (Device Under Test)), and a signal output from the DUT. Are compared with a predetermined expected value, and pass or fail is judged to test the quality of the DUT.

  Conventional semiconductor test apparatuses usually include a collection memory (fail memory) that collects fail information indicating pass / fail, and collects fail information obtained by performing a DUT test every time in the collection memory. (For example, refer to Patent Document 1). Then, the fail information collected in the collection memory is analyzed, and a redundancy calculation is performed as to whether or not the fail address can be relieved by a spare block in the DUT.

  However, with the conventional technology, new fail information cannot be collected in the collection memory during failure information analysis. Therefore, the next test is performed after waiting for the analysis to finish, and the new test is performed again. Since it is necessary to collect the fail information in the collection memory, it takes a long time for the test.

Therefore, in recent years, an analysis memory is provided separately from the collection memory, and fail information collected in the collection memory is copied (saved) to the analysis memory every time a DUT test is completed, and copied to this analysis memory. There has been proposed a semiconductor test apparatus that performs analysis using the failed information. In such a semiconductor test apparatus, the fail information copied to the analysis memory is used to analyze the DUT after one test, and in parallel with this, the fail information obtained by performing the next DUT test is collected to the memory. Therefore, the test time can be shortened accordingly.
JP 2004-348892 A

  Incidentally, in recent years, semiconductor memories capable of burst transfer have become mainstream in order to increase the speed of data reading and writing. Here, burst transfer refers to a data transfer system in which data of a specified address and data of the next address are transferred continuously only by specifying one address. By using such a data transfer method, it is not necessary to specify addresses one by one when reading and writing continuous data, so that data can be transferred at high speed.

  As described above, in the conventional semiconductor test apparatus, the fail information obtained by performing the DUT test is once collected in the collection memory, and the operation of copying the fail information collected in the collection memory to the analysis memory is repeatedly performed. For this reason, it is desirable for semiconductor test equipment to shorten the time required for testing by efficiently transferring fail information using a memory capable of burst transfer for the collection memory and the analysis memory.

  Even when a memory capable of burst transfer is used as a collection memory and an analysis memory, depending on the type of test for the DUT, a data transfer method in which addresses are specified one by one as in the prior art may be required. . Here, when using a data transfer method in which addresses are specified one by one, it is only necessary to read data from a specified address and write data to the specified address. However, when using a burst transfer method, continuous data Must be read from successive addresses or written to successive addresses (hereinafter referred to as “burst property”). For this reason, in the access control of the collection memory and the analysis memory, it is necessary to specify an appropriate address according to the data transfer method used at that time. In addition, when fail information is stored in the analysis memory, if the fail information is stored in a completely meaningless order, the analysis of the fail information becomes troublesome later. Therefore, it is necessary to store the fail information in some meaningful order (for example, an order that matches the memory map of the DUT) so that the fail information can be easily analyzed later.

  The present invention has been made in view of the above circumstances, and it is possible to shorten the test time by improving the transfer efficiency of fail information and to perform appropriate addressing according to the data transfer method. It is another object of the present invention to provide a semiconductor test apparatus capable of easily analyzing fail information.

  The present invention is a semiconductor test apparatus that performs test of a test target by obtaining fail information indicating a pass or a fail from an output signal of the test target. In particular, in order to solve the above-mentioned problem, the first feature is that an address generation unit for generating a two-dimensional address for obtaining an output signal from a test object and a first conversion for converting the two-dimensional address into a one-dimensional address An address organizing unit that organizes the one-dimensional address output from the first converter, a second converter that converts the one-dimensional address output from the address organizing unit according to a predetermined second conversion rule, A collection memory that collects fail information; and a memory control unit that burst-transfers the fail information to the collection memory using the one-dimensional address converted by the second conversion unit.

  According to the present invention, the two-dimensional address generated by the address generator is output to the test object, and the fail information is obtained from the output signal output from the test object. On the other hand, the two-dimensional address generated by the address generation unit is output to the first conversion unit and converted into a one-dimensional address. The converted one-dimensional address is then rearranged by the address organizing unit, and then converted by the second converting unit so as to be continuous in units of a predetermined number. Then, the fail information is burst transferred to the first memory using the one-dimensional address converted by the second conversion unit. Thereby, the efficiency of collecting fail information in the first memory can be improved, and the test time can be shortened.

  The second feature is that an address generator for sequentially generating a predetermined number of two-dimensional addresses for obtaining an output signal within the access cycle for the test object without overlapping within the predetermined number of ranges, and this address The first conversion unit that converts the two-dimensional address generated by the generation unit into a one-dimensional address according to a predetermined first conversion rule, and the one-dimensional address that is sequentially output from the first conversion unit, the physical configuration of the object to be tested An address organizing unit that arranges corresponding to the order of addresses seen above, and a one-dimensional address that is sequentially output in a state arranged by the address organizing unit is converted according to a predetermined second conversion rule, and is continuously in units of a predetermined number A second conversion unit that outputs a one-dimensional address, a first memory capable of burst transfer for collecting fail information, and a one-dimensional address converted by the second conversion unit Using, it is to include a memory controller for burst transfer to the first memory fail information as a unit of a predetermined number.

  According to the second feature of the present invention, the two-dimensional address generated by the address generator is output to the test object, and the fail information is obtained from the output signal output from the test object. At this time, the address generation unit sequentially generates addresses without overlapping within a predetermined number of ranges. For example, if the predetermined number is n, the addresses generated by the address generation unit may be within a predetermined number range (0, 1, 2,..., N), and the order may be random. That is, if the access to the test object is random, addresses are generated in the access order (however, there is no duplication of addresses within the range of 0 to n).

  On the other hand, the two-dimensional address generated by the address generation unit is output to the first conversion unit and converted by the first conversion rule. If the address generated by the address generation unit is random, the two-dimensional address is converted. One-dimensional addresses are also random. Even in this case, for example, if the last bit of the address has a one-incremental relationship, it is converted into a continuous one-dimensional address in units of a predetermined number, so that the burst by the memory control unit is finally obtained. Fit for transfer.

  However, if the access order for the lower addresses in the physical configuration to be tested is later in time series, the incremental conversion rules cannot later process the lower addresses on the physical configuration. Therefore, in the present invention, when a one-dimensional address is received by the address organizing unit, it is arranged in an incremental order and output to the second converting unit. As a result, when the above fail information is burst transferred to the first memory using the one-dimensional address converted by the second conversion unit, the burst property for the lower address is guaranteed in view of the physical configuration of the test target. Can do.

  That is, in the present invention, the address organizing unit, when the one-dimensional address sequentially output from the first conversion unit does not correspond to the order of the addresses as viewed on the physical configuration of the test object, Sort and output.

  As a result, even if the lower addresses are generated in the access order later in the physical configuration, the lower addresses are rearranged in the order in the burst transfer, so that the first memory is fully utilized by utilizing the burst property. Can be transferred at high speed.

  Therefore, the address generation unit can generate a lower-order two-dimensional address later in time series than a higher-order two-dimensional address in view of the physical configuration of the test target. Since the generation of such an address is arbitrary as long as there is no overlap within a predetermined number of ranges, a burst transfer of fail information to the first memory is possible even when a test by a random access is performed on an object to be tested. Can be done without waste.

  The present invention also provides a second memory capable of burst transfer for saving fail information collected in the first memory, and a save for generating a save address for saving fail information from the first memory to the second memory. An address generation unit and an inverse conversion unit that converts the save address generated by the save address generation unit according to an inverse conversion rule that is an inverse conversion with respect to the second conversion rule may be further provided. In this case, the memory control unit can burst transfer the fail information stored in the first memory to the second memory using the save address reversely converted by the reverse conversion unit.

  With this configuration, the test time can be shortened by efficiently saving fail information from the first memory to the second memory. Further, since the fail information is saved in the second memory so as to match the memory map to be tested by the inverse transformation, the fail information can be easily analyzed.

  According to the present invention, even when fail information is collected by performing random access in which the address order in the physical configuration of the test target and the access order in time series are different, the burst property to the memory that performs the collection is full. It can be used for high-speed data transfer.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the description, first, a basic embodiment in which data transfer is performed using burst characteristics will be described, and then a central embodiment of the present invention will be described.

[First basic embodiment]
FIG. 1 is a block diagram showing the main configuration of a semiconductor test apparatus according to the first basic embodiment. The semiconductor test apparatus 10 of the first basic embodiment is used as a memory tester for testing a DUT 40 such as an LSI having a semiconductor memory device or an internal memory.

  As shown in FIG. 1, the semiconductor test apparatus 10 according to the first basic embodiment includes a timing generator 11, a data generator 12, an address generator 13 (address generation unit), a comparator 14, a copy address generator 15 (evacuation address generation unit), and an address. A conversion unit 16, a collection memory controller 17 (memory control unit), a collection memory (fail memory) 18 (first memory), an analysis memory controller 19 (memory control unit), and an analysis memory 20 (second memory) are provided. . In FIG. 1, only one DUT 40 is illustrated, but the semiconductor test apparatus 10 generally performs testing of a plurality of DUTs 40 at one time.

  The timing generator 11 generates a reference signal that defines the operation timing of the semiconductor test apparatus 10. The reference signal generated by the timing generator 11 is supplied not only to the data generator 12 to the copy address generator 15 and the DUT 40 but also to the inside of the address conversion unit 16 and the collection memory controller 17 to the analysis memory 20 as shown in the figure. The data generator 12 generates an address A1, data D1, and a control signal C1 to be given to the DUT 40 in synchronization with the reference signal generated by the timing generator 11. The data generator 12 generates an address A1 based on the address generated by the address generator 13. The data generator 12 also generates an expected value to be given to the comparator 14.

  The address generator 13 generates an address for designating a specific storage area among a plurality of storage areas of the memory provided in the DUT 40 in synchronization with the reference signal generated by the timing generator 11. Here, since the storage areas of the memory provided in the DUT 40 are generally physically two-dimensionally arranged, the address generator 13 generates a two-dimensional address composed of an X address and a Y address. The data generator 12 generates an address A1 based on this two-dimensional address.

  FIG. 2 is a diagram illustrating an example of a memory space of a memory provided in the DUT 40. Each of the plurality of rectangular areas shown in FIG. 2 represents a storage area for storing one data (for example, 8-bit data), and this storage area has a physical configuration of a two-dimensional array. In FIG. 2, for simplicity of explanation, it is assumed that 64 storage areas are two-dimensionally arranged, and each storage area has a 3-bit X address (X3, X2, X1) and 3 bits. The Y address (Y3, Y2, Y1) is designated. For example, the storage area located at the uppermost leftmost position in the figure is designated by the X address (0, 0, 0) and the Y address (0, 0, 0).

  Returning to FIG. 1, the comparator 14 holds the data D2 output from the DUT 40 at a predetermined timing (strobe signal) synchronized with the reference signal generated by the timing generator 11, and generates the held data D2 and the data generator 12. A pass or fail is determined by comparing with the expected value, and fail data (failure information) D3 indicating the pass or fail is generated. The fail data D3 is output to the collection memory controller 17.

  The copy address generator 15 generates an address A3 used when copying (saving) the fail data collected in the collection memory 18 to the analysis memory 20. Since the addresses of the collection memory 18 and the analysis memory 20 are one-dimensional addresses, the address A3 generated by the copy address generator 15 is a one-dimensional address. The address conversion unit 16 converts the address A 2 generated by the address generator 13 and the address A 3 generated by the copy address generator 15, gives the address A 4 to the collection memory controller 18, and gives the address A 5 to the analysis memory controller 19. Details of the address conversion unit 16 will be described later.

  The collection memory controller 17 outputs a control signal C <b> 2 to the collection memory 18 and controls reading and writing of data with respect to the collection memory 18. Specifically, the fail data D3 output from the comparator 14 is controlled to be written in the storage area specified by the address A4 output from the address converter 16, and at the address A4 output from the address converter 16. Control is performed to read data stored in the designated storage area.

  The collection memory 18 is a memory for collecting fail data D3 obtained by performing the test of the DUT 40 and cumulatively storing fail information over a plurality of tests. Therefore, for the address of the DUT 40 that has been determined to fail even once in the test, even if it is determined to be a pass in subsequent tests, it is necessary to cumulatively hold fail information to the end. Therefore, access control of the collection memory 18 by the collection memory controller 17 is performed in the form of read-modify-write.

  The collection memory 18 is a memory (for example, DRAM) capable of burst transfer. For this reason, the collection memory controller 17 transfers to the collection memory 18 one data for each address (hereinafter referred to as “random transfer mode”) and a plurality of addresses for one address. A transfer mode for transferring data (hereinafter referred to as a “burst transfer mode”).

  The analysis memory controller 19 outputs a control signal C3 to the analysis memory 20, and controls reading and writing of data with respect to the analysis memory 20. Specifically, control is performed to write fail data (fail data read from the collection memory 18) D4 output from the collection memory controller 17 to an address specified by an address A5 output from the address conversion unit 16. . The analysis memory controller 19 also performs read control when analyzing the fail data stored in the analysis memory 20, but a description thereof is omitted here. The analysis memory 20 is for copying the fail data collected in the collection memory 18 in order to analyze the fail data D3 obtained by performing the test of the DUT 40, and is a memory capable of burst transfer. For this reason, the analysis memory controller 19 also has a random transfer mode and a burst transfer mode.

  Next, the address conversion unit 16 that is a main part of the first basic embodiment will be described in detail. As described above, the address conversion unit 16 converts the address A2 generated by the address generator 13 and the address A3 generated by the copy address generator 15, respectively, to the address A4 and the analysis memory controller 19 which are given to the collection memory controller 18. The address A5 to be given is generated.

  Here, as described above, the collection memory controller 17 and the analysis memory controller 19 have a random transfer mode and a burst transfer mode, and an address designation method is different for each transfer mode. Therefore, the address conversion unit 16 converts the address A2 generated by the address generator 13 and the address A3 generated by the copy address generator 15 into addresses suitable for each transfer mode.

  As shown in FIG. 1, the address conversion unit 16 includes an address scrambler 21 (first conversion unit), a burst address scrambler 22 (second conversion unit), a burst address selector 23 (address selection unit), a copy address selector 24, Inverse burst address scrambler 25 (inverse conversion unit), burst address selector 26 (save address selection unit), burst mode setting register 27 (transfer mode setting unit), burst scramble setting register 28 (moving bit setting unit), and burst length A setting register 29 (burst length setting unit) is provided.

  The address scrambler 21 converts the address (two-dimensional address) A2 generated by the address generator 13 based on a predetermined conversion rule to generate a one-dimensional address A11. The address scrambler 21 is provided to convert the two-dimensional address A2 generated by the address generator 13 into a one-dimensional address because the addresses of the collection memory 18 and the analysis memory 20 are one-dimensional addresses.

  For example, when the address A2 generated by the address generator 13 is composed of the 3-bit X address (X3, X2, X1) and the 3-bit Y address (Y3, Y2, Y1) shown in FIG. The scrambler 21 converts it into a 6-bit one-dimensional address (Y3, Y2, Y1, X3, X2, X1) in which the X bit is the lower bit and the Y bit is the upper bit. In the first basic embodiment, this conversion rule will be described as an example. However, the conversion rule of the address scrambler 21 is not limited to this example, and an arbitrary conversion function can be used. The address A11 converted by the address scrambler 21 is output to the burst address scrambler 22 and the burst address selector 23.

  The burst address scrambler 22 converts the address A11 output from the address scrambler 21 so that the burst property is guaranteed when the fail data D3 is written to the collection memory 18 in the burst transfer mode. That is, by converting the address A11 sequentially output from the address scrambler 21, a continuous address A12 is generated with a predetermined burst length as one unit. Specifically, assuming that the variable k is an integer greater than or equal to 1 and the burst length in the burst transfer mode is 2k, a bit whose value changes for every k addresses A11 sequentially output from the address scrambler 21 is Conversion to the k-th bit from the lowest order is performed.

  FIG. 3 is a diagram for explaining the address conversion process performed by the burst address scrambler 22. 3A is an explanatory diagram when the burst length is “2”, and FIG. 3B is an explanatory diagram when the burst length is “4”.

  3A: For example, when the burst length is “2”, the values of the m-th bit of the address A11 sequentially output from the address scrambler 21 are “0”, “1”, “0”, If it is changed to “1”,..., The burst address scrambler 22 moves the m-th bit of the address A11 to the least significant bit, and sets the bit string B1 positioned at the lower order of the m-th bit to 1 The address A12 is generated by performing a conversion that shifts the bits upward.

  3B: Next, when the burst length is “4”, the values of the m-th bit of the address A11 sequentially output from the address scrambler 21 are “0”, “1”, “0”. , “1”,..., And the value of the nth bit of the address A11 is “0”, “0”, “1”, “1”, “0”, “0”, “1”. , “1”,... In this case, the burst address scrambler 22 performs conversion to move the mth bit of the address A11 to the least significant bit and move the nth bit of the address A11 to the second bit counted from the least significant bit. . In addition, the bit string B2 located between the m-th bit and the n-th bit of the address A11 is shifted to the upper side by 1 bit, and the bit string B3 located at the lower order of the n-th bit of the address A11 is shifted by 2 bits. The address A12 is generated by performing the conversion to shift to the side.

  By performing the above conversion, the burst property of the address A12 is guaranteed. Information indicating the bit to be moved is set in the burst scramble setting register 28, and information indicating the burst length is set in the burst length setting register 29. The burst address scrambler 22 performs the above conversion based on the information set in these registers.

  The burst address selector 23 receives the address A11 output from the address scrambler 21 and the address A12 output from the burst address scrambler 22 and inputs the address A11 and the address according to the setting contents of the burst mode setting register 27. Any one of A12 is selectively output. The copy address selector 24 is connected to the burst address selector 23 and the copy address generator 15, and outputs one of the addresses output from these to the collection memory controller 17.

  When the reverse burst address scrambler 25 burst-transfers the fail data collected in the collection memory 18 and copies it to the analysis memory 20, the memory map after being copied to the analysis memory 20 matches the memory map of the DUT 40. Thus, the address A3 output from the copy address generator 15 is converted. Specifically, reverse conversion of conversion performed by the burst address scrambler 22 is performed.

FIG. 4 is a diagram for explaining an address conversion process performed by the reverse burst address scrambler 25. In FIG. 4A, the burst length is “2”.
FIG. 4B is an explanatory diagram when the burst length is “4”.

  4A: For example, when the burst length is “2”, the reverse burst address scrambler 25 moves the least significant bit of the address A3 sequentially output from the copy address generator 15 to move the mth bit. The address A13 is generated by converting the bit string B6 of (m−1) bits positioned higher than the least significant bit of the address A3 to the lower side by 1 bit.

  In FIG. 4B, when the burst length is “4”, the reverse burst address scrambler 25 moves the least significant bit of the address A3 sequentially output from the copy address generator 15 to move the mth bit. A bit is converted to the nth bit by moving the second bit from the least significant bit of the address A3. In addition, the bit string B7 from the (n + 2) th bit to the mth bit of the address A3 is shifted to the lower side by 1 bit, and from the third bit to the (n + 1) th bit counted from the least significant bit of the address A3. The address A13 is generated by performing a conversion that shifts the bit string B8 of 2 bits to the lower side by 2 bits.

  By performing the above conversion, the data sequence rearranged by the conversion of the burst address scrambler 22 when the fail data is collected in the collection memory 18 by burst transfer is restored to the original arrangement that matches the memory map of the DUT 40. Is done. Information indicating the destination bit is set in the burst scramble setting register 28, and information indicating the burst length is set in the burst length setting register 29. The reverse burst address scrambler 25 performs the above conversion based on the information set in these registers.

  The burst address selector 26 receives the address A3 output from the copy address generator 15 and the address A13 output from the reverse burst address scrambler 25 as input, and according to the setting contents of the burst mode setting register 27, the address A3 and One of the addresses A13 is selectively output.

  The burst mode setting register 27 transfers the collection memory controller 17 and the analysis memory controller 19 when fail data is collected in the collection memory 18 or when the fail data stored in the collection memory 18 is copied to the analysis memory 20. Sets the mode. For example, when the value “0” is stored, the random transfer mode is set, and when the value “1” is set, the burst transfer mode is set. The set value of the burst mode setting register 27 is output to the burst address selectors 23 and 26, the collection memory controller 17, and the analysis memory controller 19.

  As described with reference to FIGS. 3 and 4, the burst scramble setting register 28 stores information indicating the destination bit of the address A3 output from the address scrambler A11 and the address A3 output from the copy address generator 15. Information indicating the destination bit is set. Information set in the burst scramble setting register 28 is output to the burst address scrambler 22 and the reverse burst address scrambler 25. The burst length setting register 29 sets information indicating the burst length in the burst transfer mode. Information set in the burst length setting register 29 is output to the burst address scrambler 22 and the reverse burst address scrambler 25, the collection memory controller 17, and the analysis memory controller 19.

  The above is the description of the configuration of the semiconductor test apparatus 10 according to the first basic embodiment. Next, the operation of the semiconductor test apparatus 10 will be described. In general, the semiconductor test apparatus 10 repeatedly performs an operation of writing a test signal to the DUT 40, reading the written test signal, and comparing a predetermined expected value to determine a pass or a fail. Now, the description of the operation at the time of writing is omitted on the assumption that the test signal is already written in the DUT 40, and the operation at the time of reading the test signal will be described in detail.

  Since the semiconductor test apparatus 10 of the first basic embodiment includes the collection memory controller 17 and the analysis memory controller 19 having the random transfer mode and the burst transfer mode, the operation in the random transfer mode and the burst transfer mode will be described below. The explanation will be divided into the operation of time. For easy understanding, it is assumed that the same address is output from the address generator 13 as an address for reading the test signal in any of the random transfer mode and the burst transfer mode. .

  FIG. 5 is a diagram illustrating an example of an address generated by the address generator 13 when the test signal is read. Here, as shown in FIG. 5A, storage areas arranged in a column R1 whose X address is (0, 0, 0) and a column R2 whose X address is (1, 0, 0), respectively. Consider the case where test signals are read alternately from. In FIG. 5, “A”, “B”, “C”, “D”, “E”,... Shown in the rectangular area in FIG. 5 indicate test signals stored in the storage area. Assume that the test signals are sequentially read in the order of the test signals “A” to “P”.

  When the test signals are read in this order, the address generator 13 generates an address shown in (b) of FIG. Specifically, for the Y address, the Y address incremented every two times from (0, 0, 0) is sequentially output, and for the X address, (0, 0, 0) and (1, 0, 0 ) And output alternately. In FIG. 5B, an address A11 obtained by converting the address output from the address generator 13 by the address scrambler 21 is also shown.

<Operation in random transfer mode>
First, in the random transfer mode, the value “0” is set in the burst mode setting register 27. Thus, the burst address selector 23 is set to output the address A11 from the address scrambler 21, and the burst address selector 26 is set to output the address A3 from the copy address generator 15. The transfer mode of the collection memory controller 17 and the analysis memory controller 19 is set to the random transfer mode according to the setting contents of the burst mode setting register 27.

  When the address generator 13 generates an X address (0, 0, 0) and a Y address (0, 0, 0), these addresses are output to the data generator 12 and also output to the address scrambler 21 as an address A2. . In synchronization with the reference signal generated by the timing generator 11, the data generator 12 generates an address A <b> 1 to be given to the DUT 40 based on an address from the address generator 13 and an expected value to be given to the comparator 14. The generated address A1 is output to the DUT 40, and the generated expected value is output to the comparator 14.

  When the address A1 is input to the DUT 40, the test signal “A” stored in the storage area specified by the address A1 is read and output to the comparator 14 as data D2. The comparator 14 holds the data D2 output from the DUT 40 as a strobe signal, compares the held data D2 with the expected value generated by the data generator 12, determines pass / fail, and indicates a fail indicating pass / fail. Data D3 is output. The fail data D3 is output to the collection memory controller 17.

  On the other hand, the address A2 output from the address generator 13 to the address scrambler 21 is converted into a one-dimensional address by the address scrambler 21. Specifically, the X address (0, 0, 0) and Y address (0, 0, 0) generated by the address generator 13 are one-dimensional addresses (0, 0, 0) with the Y address at the top and the X address at the bottom. 0,0,0,0,0). The address A11 converted by the address scrambler 21 is output to the collection memory controller 17 as the address A4 via the burst address selector 23 and the copy address selector 24. The collection memory controller 17 writes the fail data output from the comparator 14 in the storage area of the collection memory 18 indicated by the address A4 output from the address conversion unit 16.

  Next, the address generator 13 generates an X address (1, 0, 0) and a Y address (0, 0, 0). This address is output to the data generator 12 and also output to the address scrambler 21 as an address A2. In synchronization with the reference signal generated by the timing generator 11, the data generator 12 generates an address A1 to be given to the DUT 40 based on the address from the address generator 13, and generates an expected value.

  When the address A1 is input to the DUT 40, the test signal “B” stored in the storage area specified by the address A1 is read and output to the comparator 14 as data D2. The comparator 14 holds the data D2 output from the DUT 40 as a strobe signal, compares the held data D2 with the expected value generated by the data generator 12, determines pass / fail, and indicates a fail indicating pass / fail. Data D3 is output. The fail data D3 is output to the collection memory controller 17.

  On the other hand, the address A2 output from the address generator 13 to the address scrambler 21 is converted into a one-dimensional address by the address scrambler 21. Specifically, the X address (1, 0, 0) and Y address (0, 0, 0) generated by the address generator 13 are converted into a one-dimensional address (0, 0, 0, 1, 0, 0). Is done. The address A11 converted by the address scrambler 21 is output to the collection memory controller 17 as the address A4 via the burst address selector 23 and the copy address selector 24. The collection memory controller 17 outputs the address output from the address conversion unit 16. The fail data output from the comparator 14 is written into the storage area of the collection memory 18 indicated by A4.

  Similarly, every time the address generator 13 generates one address, one test signal is read from the storage area of the DUT 40 specified by the address, and fail data is generated. It is converted by the scrambler 21. Then, fail data is written in the storage area of the collection memory 18 designated by the address converted by the address scrambler 21.

  When the above operation is repeated and the test of the DUT 40 is completed, the operation of copying the fail data collected in the collection memory 18 to the analysis memory 20 is performed. When the address A3 is output from the copy address generator 15, copying of the fail data collected in the collection memory 18 is started. The copy address generator 15 first outputs the head address A3 (for example, 0, 0, 0, 0, 0, 0). The address A3 is output to the collection memory controller 17 as the address A4 via the copy address selector 24 and is output to the analysis memory controller 19 as the address A5 via the burst address selector 26.

  The collection memory controller 17 reads fail data from the storage area of the collection memory 18 specified by the address A4, and outputs the read fail data to the analysis memory controller 19 as data D4. The analysis memory controller 19 writes the data D5 output from the collection memory controller 17 in the storage area of the analysis memory 20 specified by the address A5. When the above processing is completed, the copy address generator 15 outputs the next address A3 (for example, 0, 0, 0, 0, 0, 1). Then, by the same process, one piece of fail data stored in the collection memory 18 is copied to the analysis memory 20. The above operation is repeated and the fail data in the collection memory 18 is copied to the analysis memory 20.

  FIG. 6 is a diagram illustrating an example of the storage contents of the DUT 40, the collection memory 18, and the analysis memory 20 in the random transfer mode. When the one-dimensional address A11 output from the address scrambler 21 is used, the memory map of the DUT 40 can be expressed as the memory map shown on the left side in FIG. That is, the test signals “A”, “B”, “C”, “D”, “E”,... Are sequentially arranged every four addresses from the top address (0, 0, 0, 0, 0, 0). It is a stored memory map.

  When fail data is collected in the collection memory 18 by the above random transfer, the memory map of the analysis memory 20 can be expressed as the memory map shown at the center in FIG. That is, the test signals “A”, “B”, “C”, “D”, “E”,... Every four addresses from the top address (0, 0, 0, 0, 0, 0). .. Is a memory map in which corresponding fail data “FA”, “FB”, “FC”, “FD”, “FE”,.

  When the fail data collected in the collection memory 18 is copied to the analysis memory 20, the memory map of the analysis memory 20 can be expressed as the memory map shown on the right side in FIG. That is, the test signals “A”, “B”, “C”, “D”, “E”,... Every four addresses from the top address (0, 0, 0, 0, 0, 0). .. Is a memory map in which corresponding fail data “FA”, “FB”, “FC”, “FD”, “FE”,. Thus, in the random transfer mode, fail data is collected in the collection memory 18 so as to match the memory map of the DUT 40, and the fail data is copied to the analysis memory 20 so as to match the memory map of the DUT 40.

<Operation in burst transfer mode>
Next, in the burst transfer mode, the value “1” is set in the burst mode setting register 27. Thus, the burst address selector 23 is set to output the address A12 from the burst address scrambler 22, and the burst address selector 26 is set to output the address A13 from the reverse burst address scrambler 25. The transfer mode of the collection memory controller 17 and the analysis memory controller 19 is set to the burst transfer mode according to the setting contents of the burst mode setting register 27.

<Restrictions during burst transfer>
In the random transfer mode described above, any address can be generated by the address generator 13, but in the burst transfer mode, there is a certain restriction on the address generated by the address generator 13. As described above, the burst address scrambler 22 assumes that the variable k is an integer equal to or greater than 1, and the burst length in the burst transfer mode is 2k, for every k addresses A11 sequentially output from the address scrambler 21. Conversion in which the bit whose value changes is counted from the least significant bit to the kth bit is performed.

  For this reason, when the burst length is “2”, the address A11 sequentially output from the address scrambler 21 needs to have bits whose values alternately change for each address. In addition, for the two addresses A11 output continuously from the address scrambler 21, all of the other bits except for the bits whose values change alternately need to be the same. When the burst length is “4”, the address A11 sequentially output from the address scrambler 21 includes a bit whose value changes alternately for each address, and a bit whose value changes for every two addresses. Of the four consecutive addresses, all of the other bits except these bits must be the same.

  For this reason, when fail data D3 is collected in the burst transfer mode, when the address generated by the address generator 13 is first converted into the address A11 by the address scrambler 21, it is confirmed that the above restrictions are met. In addition, the burst length at the time of burst transfer is set in the burst length setting register 29, and information indicating the bits to be moved by the burst address scrambler 22 is set in the burst scramble setting register 28.

  Referring to the address A11 shown in FIG. 5B, the value of the third bit, counting from the least significant bit, changes (0, 1, 0, 1,...) For each address, Excluding this bit, it can be seen that all bits other than two consecutive addresses are the same. Therefore, it can be seen that the X address and the Y address shown in FIG. 5B meet the above-described restrictions and can be collected by burst transfer. In the following description, the value “2” is set in the burst length setting register 29, and “3” is set in the burst scramble setting register 28 as information indicating the bit to be moved by the burst address scrambler 22. To do.

  When the address generator 13 generates an X address (0, 0, 0) and a Y address (0, 0, 0), these addresses are output to the data generator 12 and also output to the address scrambler 21 as an address A2. . In synchronization with the reference signal generated by the timing generator 11, the data generator 12 generates an address A <b> 1 to be given to the DUT 40 based on an address from the address generator 13 and an expected value to be given to the comparator 14. The generated address A1 is output to the DUT 40, and the generated expected value is output to the comparator 14.

  When the address A1 is input to the DUT 40, the test signal “A” stored in the storage area specified by the address A1 is read and output to the comparator 14 as data D2. The comparator 14 holds the data D2 output from the DUT 40 as a strobe signal, compares the held data D2 with the expected value generated by the data generator 12, determines pass / fail, and indicates a fail indicating pass / fail. Data D3 is output. The fail data D3 is output to the collection memory controller 17.

  On the other hand, the address A2 output from the address generator 13 to the address scrambler 21 is converted into a one-dimensional address by the address scrambler 21. Specifically, the X address (0, 0, 0) and Y address (0, 0, 0) generated by the address generator 13 are one-dimensional addresses (0, 0, 0) with the Y address at the top and the X address at the bottom. 0,0,0,0,0). The address A11 converted by the address scrambler 21 is input to the burst address scrambler 22 and converted according to the setting contents of the burst scramble setting register 28 and the burst length setting register 29.

  Specifically, the third bit counted from the least significant address of the address A11 output from the address scrambler 21 is moved to the least significant bit, and the second least significant bit and the second least significant bit of the address A11 are counted. The address A12 is generated by performing conversion that shifts only one bit to the upper side. Here, since the address A11 output from the address scrambler 21 is (0, 0, 0, 0, 0, 0), the address A12 output from the burst address scrambler 22 is also (0, 0, 0, 0, 0, 0). This address is output to the collection memory controller 17 as the address A4 via the burst address selector 23 and the copy address selector 24.

  Next, the address generator 13 generates an X address (1, 0, 0) and a Y address (0, 0, 0). This address is output to the data generator 12 and also output to the address scrambler 21 as an address A2. In synchronization with the reference signal generated by the timing generator 11, the data generator 12 generates an address A1 to be given to the DUT 40 based on the address from the address generator 13, and generates an expected value.

  When the address A1 is input to the DUT 40, the test signal “B” stored in the storage area specified by the address A1 is read and output to the comparator 14 as data D2. The comparator 14 holds the data D2 output from the DUT 40 as a strobe signal, compares the held data D2 with the expected value generated by the data generator 12, determines pass / fail, and indicates a fail indicating pass / fail. Data D3 is output. The fail data D3 is output to the collection memory controller 17.

  On the other hand, the address A2 output from the address generator 13 to the address scrambler 21 is converted into a one-dimensional address by the address scrambler 21. Specifically, the X address (1, 0, 0) and Y address (0, 0, 0) generated by the address generator 13 are converted into a one-dimensional address (0, 0, 0, 1, 0, 0). Is done. The address A11 converted by the address scrambler 21 is input to the burst address scrambler 22 and converted according to the setting contents of the burst scramble setting register 28 and the burst length setting register 29.

  Specifically, the third bit counted from the least significant address of the address A11 output from the address scrambler 21 is moved to the least significant bit, and the second least significant bit and the second least significant bit of the address A11 are counted. Conversion is performed to shift the upper side by 1 bit. As a result, the address (0, 0, 0, 1, 0, 0) output from the address scrambler 21 is converted into an address (0, 0, 0, 0, 0, 1). This address is output to the collection memory controller 17 as the address A4 via the burst address selector 23 and the copy address selector 24.

  With the above processing, the collection memory controller 17 has two addresses (0, 0, 0, 0, 0, 0) and (0, 0, 0, 0, 0, 1), two fail data D3, Is entered. The collection memory controller 17 burst-transfers the two fail data D2 to the collection memory 18 using the previously input address (0, 0, 0, 0, 0, 0), and is designated by the address. Two pieces of fail data are respectively written in a storage area and a storage area continuous with the storage area. Of the two addresses input to the collection memory controller 17, the address input later is discarded.

  Next, the address generator 13 generates an X address (0, 0, 0) and a Y address (0, 0, 1). When this address is output, fail data D3 related to the test signal “C” stored in the DUT 40 is obtained, and the address (0, 0, 1, 0, 0, 0) is obtained by the address scrambler 21 and the burst address scrambler 22. 0) is obtained. Next, when the address generator 13 generates the X address (1, 0, 0) and the Y address (0, 0, 1), fail data D3 relating to the test signal “D” stored in the DUT 40 is obtained, and the address An address (0, 0, 1, 0, 0, 1) is obtained by the scrambler 21 and the burst address scrambler 22.

  Two addresses (0, 0, 1, 0, 0, 0) and (0, 0, 1, 0, 0, 1) and two fail data D3 are input to the collection memory controller 17. . The collection memory controller 17 performs burst transfer of the two fail data D2 to the collection memory 18 using the previously input address (0, 0, 1, 0, 0, 0), and is designated by the address. Two pieces of fail data are respectively written in a storage area and a storage area continuous with the storage area. Of the two addresses input to the collection memory controller 17, the address input later is discarded.

  Similarly, every time the address generator 13 generates an address, one test signal is read from the storage area of the DUT 40 specified by the address to generate fail data, and the address is also converted into an address scrambler. 21 and the burst address scrambler 22 respectively.

  FIG. 7 is a diagram illustrating an example in which the burst address scrambler 22 converts the address A11 into the address A12. As shown in FIG. 7, the third bit moves from the least significant bit of the address A11 to the least significant bit, and the second bit of the address A12 shifted from the least significant bit and the least significant bit of the address A11 is shifted by one bit to the upper side. Is formed. Of the two addresses input to the collection memory controller 17, two fail data are burst transferred to the collection memory 18 using the previously input address, and a storage area designated by the address and its storage Two pieces of fail data are respectively written in a storage area continuous with the area.

  When the above operation is repeated and the test of the DUT 40 is completed, the operation of copying the fail data collected in the collection memory 18 to the analysis memory 20 is performed. When the address A3 is output from the copy address generator 15, copying of the fail data collected in the collection memory 18 is started. The copy address generator 15 first outputs the head address A3 (for example, 0, 0, 0, 0, 0, 0). The address A3 is output to the collection memory controller 17 as the address A4 via the copy address selector 24 and also input to the reverse burst address scrambler 25.

  The reverse burst address scrambler 25 reverses the conversion performed by the burst address scrambler 22 on the address A3 output from the copy address generator 15 according to the settings of the burst scramble setting register 28 and the burst length setting register 29. Perform conversion. Specifically, the least significant bit of the address A3 output from the copy address generator 15 is moved to the third bit counted from the least significant bit, and the second and third bits counted from the least significant bit of the address A3 The address A13 is generated by performing a conversion that shifts bitwise to the lower side bit by bit. Here, since the address A3 output from the copy address generator 15 is (0, 0, 0, 0, 0, 0), the address A13 output from the reverse burst address scrambler 25 is also (0, 0). , 0, 0, 0, 0). This address is output to the analysis memory controller 19 through the burst address selector 26 as the address A5.

  The collection memory controller 17 reads the fail data stored in the storage area of the collection memory 18 specified by the address A4 output from the address conversion unit 16, and uses the read fail data as data D4 to the analysis memory controller 19. Output. The analysis memory controller 19 writes the data D5 output from the collection memory controller 17 in the storage area of the analysis memory 20 specified by the address A5 output from the address conversion unit 16. When the above processing ends, the copy address generator 15 outputs the next address (for example, address (0, 0, 0, 0, 0, 1)) A3. Then, by the same process, one piece of fail data stored in the collection memory 18 is copied to the analysis memory 20. The above operation is repeated and the fail data in the collection memory 18 is copied to the analysis memory 20. Note that the transfer of fail data from the collection memory 18 to the analysis memory 20 is preferably performed by burst transfer.

  FIG. 8 is a diagram illustrating an example of storage contents of the DUT 40, the collection memory 18, and the analysis memory 20 in the burst transfer mode. Similarly to FIG. 6, when the one-dimensional address A11 output from the address scrambler 21 is used, the memory map of the DUT 40 can be expressed as the memory map shown on the left side in FIG. That is, the test signals “A”, “B”, “C”, “D”, “E”,... Are sequentially arranged every four addresses from the top address (0, 0, 0, 0, 0, 0). It is a stored memory map.

  When fail data is collected in the collection memory 18 by burst transfer, the memory map of the collection memory 18 can be expressed as the memory map shown at the center in FIG. That is, the fail data “FB” corresponding to the test signal “B” is stored at the address following the fail data “FA” corresponding to the test signal “A”, and the fail data “FC” corresponding to the test signal “C” is stored. The fail data “FD” corresponding to the test signal “D” is stored at the address following. Similarly, the memory map stores two pieces of fail data every six addresses.

  When the fail data collected in the collection memory 18 is copied to the analysis memory 20, the memory map of the analysis memory 20 can be expressed as the memory map shown on the right side in FIG. That is, in the DUT 40, the test signals “A”, “B”, “C”, “D”, “E”,. Fail data “FA”, “FB”, “FC”, “FD”, “FE”,... Corresponding to “B”, “C”, “D”, “E”,. Memory map. As described above, in the burst transfer mode, when fail data is collected in the collection memory 18, the address conversion is performed so as to guarantee the burst property. However, the fail data collected in the collection memory 18 is analyzed by the analysis memory. When copying to 20, the fail data is copied to the analysis memory 20 so as to match the memory map of the DUT 40.

  In the first basic embodiment described above, the case where one test signal is obtained by applying one address generated by the address generator 13 to the DUT 40 has been described as an example for easy understanding. However, the first basic embodiment can also be applied to a case where a plurality of test results are obtained for one address by operating the DUT 40 in the burst transfer mode.

[Second Basic Embodiment]
FIG. 9 is a block diagram showing a main configuration of a semiconductor test apparatus 50 according to the second basic embodiment of the present invention. In FIG. 9, the same components as those shown in FIG. 1 are denoted by the same reference numerals. The difference between the semiconductor test apparatus 50 of the second basic embodiment and the semiconductor apparatus 10 of the first basic embodiment is that a comparator 51 is provided instead of the comparator 14 shown in FIG. 1, and an address conversion unit is provided instead of the address conversion unit 16. 52.

  The semiconductor test apparatus 10 according to the first basic embodiment described above collects fail data by burst transfer, and improves the collection efficiency of fail data. For this reason, even if the DUT 40 is accelerated to some extent, fail data can be collected efficiently. However, if the operation speed of the DUT 40 is further increased, for example, when the DUT 40 is operated in the burst mode and tested. , Fail data collection may not be able to keep up.

  For this reason, the semiconductor test apparatus 50 of the second basic embodiment includes a comparator 51 that can perform pass / fail judgment at high speed, an address conversion unit 52 that uses the collection memory 18 divided into a plurality of areas, and And testing the DUT 40 in a plurality of times (for example, twice). That is, in the first test, fail data obtained by giving an address to the DUT 40 is thinned out and collected in one area of the collection memory 18, and in the second test, it is the same as the address given to the DUT 40 for the first time. And the remaining fail data is collected in another area of the collection memory 18.

  As the comparator 51, a comparator capable of operating at a high speed about twice or more than the comparator 14 shown in FIG. 1 is used in order to perform a test at a high speed operation of the DUT 40. FIG. 10 is a diagram for explaining the position of the strobe signal in which the comparator 51 holds the data D2 from the DUT 40 in the second basic embodiment.

  Here, since the DUT 40 operates in the burst mode, as shown in FIG. 10, when one address is output from the address generator 13, two data D2 are read from the DUT 40. Specifically, when the address “adrA” in FIG. 10 is (0, 0, 0, 0, 0, 0), the DUT 40 sends a test signal “0” stored in the storage area designated by the address. A ”and a test signal (in this case,“ a ”) stored in the storage area designated by the address (0, 0, 0, 0, 0, 1) following that address continuously Read as data D2. If the address “adrB” in FIG. 10 is (0, 0, 0, 1, 0, 0), the test signal “B” stored in the storage area designated by the address is sent from the DUT 40. The test signal (in this case, “b”) stored in the storage area specified by the address (0, 0, 0, 1, 0, 1) following the address is continuously obtained as data D2. Read out.

  In the first test, the position of the strobe signal of the comparator 51 is set so as to hold the data (test signals “A” and “B”) output first from the DUT 40, and in the second test, after the DUT 40 The position of the strobe signal of the comparator 51 is set so as to hold the output data (test signals “a” and “b”). Therefore, in the first test, fail data (fail data “FA”) for the test signals (test signals “A”, “B”,...) Stored in the storage area specified by the address given to the DUT 40. , “FB”,...) Are obtained by the number of addresses given to the DUT 40. In the second test, fail data (fail data) for the test signals (test signals “a”, “b”,...) Stored in the storage area specified by the address subsequent to the address given to the DUT 40. “Fa”, “Fb”,...) Are obtained by the number of addresses given to the DUT 40.

  The address conversion unit 52 includes a burst address fixing circuit 31 and a fixed bit setting register 32 in addition to the components included in the address conversion unit 16 such as the address scrambler 21 and the burst address scrambler 22 shown in FIG. The burst address fixing circuit 31 is provided between the address scrambler 21 and the burst address scrambler 22, and is used from the address scrambler 21 in order to use the collection memory 18 divided into a plurality of areas in the burst transfer mode. A predetermined conversion is performed on the output address A11 to generate an address A21. Specifically, conversion is performed to fix the value of a predetermined bit of the address A11 to “0” or “1”. The fixed bit setting register 32 sets information indicating a bit whose value is fixed to “0” or “1”.

  FIG. 11 is a diagram for explaining the address conversion process performed by the burst address fixing circuit 31. The burst address fixing circuit 31 fixes the value of the p-th bit of the address A11 to “0” or “1”. For example, in the first test, the value of the p-th bit of the address A11 is fixed to “0”, and in the second test, the value of the bit is fixed to “1”. The bit of the address A11 whose value is fixed is determined according to the pattern generated by the address generator 13 and the position of the strobe signal holding the data D2 by the comparator 51. For example, if the address shown in (b) of FIG. 5 is generated by the address generator 13 and the position of the strobe signal in the comparator 51 is set as described in FIG. Becomes the lower bit.

  When the address shown in (b) of FIG. 5 is generated, the address converter 52 generates the address shown in FIG. FIG. 12 is a diagram showing an example of addresses generated by the address conversion unit 52 in the second basic embodiment of the present invention. In the first test, when the address A11 generated by the address scrambler 21 is input to the burst address fixing circuit 31, the value of the least significant bit is fixed to “0” as shown in FIG. An address A21 is generated. When this address A21 is input to the burst address scrambler 22, the third bit is counted from the least significant bit of the address A21, and the third least significant bit and the least significant bit of the address A11 are counted. An address A12 that has been converted to shift the second bit by one bit to the upper side is generated. Therefore, in the first test, an address A12 is generated in which the value of the second bit counted from the least significant bit is fixed to “0”.

  On the other hand, in the second test, when the address A11 generated by the address scrambler 21 is input to the burst address fixing circuit 31, the value of the least significant bit is “1” as shown in FIG. An address A21 fixed to is generated. When this address A21 is input to the burst address scrambler 22, the third bit is counted from the least significant bit of the address A21, and the third least significant bit and the least significant bit of the address A11 are counted. An address A12 that has been converted to shift the second bit by one bit to the upper side is generated. For this reason, in the second test, an address A12 is generated in which the value of the second bit, counting from the lowest, is fixed to “1”.

  The fail data D3 is collected in the collection memory 18 by using the address A12 output from the burst address scrambler 22. For this reason, in the first test, the fail data D3 is collected in an area specified by an address in which the value of the second bit is fixed to “0” from the lowest order. On the other hand, in the second test, the fail data D3 is collected in an area designated by an address in which the value of the second bit is fixed to “1” counted from the lowest order.

  As described above, in the second basic embodiment, in the first test, fail data regarding a plurality of data obtained by giving addresses to the DUT 40 is thinned out and collected in one area of the collection memory 18, and the second test is performed. In the test, the remaining fail data is collected in another area of the collection memory 18 among the fail data regarding a plurality of data obtained by giving the same address as the address given to the DUT 40 for the first time. For this reason, even when a plurality of pieces of fail data are obtained for one address, the fail data can be burst transferred and collected in the collection memory 18 without omission.

  As described above, in the first and second basic embodiments of the present invention, the fail data D3 is collected after the addresses A11 sequentially output from the address scrambler 21 are converted so as to be continuous in units of a predetermined number. Since the burst transfer is performed with respect to 18, the efficiency of collecting the fail data D3 in the collection memory 18 can be improved, and the test time can be shortened.

  In addition, when the fail data collected in the collection memory 18 is copied to the analysis memory 20, the reverse conversion is performed with respect to the conversion rule used by the address A 3 generated by the copy address generator 15 and the burst address scrambler 22. Conversion is performed according to the reverse conversion rule, and the fail information is copied using this address A5. Therefore, the test time can be shortened, and the fail data can be easily analyzed by copying the fail data to the analysis memory 20 so as to match the memory map of the DUT 40.

  In the first and second basic embodiments of the present invention, the fail data transfer mode can be switched between the burst transfer mode and another transfer mode. Since an address to be given to the analysis memory controller 19 can be selected, it is possible to specify an appropriate address according to the data transfer method.

  Furthermore, in the second basic embodiment of the present invention, when the fail data D3 is collected in the collection memory 18, the collection memory 18 is collected in a plurality of areas. For this reason, when the DUT 40 is tested at high speed, even if the fail data D3 cannot be collected, the fail data D3 is normally collected (without omission) by storing each fail data D3 in another area. be able to.

(Central embodiment)
Based on the configuration of the first and second basic embodiments described above, an embodiment that is central to the present invention will be described below.

  First, the background leading to the central embodiment will be described. In the first and second basic embodiments described above, by adding the burst scramble function using the address scrambler 21 and the burst address scrambler 22, the address A2 generated by the address generator 13 is changed to the incremental address A12 (in two bursts). n, n + 1). As a result, when the fail data is collected by the collection memory 18, an excellent effect is exhibited in that high-speed transfer utilizing burst characteristics is possible.

  By the way, in the test of the DUT 40, since the storage area is randomly accessed, the data at the lower address is not always accessed before in time series due to the physical configuration of the DUT 40. That is, when the access to the lower address is performed after the upper address in time series, the burstiness cannot be fully utilized by the methods of the first and second basic embodiments.

  FIG. 13 is a conceptual diagram illustrating a physical configuration example of the DUT 40. “A” to “D” indicated by the rectangular areas in FIG. 13 indicate data held in the storage area of the DUT 40, and these are “D” → “A” → “B” → It will be taken in order of "C". The vertical direction in FIG. 13 indicates the depth of the physical address, and the data “D” corresponds to the address (0000).

  In this case, the operation when the collection memory 18 is accessed (read-modify-write) in the burst transfer mode by the method of the first and second basic embodiments will be described. FIG. 14 is a diagram illustrating an example of an access operation by burst transfer to the collection memory 18. FIG. 14A shows the rise of the memory clock. In FIG. 14, (B) shows each command of fetching (READ), writing (WRITE), and waiting without doing anything (NOP) of the collection memory controller 17. 14C shows data transferred by the first burst access, and FIG. 14D shows data transferred by the second burst access.

  Here, for example, the collection memory 18 having a bus width that is a half of the bit width of data handled on the physical configuration of the DUT 40 is used, and the burst length is 4 bursts. Further, the lower bits of the data (“OutAL”, “InAL”, etc. in FIG. 14B) and the upper bits (“OutAU”, “InAU”, etc. in FIG. 14B) are processed separately. It shall be.

  In FIG. 14, (C): In the first burst access, fail data D3 corresponding to the data “A” and “B” of the DUT 40 is collected. At this time, the address data transferred to the collection memory 18 is the address of the physical configuration of the DUT 40 with the upper bit doubled and the lower bit doubled with 1 added. Therefore, in the address data transferred to the collection memory 18 by burst access, the lower address “OutAL” is twice the physical address (0001) of the data “A” (0010), and the upper address “OutAU” is the physical address ( (0001) is doubled and 1 is added (0011). Similarly, the lower address “OutBL” is twice the physical address (0010) of the data “B” (0100), and the upper address “OutBU” is twice the physical address (0010) and 1 is added (0101). ). In either case, since the least significant bit has a relationship of “0” and “1”, burst access to the collection memory 18 can be performed satisfactorily.

  In FIG. 14, (D): In the second burst access, fail data D3 corresponding to the data “C” and “D” of the DUT 40 is to be collected. At this time, in the address data transferred to the collection memory 18 by burst access, the lower address “OutCL” is twice the physical address (0011) of the data “C” (0110), and the upper address “OutCU” is the physical address. (0011) is doubled and 1 is added (0111). However, since the address generator 13 generates an address in increments of 1, the address data corresponding to the physical address (0000) of the data “D” cannot be processed in the second burst access.

  In other words, considering the original physical configuration of the DUT 40, the address data expected as the lower address “OutDL” is twice the physical address (0000) of the data “D” (0000), and the upper address “OutDU”. The address data expected as is (0001) obtained by doubling the physical address (0000) and adding 1 to it.

  However, the address data actually transferred to the collection memory 18 is generated based on an address (0100) obtained by incrementing the physical address (0011) of the data “C” by one. Specifically, as shown in one of the regions (reference symbol Z) indicated by a broken line in the figure, the upper address “OutDU” is (1000) that is twice the original address (0100). The lower address “OutDL” is doubled from the original address (0100) and 1 is added (1001). This does not match the original expected address data.

  In the first and second basic embodiments, by providing the address generator 13 with a rule for generating an address by one increment, it is effective in burst transfer of data at consecutive addresses (n, n + 1,...). is doing. However, as shown in FIG. 13 and FIG. 14, when random access is performed with the address depth changing in time sequence, there is overhead somewhere, and the burstiness cannot be fully utilized. There is a case.

  Therefore, in the following central embodiment, in addition to the advantages of the first and second basic forms, the burst property is more fully utilized.

  FIG. 15 is a block diagram showing a main configuration of a semiconductor test apparatus 110 according to the central embodiment of the present invention. In FIG. 15, the same components as those shown in FIG. 9 are denoted by the same reference numerals. Further, in FIG. 15, the notation of the connection lines between the blocks is simplified, but the connection relationship between the blocks is the same as that shown in FIG. The difference between the second basic embodiment and the central embodiment is that the address converting unit 52 includes an address organizing circuit (address organizing unit) 101.

  The address organizing circuit 101 is disposed between the address scrambler 21 and the burst address fixing circuit 31 described above. This address rearrangement circuit 101 rearranges the address data output from the address scrambler 21, rearranges it as necessary, and delivers the output to the burst address fixing circuit 31. For this reason, the address simplification circuit 101 has a built-in cache memory, and the data inputted from the address scrambler 21 can be rearranged after being cached. The address simplification circuit 101 receives fail data D3 from the comparator 51 together with address data.

  FIG. 16 is a schematic diagram illustrating an operation example of the address organizing circuit 101. On the left side in FIG. 16, the physical configuration of the DUT 40 is shown in the order of access time series. As described above, the storage area of the DUT 40 is accessed in the order of “A” → “B” → “C” → “D” for four physical addresses (0000) to (0011) described in 4 bits. In this case, the address in the depth direction generated by the address generator 13 is (0001) → (0010) → (0011) → (0000).

  The addresses are converted by the address scrambler 21 in chronological order and output to the address organizing circuit 101. Further, the fail data D3 corresponding to the data “A” → “B” → “C” → “D” of the DUT 40 is output from the comparator 51 to the address organizing circuit 101 in time series.

  As shown in the center of FIG. 16, the address simplification circuit 101 caches the data “A”, “B”, “C”, “D” received in chronological order, rearranges them in the order of their physical addresses, and outputs them. . As a result, as shown on the right side in FIG. 16, the data “D” and its address are finally stored in the collection memory 18 and become the top data “A ′ (D)” in time series, Hereinafter, the storage configuration of the collection memory 18 is configured in a time-series order of “B ′ (A)”, “C ′ (B)”, and “D ′ (C)”.

  In this case, the operation when the collection memory 18 is accessed (read-modify-write) in the burst transfer mode will be described. FIG. 17 is a diagram illustrating an example of an access operation by burst transfer to the collection memory 18 in the central embodiment. The differences between (A) to (D) in FIG. 17 are the same as (A) to (D) in FIG. The same applies to the setting of the bus width and burst length (4 bursts) of the collection memory 18 and the processing of lower bits and upper bits of data separately.

  (C) in FIG. 17: The address data transferred to the collection memory 18 by the first burst access is the lower address “OutA′L” with respect to the data “A ′ (D)” according to the output order of the address organizing circuit 101. The physical address (0000) of the data “D” is doubled (0000), and the upper address “OutA′U” is doubled the physical address (0000) and 1 is added (0001). In addition, regarding the data “B ′ (A)”, the lower address “OutB′L” is doubled the physical address (0001) of the data “A” (0010), and the upper address “OutB′U” is the physical address ( (0001) is doubled and 1 is added (0011).

  In FIG. 17D, the address data transferred to the collection memory 18 by the second burst access in accordance with the output order of the address organizing circuit 101 is the lower address “OutC′L” with respect to the data “C ′ (B)”. "Is double the physical address (0010) of the data" B "(0100), and the upper address" OutC'U "is double the physical address (0010) and 1 is added (0101). For the data “D ′ (C)”, the lower address “OutD′L” is twice the physical address (0011) of the data “C” (0110), and the upper address “OutD′U” is the physical address. (0011) is doubled and 1 is added (0111).

  As described above, in the central embodiment, since the output order of the address organizing circuit 101 is arranged in the order of addresses incremented by one, transfer is performed during the first and second burst accesses (read / modify / write). There is no discrepancy between the address data to be generated and the address generated by the address generator 13 in the burst transfer mode. Accordingly, the collection memory 18 can collect fail data corresponding to the data “D” and “A” in the first burst access, and the data “B” and “C” are normal in the second burst access. Therefore, burst transfer fully utilizing the burst property can be realized.

  Note that the address organizing circuit 101 does not always have to be rearranged. For example, if the access order of the DUT 40 is in the order of addresses in the physical configuration, the input addresses are arranged in the order of input without being rearranged, and are output as they are.

  The function of the address organizing circuit 101 in the above-described central embodiment can be realized by, for example, a dual port memory. In other words, if data is written to the dual port memory using addresses corresponding to the lower few bits among the addresses on the physical configuration of the DUT 40, reading from the dual port memory is naturally arranged in the order of addresses. ing. Therefore, if necessary, the input data can be rearranged in the order of addresses, and if not particularly necessary, the input data can be output as it is without changing the address order. Further, when a dual port memory is used for the address organizing circuit 101, since the hardware configuration is a dual port, writing and reading can be performed at the same time, and the time overhead can be reduced accordingly. There is.

  The cache size of the address organizing circuit 101 can be changed according to the burst length each time by referring to the information (burst length) in the burst length setting register 29 described above. If the cache size is increased in accordance with the increase of the burst length, the restriction on the data transmission order from the DUT 40 can be relaxed accordingly, and more flexible burst transfer can be realized.

It is a block diagram which shows the principal part structure of the semiconductor test apparatus by 1st basic embodiment of this invention. 4 is a diagram illustrating an example of a memory space of a memory provided in a DUT 40. FIG. 6 is a diagram for explaining address conversion processing performed by a burst address scrambler 22; FIG. 6 is a diagram for explaining address conversion processing performed by an inverse burst address scrambler 25. FIG. It is a figure which shows an example of the address which the address generator 13 generate | occur | produces at the time of the reading of a test signal. It is a figure which shows an example of the memory content of DUT40, the collection memory 18, and the analysis memory 20 at the time of random transfer mode. It is a figure which shows an example in which the burst address scrambler 22 converts the address A11 into the address A12. It is a figure which shows an example of the memory content of DUT40, the collection memory 28, and the analysis memory 20 at the time of burst transfer mode. It is a block diagram which shows the principal part structure of the semiconductor test apparatus by 2nd basic embodiment of this invention. In the second basic embodiment of the present invention, the comparator 51 is a diagram for explaining the position of the strobe signal that holds the data D2 from the DUT 40. FIG. 6 is a diagram for explaining address conversion processing performed in a burst address fixing circuit 31. FIG. It is a figure which shows an example of the address produced | generated by the address conversion part 52 in 2nd basic embodiment of this invention. 2 is a conceptual diagram illustrating a physical configuration example of a DUT 40. FIG. 5 is a diagram illustrating an example of an access operation by burst transfer to the collection memory 18. FIG. It is a block diagram which shows the principal part structure of the semiconductor test apparatus 110 used as center embodiment of this invention. FIG. 3 is a schematic diagram showing an operation example of an address organizing circuit 101. It is a figure which shows the example of access operation by the burst transfer to the collection memory 18 in center embodiment.

Explanation of symbols

10, 50, 100 Semiconductor test equipment 13 Address generator 15 Copy address generator 17 Collection memory controller 18 Collection memory 19 Analysis memory controller 20 Analysis memory 21 Address scrambler 22 Burst address scrambler 23 Burst address selector 25 Reverse burst address scrambler 26 Burst Address selector 27 Burst mode setting register 28 Burst scramble setting register 29 Burst length setting register 31 Burst address fixing circuit 40 DUT
101 Address arrangement circuit

Claims (5)

In a semiconductor test apparatus that performs a test of a test target by obtaining fail information indicating a pass or a fail from the output signal of the test target,
An address generator for generating a two-dimensional address for obtaining the output signal from the test object;
A first conversion unit for converting the two-dimensional address into a one-dimensional address;
An address organizing unit for organizing one-dimensional addresses output from the first conversion unit;
A second conversion unit for converting the one-dimensional address output from the address organizing unit according to a predetermined second conversion rule;
A collection memory for collecting the fail information;
A semiconductor test apparatus comprising: a memory control unit that burst-transfers the fail information to the collection memory using the one-dimensional address converted by the second conversion unit. In a semiconductor test apparatus that performs a test of a test target by obtaining fail information indicating a pass or a fail from the output signal of the test target,
An address generation unit for sequentially generating a predetermined number of two-dimensional addresses for obtaining the output signal within the access cycle for the test object without overlapping within the predetermined number of ranges;
A first conversion unit that converts the two-dimensional address generated by the address generation unit into a one-dimensional address according to a predetermined first conversion rule;
An address organizing unit for organizing the one-dimensional addresses sequentially output from the first converting unit in correspondence with the address order seen on the physical configuration of the test target;
A second conversion unit that converts the one-dimensional addresses sequentially output in a state of being arranged by the address arrangement unit according to a predetermined second conversion rule, and outputs the converted one-dimensional addresses in units of a predetermined number;
A first memory capable of burst transfer for collecting the fail information;
And a memory control unit that burst-transfers the fail information to the first memory in units of the predetermined number using the one-dimensional address converted by the second conversion unit. Test equipment. The semiconductor test apparatus according to claim 2,
The address organizing unit
When the one-dimensional addresses sequentially output from the first conversion unit do not correspond to the order of addresses seen on the physical configuration of the test object, the one-dimensional addresses are rearranged in the order of addresses on the physical configuration and output. Semiconductor test equipment. The semiconductor test apparatus according to claim 2 or 3,
The address generation unit
A semiconductor test apparatus characterized in that a lower two-dimensional address is generated later in time series than a higher two-dimensional address in terms of a physical configuration of an object to be tested. The semiconductor test apparatus according to any one of claims 2 to 4,
A second memory capable of burst transfer for saving the fail information collected in the first memory;
A save address generator for generating a save address for saving the fail information from the first memory to the second memory;
An inverse conversion unit that converts the save address generated by the save address generation unit according to an inverse conversion rule that is an inverse conversion with respect to the second conversion rule;
The memory control unit burst-transfers the fail information stored in the first memory to the second memory using the save address reversely converted by the inverse conversion unit. apparatus.

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