GB2366634A

GB2366634A - Gray code program counter and address compiler

Info

Publication number: GB2366634A
Application number: GB0022202A
Authority: GB
Inventors: Richard Clive Benson
Original assignee: Lucent Technologies Inc
Current assignee: Nokia of America Corp
Priority date: 2000-09-11
Filing date: 2000-09-11
Publication date: 2002-03-13
Anticipated expiration: 2020-09-11
Also published as: GB0022202D0; GB2366634B

Abstract

A reduction in power consumption on an address bus 6 of a computer system including processor 2 and memory 10 is achieved using Gray code. A program counter 4 is connected to the address bus for incrementing the processor through a sequence of memory locations with a minimised hamming distance between consecutive addresses preferably using Gray code. In addition at compile time the compiler/linker 12 places code and data in memory so as to achieve the minimum hamming distance between successive memory locations allowing for system constraints such as available memory space.

Description

2366634 MEMORY ADDRESSING 5 This invention relates to the addressing of

memory associated with a processor in a computer system, for example a digital signal processor.

Processors in integrated circuit form nowadays have various widths of Address bus, ranging up to a common maximum of 64 lines. Each address line has a certain associated bus 10 capacitance, and the total capacitance increases with the address width. This bus capacitance places a constraint on speed of address access and therefore instruction throughput, and more power has to be consumed to drive the address lines.

Various methods have been proposed to reduce the bus capacitance by measures such as 15 reducing the physical size of the address lines and other such process improvements. However, such measures just limit the size of the problem and do not remove the cause of the problem.

Summary of the Invention

The present invention is based on the recognition that since programs often have linear tracts of sequentially numerically increasing addresses, a change from one address to the next address, involving an increment of the program counter, may involve a switch in value of a large number of address lines. Hence, there may be a large switching capacitance to contend 25 with as the address lines change value.

The concept of the invention is to arrange memory contents such that a next instruction in a sequence of instructions stored in memory merely involves changing the address from the current address in one bit, or a minimum number of bits, i.e. - the value of one address line, 30 or a minimum number of address lines. Thus, since only one address line at a time changes when executing a routine, the average value of bus capacitance change is much reduced, whereby power consumption can be reduced, and/or instruction throughput increased, The invention provides, in a first aspect, a computer system including a processor, a memory coupled to the processor by an address bus, and including a program counter for incrementing the processor through a sequence of memory locations, the value of the program counter 5 determining the address value put out on the address bus, and wherein the program counter is arranged to count in a code, wherein each next sequential value of the code is a predetermined hamming distance or less, and less than that of normal binary code, from the current code value.

10 In a finther aspect, the invention provides a method of operating a computer system including a processor, a memory, an address bus for addressing the memory, and a program counter, the value of the program counter determining the address value put out on the address bus by the processor, the method comprising:

the program counter counting through a sequence of values, and the processor addressing a 15 section of memory in accordance with the values, and the program counter counting in a code such that the hamming distance between consecutive values of the code and hence consecutive values on the address bus, is minimised having regard to the constraints imposed by the computing system.

20 In accordance with convention, the hamming distance between a first binary code value and a second binary code value is defined as the number of bits of each code in which the value of the code differs. Thus, for an n-bit long code having n locations and the value at each location being a 1 or a 0, there may be a hamming distance anywhere between I and n, if no steps are taken to reduce the hamming distance..

As preferred, the code employed in the program counter has a minimum hamming distance between sequential values of the code, e.g. - a hamming distance of one. Thus, the program counter increments its count far at least part of a routine with a change of as little as one bit, or code element value, at a time. A code with a constant hamming distance of I is known as a 30 Gray code.

For the purposes of the present specification, the term "normal binary code" should be understood as the code usually employed in computer systems where numbers are expressed as polynomials to the radix 2, with sequential values of the normal binary code being created

5 by incrementing the least significant bit.

When programs are executed, it is common to require a jump from one section of code to another, in a different section of memory. As preferred, in accordance with the invention, the address to which a jump takes place is less than a predetermined hamming distance from the 10 current address. Thus, two sections of code may be placed in separate sections of memory at compile/linking time, and a number of constraints will be employed to determine the respective memory locations, such as available memory space. In accordance with-the invention, a further constraint is employed in that the addresses between which jumps may take place have a minimum, or at least reduced, hamming distance between them. The 15 numerical value of the minimal hamming distance will be determined by the various constraints, e.g. size of memory, amount of memory available for use, etc, etc.

Further aspects of the invention are set forth in the appended claims.

20 In accordance with a further preferred form of the invention, a maximum hamming distance for code values on the address bus is specified. If a change in address from one address value to the next placed on the address bus involves a change greater than the maximum hamming distance, then the processor is delayed to achieve a delay, for example by inserting one or more processor 'wait' states to permit the address bus, with its associated capacitance, to 25 settle, before the memory location is read. Clearly, if the processor speed has been increased to take advantage of the minimal hamming distances of the address code, then a larger hamming distance occurring may cause mistiming and faulty operation.

The present invention is applicable to computer systems of any architecture, for example, the 30 Von Neumann architecture with a single data bus and a single address bus which addresses memory containing both data and executable code. The Harvard architecture has separate address and data buses for data and code respectively.

4 Brief Description of the Drawings

A preferred embodiment of the invention will now be described, merely by way of example, with reference to the accompanying drawings, wherein:

5 Figure 1 is a schematic view of a computer system including a program counter for addressing memory, for use in explaining the invention; Figure 2 is a schematic view of address lines connecting the program counter to memory; Figure 3 is an illustration of address bus skew arising from bus capacitance; and Figure 4 is a schematic view of code generation flow, for use in explaining the invention.

Description of the Preferred Embodiment

Referring to Figure 1, there is shown a processor 2 having a program counter (PC) 4. The processor 2 is coupled via address lines 6 to the address decoding section 8 of a memory 15 section 10. The address value put out on address line 6 is determined by the number held in program counter 4. A linker 12 is part of the software tools for the system and at an initial stage, assembles instructions and data into memory section 10 prior to the execution of the instructions. The PC holds an address value, which is put out on address bus 6 to the address decode section 8. Every execution cycle of the processor 2 causes PC 4 to increment, and the 20 processor to read and interpret the data and code held in memory 10 at the address matching the contents of the PC. In the prior art, PC 4 causes the address bus 6 to default to increment in the decimal order 0, 1, 2, 3, 4, 5 etc, unless it were required to look at another memory location for some reason, such as the program code has to perform a jump, or if the code requires data to be fetched from another memory location.

Referring to Figure 2, when the processor 2 accesses memory 10 it does so by taking the binary value contained in PC 4, such as Ob 10 11 and converting this to a voltage representation on a set of wires AO, Al, A2, etc, constituting address bus 6. As shown, each wire has an associated capacitance Co..C, In this example, assuming positive logic levels, based around 0 30 and 5 Volts:

wire AO is driven to 5 Volts, this represents the least significant bit; wire Al is driven to 5 Volts; wire A2 is driven to 0 Volts-, and wire A3 is driven to 5 Volts, this represents the most significant bit If the PC 4 now increments the address bus 6 to the next sequential binary value (Ob 1100) it has to change A2 to 5V, change Al & AO to OV. Since, as shown in Figure 2, each of these wires has an associated capacitance C associated with it, significant amount of power will 5 therefore be consumed when changing the logic state.

In accordance with the invention, the operation of the program counter is optimised to increment in such a way as to save power, and in certain conditions to raise the processor's maximum operating frequency.

The hamming distance between two binary values is defined as the number of binary digits (bits) that differ between the two values e.g. - ObOOOO 0001 and ObOOOO 1100 have a hamming distance of three since three of their digits differ.

15 To minimise the power consumed when incrementing the address bus, in accordance with the invention the code is ordered not as addresses 0, 1, 2, 3, 4 but as a set of addresses that have a minimum hamming distance. Such a code scheme is known as Gray code, which has the characteristic that there is a hamming distance of I between each consecutive value, eg:

20 ObOOOO ObOO01 ObOO11 ObOO10 ObO110 25 ObO111 ObO101 ObOlOO ObIlOO ObllO1 30 Obllll ObllIO ObIO10 OblOll OblO01 35 OblOOO With the rule being that to generate each new value in the series, only one bit should change.

In accordance with the preferred embodiment of the invention, the system of Figure I works in the above indicated way, providing two significant changes to previous processor design:

5 1 the program counter 4 is designed to count in Gray code sequence, rather than unit incremental sequence (0, 1, 2, 3, 4, etc.) ("normal binary code"); and 2. the linker 12 arranges the code to reside in memory at locations matching the Gray code sequence, as shown in the following example:

Prior Art Order Proposed Order

Address Value held at this address AddressValue held at this address ObOOOO Instruction I ObOOOO Instruction I ObOO01 Instruction 2 ObOO01 Instruction 2 ObOO10 Instruction 3 ObOO 10 Instruction 4 ObOO I I Instruction 4 ObOO I I Instruction 3 ObOlOO Instruction 5 ObO 100 Instruction 8 Etc. Etc.

Having code increment by changing the voltage on as few wires as possible also has the advantage that the time spent waiting for all the wires to change to their final value is not as 15 long. Referring to Figure 3, the time taken for the whole address bus (AO to A3) to achieve its final value takes from the time the value was initially asserted (W) to the time when the value has finally changed (t4) is t4-tO. In some cas es (eg - for processors that have wide address busses) this can be the limiting factor in the frequency that the processor can be clocked at. So in accordance with the preferred embodiment of the invention, where there is 20 normally only one wire changing its value from eg - 5V to OV or vice versa, this waiting time to allow for wires not changing value at precisely the same time is minimised.

In a practical situation, code would not be able to achieve the goal of only ever changing to change I bit, due to, for example, code discontinuities or data fetches. But linker 12 is aware 25 of all hamming distances in the code, and can therefore calculate the worst case. in practice, a statistical analysis would be made of hamming distances, with the best and worst cases computed together with an average value, and deviations from the average value. So if the processor speed was limited by the addess bus skew assuming all bits were changing, then it 7 is possible to characterise a different overall skew time for N bits changing (N being the worst case possible hamming distance as output from the linker), therefore allowing the overall processor clock speed to be increased.

5 In accordance with the invention, code can be compiled and linked by Compiler/Assembler/Linker software tools into an executable that is optimised for minimum power consumption. This permits significant power savings to be obtained through software tools alone.

10 In Figure 2, a differentiator unit 30 is provided coupled to the address bus and arranged to detect changes in address code greater than a maximum hamming distance. This maximum hamming distance value will be predetermined. If such an excessive hamming distance is detected, differentiator block 30 provides a signal to the processor to achieve a delay, for example by inserting one or more 'wait' states, according to the detected hamming distance, 15 to allow the address bus to settle before memory is read.

Referring to Figure 4 of the drawings, a schematic is shown of a number of files S1, S2 Sn are compiled in a compiler 14 into executable code forming object files 01, 02 On. A linker 16 gives the executable code physical memory locations and provides appropriate links between 20 code locations. A memory 18 is indicated with code locations 20 distributed in the memory In the prior art, code, that is in a state where it can be loaded into a processor's memory, is generated in two stages.

25 1. The source file(s) that contain the high level language statements, are compiled, to give assembly files, containing irmemomics for the processor base instructions.

2. These assembly files are then linked to produce I large executable file, which has areas that are split into data that is suitable for putting into RAM, data suitable for 30 ROM, code and uninitialised areas.

In accordance with the invention, the linker 16 is modified so as to place the code and data in memory 18 so as to ensure that jumps between code locations have a minimal hamming distance.

Figure 4 shows the memory 18 with the code and data distributed in sections 181-183 containing executable code in contiguous sections, and sections 184-186 contain read only data, and sections 187-189 contain read/write data. These areas are defined either by default 5 or by a "map file" which has varying degrees of detail. In accordance with the invention, the link-er 16 parses the code looking for either data fetches, program discontinuities or any other situations where the processor has to look at an area of memory that is non-contiguous with the value held in its program counter, and when it finds these conditions, it minimises the hamming distance, e.g.:

Address Pseudo Instruction Comment ObOOOO 0001 Fetch variable "A" ObOOOO 0010 Is "A">l? ObOOOO 0011 Yes - Jump to point B Jump if true ObOOOO 0100 Etc- If not true execution will carry on here ObOOOO 0 111 More instructions Point B Ob 1000 0001 10 Value of variable A In this pseudo code in accordance with the invention, the link-er achieves, as an example: when the processor fetches variable A it has been placed a hamming distance of I away (i.e. - 15 1 bit is different in the address), and if the code has to jump to point B then the linker has been able to place this a hamming distance of 1 away.

Placing a hamming distance of I away may not always be possible (for example, a 20 compromise between several locations accessing the same variable may have to be reached), but significant power savings are made by minimising the distance, between all relevant locations.

The following example is given of a software process mechanism in accordance with the invention, including a compile and linking fimction which minimises hamming distance.

5 Example

1. Default to Gray code for linear contiguous code sections.

2, (CONTELATION) Analyse all potential discontinuities.

Code Line Instruction/Data 1 A 2 B 15 3 C 4 D 5 E N z Instruction C represents a jump to Z.

Instruction E represents a jump to Z.

3. (LRTKAGE) Place C and E IN SUCH ADDRESSES THAT THEY ARE A MINEVIAL HAMMING DISTANCE, FROM Z.

Alternatively, the map file should specify that the code should be placed at certain locations -that are a minimum hamming distance apart. This would not require the linker to be changed 30 at all, and could be considered as a style of code development, that could apply to any processor and linker.

If using Von Neumann or shared bus architecture then all discontinuities be they code or data appear on the same bus, so all hamming distances should be minimised. If using separate busses (as in a Harvard architecture) hamming distances are minimised for consecutive 5 activity on the data bus, and the hamming distances for program discontinuities are separately minimised, Although a Program counter is described which counts in a Gray code so that only one bit changes at a time, i.e. a minimum hamming distance code, it is within the scope of the 10 invention to have codes which change with a hamming distance of more than one, say two or three, so that code changes are permitted with two or three code element values changing at a time.

Where discontinuities occur in code address requiring a jump between different code 15 segments, the start address of the code segments are arranged a minimal hamming distance from one another by the linker. The linker will have to take into account various parameters or constraints of the system, for example, available memory when determining where to place the separate code segments.

20 Thus, in accordance with the invention, due to the fact that very few (typically one) address lines change their value at a time, power consumption will be reduced. The other main benefit is that potential bus skew is reduced and therefore the rate at which the device advances its program counter can be increased. Thus, the instruction speed of the processor could be increased, if the address bus skew was a limiting factor in maximum clock speed.

Claims

1. A computer system including a processor, a memory coupled to the processor by an 5 address bus, and including a progrwn counter for incrementing the processor through a sequence of memory locations, the value of the program counter determining the address value put out on the address bus, and wherein the program counter is arranged to count in a code, wherein each next sequential value of the code is a predetermined hamming distance or less, and less than that of normal binary code, from the current 10 code value.

2. A computer system according to claim 1, wherein the predetermined hamming distance is 1, and the code is a Gray code.

3. A system according to claim I or 2, including a process means for arranging at code build time, data and code in memory, and including means for arranging that when the processor executes the code, sequential address values are a 'minimum hamming distance away from each other.

4. A computer system according to any preceding claim, including means coupled to the address bus for determining whether a transition between consecutive memory location is more than said predetermined hamming distance, and including means for slowing processor access times in dependence on such determination.

5. A method of operating a computer system including a processor, a memory, an address bus for addressing the memory, and a program counter, the value of the program counter determining the address value put out on the address bus by the processor, the method comprising:

the program counter counting through a sequence of values, and the processor 30 addressing a section of memory in accordance with the values, and the program counter counting in a code such that the hamming distance between consecutive values of the code and hence consecutive values on the address bus, is minimised having regard to the constraints imposed by the computing system.

6. A method according to claim 5, wherein the program counter counts in a Gray code.

7. A method according to claim 5 or 6, comprising arranging at code build time, data and 5 code in memory, such tha- iequential address values are a minimised hamming distance away from each other, having regard to the constraints imposed by the computing system.

8. A method according to any of claims 5 to 7, including assessing a maximum hamming 10 distance which will occur in operation, and speeding up the processor having regard to this maximum.

9. A computer system including a processor, a memory coupled to the processor by address and data buses, and a process means for arranging at code build time, data and 15 code in memory, such that when the processor executes the code, sequential address values are a minimised hamming distance away from one another.

10. A process means for a computer system, for arranging at code build time, data and code in memory, such that when the processor executes the code, sequential address 20 values are a minimised hamming distance away from one another.

11, A method of operating a computer system comprising a processor, a memory and an address bus for addressing the memory coupled to the processor by address and data buses, 25 wherein the method comprises, at compile time, arranging code and data in memory in a predetermined order, including examining the hamming distances occurring between addresses of sequentially addressed memory locations, and arranging at least a section of the data and/or code in memory in order to minimise said hamming distance.

12. A method of operating a computer system comprising a processor, a memory and an address bus for addressing the memory coupled to the processor by address and data buses, 5 wherein the method comprises, at compile time, arranging code and data in memory in a predetermined order, wherein the linker arranges the data and code in memory according to a map file, so as to reduce the hamming distances occurring between addresses of sequentially addressed memory locations.

10

13. A computer system as claimed in claim 1, and substantially as described with reference to the accompanying drawings.

14. A method of operating a computer system as claimed in claim 5, and substantially as described with reference to the accompanying drawings.