JPH07174828A - Device to generate data train with optional length - Google Patents

Abstract

PURPOSE:To generate data train with optional length at high speed by device with a simple structure. CONSTITUTION:Data of 16 bits in parallel is stored in a first memory 12. A first shift/register 14 loads the data in parallel and converts it into data in series. A load controlling memory (a second memory) 22 save load controlling data of 16 bits of which optionally prescribed bit orders the loading. A second shift/register 24 loads the load controlling data and converts it into a load signal. An address producing device 10 supplies the address to the first and the second memories 12, 22. The first and the second shift/registers 14, 24 load the data based on the load signal. That is, the first and the second shift/registers 14, 24 load the data in parallel and the data in series simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data string generator, and more particularly to an arbitrary length data string generator capable of arbitrarily setting the length of a data string.

[0002]

Data string generators are used to provide desired digital patterns to various digital electronic devices. For example, during development of various devices, it is used such that a signal to be output from an unfinished circuit is generated by this data string generator and other circuits are inspected.

FIG. 3 is a block diagram of an example of a conventional data string generator. 2 is a sequencer that determines the output order of parallel data. A sequence control circuit 1 controls the sequencer 2. Further, 3 is an address generator controlled by a sequencer, 4 is a memory for storing parallel data, and 5 is a parallel-serial converter (shift register or the like, SR) for converting parallel data into serial data. The serial data can be used as is as described above, but multiple serial data generated in the same
If it is converted into an analog signal using an analog converter (D / A), it can be applied as an analog waveform generator.

Although a high-speed D / A is relatively easy to obtain, it is generally difficult to operate a large capacity memory at high speed. Therefore, the parallel data having the number of bits n is stored in the memory 3, the data is read in parallel in accordance with the low-speed frequency-divided clock (frequency fn), the parallel-serial converter 4 performs parallel-serial conversion into serial data, and the frequency fr The serial-to-serial converter 4 outputs serial data according to a high-speed reference clock. This makes it possible to generate an apparently high-speed data string. In response to this, the address generator 2 is clocked by the divided clock fn and supplies the address to the memory 3.
The divided clock fn is obtained by dividing the reference clock fr by the dividing ratio n corresponding to the number n of bits of parallel data.

[0005]

However, in the above-mentioned conventional example, serial data can only be generated with a length of n units corresponding to the bit number n of the parallel data output from the memory. That is, only a data string having an integral multiple of n can be generated, and a data string having an arbitrary length cannot be generated. In addition, in order to perform an operation such as jumping or looping (repeating) when designating the next address of the memory, it is necessary to add a complicated circuit to the sequencer.

Therefore, an object of the present invention is to provide an arbitrary length data string generator which can generate a data string of an arbitrary length at high speed. Another object of the present invention is to provide an arbitrary length data string generator having a relatively simple structure.

[0007]

SUMMARY OF THE INVENTION The present invention provides an arbitrary length data string generator capable of generating a high speed data string of an arbitrary length. The first memory 12 has n
Stores bit parallel data. n is an integer of 2 or more. The first parallel-serial conversion means 14 loads parallel data and converts it into serial data. The second memory 22 stores n-bit load control data in which an arbitrary predetermined bit indicates a load. The second parallel-serial conversion means 24 loads the load control data and converts it into a load signal. The address supply means 10 supplies an address to the first and second memories.

The first and second parallel-serial conversion means 14 and 24 load data according to the load signal. That is, the first and second parallel-serial conversion means 14 and 24
Respectively loads parallel data and load control data at the same time. With this, the length of serial data generated from one parallel data can be controlled, and as a result, a data string of an arbitrary length can be generated.

[0009]

FIG. 1 is a block diagram of a preferred embodiment of a data string generator of the present invention. Memory (first memory) 12
At each address, n-bit parallel data is stored. n is an integer of 2 or more. The first shift register (SR) 14 is a parallel-serial conversion unit that loads parallel data from the memory 12 and converts it into serial data. Second
The memory (load control memory) 22 stores n-bit load control data in which an arbitrary predetermined bit indicates a load. The second shift register (SR) 24 is a parallel-serial conversion unit that loads the load control data and converts it into a load signal. The address generator 10 supplies a common address to the memory 12 and the load control memory 22. The output of the shift register 14 is converted into a digital / analog converter (D
As described above, it can be used as a waveform generator if it is converted into an analog signal using / A) or the like. As is well known, the loop 16 is provided to execute a jump instruction that removes an intermediate address and specifies the next address. The central processing unit (CPU, not shown) controls operations such as reading and writing data in each memory.

The number n of bits of parallel data is an arbitrary integer of 2 or more as described above. However, in the following description, n = 16 for simplicity. That is, 16-bit data (parallel data) is stored in each address of the first and second memories.
Is memorized. Therefore, in this case, the number of bits of each parallel data when loading the parallel data from the first and second memories to the first and second shift registers is always 16 bits.

FIG. 2 shows a timing chart for serial data output from the first shift register 14 and a clock (CLK) of the load signal output from the second shift register 24. The serial data A has 16 data items. At this time, the serial data A is transferred to the first shift register 1
The second shift register 2 simultaneously when loaded into
The load control data A loaded in No. 4 has data indicating the load in its 16th bit. Therefore, the load signal rises at the 16th clock after the first loading. Each shift register receives the load signal and loads the parallel data from the corresponding memory. That is, the load signal defines the load timing.

Similarly, the load control data B corresponding to the serial data B has data indicating a load in its ninth bit. Therefore, the load signal rises at the ninth clock after the first loading. Similarly, the length of serial data generated from one parallel data can be adjusted in the range of n or less by inserting data indicating the load in any bit of the n-bit load control data. Therefore, a data string of an arbitrary length can be generated by combining serial data generated from one parallel data. In the load control data, the data indicating the load of the n bits is set to "1" and the other data is set to "1"
It should be 0 ".

Although the embodiment of FIG. 1 shows the case where only one first memory stores parallel data, a plurality of memories may be used. According to this, parallel data having a larger number of bits can be called from the first memory to generate long serial data at one time. In this case, the parallel data (load control data) having the same number of bits as the parallel data is stored in each address of the second memory (load control memory). As a result, even if the next designated address jumps, the contents of each address in the first memory and the second memory always correspond, and the length of serial data generated from one parallel data is set to a preset length. You can

[0014]

The arbitrary length data string generator of the present invention stores the parallel data in one of the first and second memories and the load control data for determining the timing of loading the parallel data into the parallel-serial conversion means in the other. I remember. And
According to this load control data, the length of serial data generated from one parallel data can be set arbitrarily. Therefore, the length of the data string composed of each serial data can be set to an arbitrary length. Further, the first and second memories have addresses corresponding to each other, and even if the addresses are not sequentially designated by a jump instruction or the like, a data string can be generated without requiring special processing or circuits.

[Brief description of drawings]

FIG. 1 is a block diagram of a preferred embodiment of an arbitrary length data string generator of the present invention.

FIG. 2 is a timing diagram of serial data and a load signal.

FIG. 3 is a block diagram of an example of a conventional data string generator.

[Explanation of symbols]

 10 Address Supply Means 12 First Memory 14 First Parallel-Serial Conversion Means 22 Second Memory (Load Control Memory) 24 Second Parallel-Serial Conversion Means

Claims (1)

[Claims] 1. A first memory for storing n-bit parallel data
A memory and a first for loading the parallel data and converting it into serial data
Parallel-serial conversion means, a second memory that stores n-bit load control data in which an arbitrary predetermined bit indicates a load, second parallel-serial conversion means that loads the load control data and converts the load control data into a load signal, An arbitrary length data string generator comprising: address supply means for supplying an address to the first and second memories, wherein the first and second parallel-serial conversion means load data in accordance with the load signal.