JPH05281973A - Memory access device - Google Patents

Abstract

PURPOSE:To divide the readout timing of respective sound generation channels, to assign read timing for reading control data out, and to shorten the time of access for reading the control data out of a memory when musical sound waveform data are read out on a time-division basis, channel by channel, out of the memory stored with musical sound waveform data and the control data other than the musical sound waveform data. CONSTITUTION:At the timing obtained by dividing current value addresses assigned to the respective channels by four, a control data read address, a current value address, a control data read address, and a decrement address are selected in this order to generate an address (Address). At the timing of the network mark of the address (Address), the control data read address is outputted to read the control data out of the memory 4. The decrement address is outputted at timing '-1' and the current value address is outputted at unmarked timing to read the musical sound waveform data out of the memory 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access device, and more particularly to a memory for storing tone waveform data,
When storing other control data and reading musical tone waveform data for each sound generation channel from this memory in a time division manner, the control data is read during this time division timing to reduce the number of sound generation channels and The present invention relates to a memory access device in which control data can be read.

[0002]

2. Description of the Related Art Conventionally, an electronic musical instrument that simultaneously generates a plurality of musical tones has a plurality of sound generation channels,
The tone waveform data is read out by addressing the memory storing the tone waveform data for each tone generation channel in a time division manner and generating the tone. However, since the memory for storing tone waveforms has a relatively large capacity and has a free area, in order to effectively use the free area of this memory,
Control data other than waveform data, such as rhythm and tempo, may be stored in this empty area. In order to read control data other than such waveform data from the memory, conventionally, a predetermined empty channel is set as a control data reading channel separately from the tone waveform reading channel, and the read timing of the set empty channel is reached. At times, data other than the waveform data is read from the memory. Therefore, the memory for storing the musical tone waveform data can be used for storing data other than the waveform data, and the memory can be effectively used.

[0003]

However, in such a conventional memory access device, particularly in the memory access device which reads out musical tone waveform data from a memory and outputs a polyphonic tone, the musical tone waveform data is stored. In order to effectively use the memory, the control data other than the tone waveform data is stored in the empty area of the memory, and if there is an access request, the control data read waits for the channel timing to access the memory. Since the access request has been permitted, the process is in a waiting state from when there is an access request until the timing of generation of this channel. As a result, there is a problem in that the processing time is wasted and becomes an obstacle to the speed-up processing. Therefore, the present invention enables control data other than tone waveform data to be read at high speed without reducing the number of sound generation channels, and shortens the memory access time when reading control data other than tone waveform data from the memory. Then, the purpose is to increase the processing speed.

[0004]

In order to solve the above problems, the present invention provides a memory means for storing tone waveform data and other control data, and a plurality of tone waveform data from the memory means in a time division manner. For reading, a tone waveform data address output means for outputting a corresponding address signal at time division timing, and each time each address is outputted from the tone waveform data address output means, control from the memory means during the time division timing section Control data address output means for outputting an address signal for reading data instead of the address signal for reading the musical tone waveform data, and a musical tone based on the musical tone waveform data read by the musical tone waveform data address outputting means. The tone generation instruction means for instructing the generation and the control data address output means A receiving means for receiving control data Desa seen, it is characterized by comprising a. In this case, for example, as described in claim 2, the memory means continuously stores the control data in a specific address area, and the control data address output means outputs at each time division timing. A stepping means for automatically stepping the address signal may be provided.

[0005]

According to the present invention, in order to store musical tone waveform data and other data in the memory means and to read a plurality of musical tone waveform data from this memory means in a time division manner, the corresponding address signal is converted into the musical tone waveform data. The address output means outputs at time-division timing. Every time each address is output by the tone waveform data address output means, an address signal for reading control data from the memory means in the time division timing section is output by the control data address output means for reading the tone waveform data. Instead of the address signal, the tone generation instruction means instructs the tone generation based on the tone waveform data output by the tone waveform data address output means. The receiving means receives the control data read by the control data address output means. Therefore, when the tone waveform data is read out from the memory storing the tone waveform data and the control data other than the tone waveform data at the time-division timing for each tone-generation channel, the read-out timing of each tone-division tone-generation channel is divided. The read timing for reading the control data other than the tone waveform data can be assigned to the divided read timings. As a result, control data other than tone waveform data can be read at high speed without reducing the number of sound generation channels, and the access time to the memory when reading control data other than tone waveform data from the memory is shortened. The processing speed can be increased. In this case, the memory means continuously stores control data in a specific address area, and the control data address output means automatically advances the address signal output at each time division timing. By providing the means, it is not necessary to output the address signal for reading the control data from the CPU, the microcomputer, etc., and the load on the CPU, the microcomputer, etc. can be reduced.

[0006]

[Examples] Specific examples will be described below.
1 to 11 are views showing an embodiment of a memory access device of the present invention, which is applied to an electronic musical instrument. FIG. 1 is an overall configuration diagram of the electronic musical instrument 1.
A CPU (Central Processing Unit) 2, a sound source 3, a memory (memory means) 4, a clock generator 5 and the like are provided.

The electronic musical instrument 1 has a plurality of tone generation channels, for example, eight channels, and performs so-called polyphonic performance.

The clock generator 5 is provided with an oscillation circuit and a frequency dividing circuit, and outputs the clock CK1 and the clock CK2 to each section of the electronic musical instrument 1.

In the electronic musical instrument 1, when a keystroke operation or a key release operation is performed on a keyboard (not shown), the operation signal is output to the CPU 2, and the CPU 2 takes in the operation signal and processes it as various electronic musical instruments 1. Do. In particular, various signals corresponding to the key operation to the sound source 3, for example, chip select (Chip
Select), write strobe (WriteStrobe), read strobe (ReadStrobe) and address are output, and the tone generator 3 accesses the memory 4 based on the signal from the CPU 3 to read musical tone waveform data from the memory 5. Further, the sound source 3 has an address (Address) and a chip enable (ChipEnabl) in the memory 4, as described later.
e) is output to read the control data from the memory 4,
When the control data read from the memory 4 is transferred to the CPU 2 via the data bus (DataBus) or the musical tone waveform data is read from the memory 4, the musical tone waveform data is subjected to integration processing and interpolation processing as described later. And output as waveform output.

The CPU 2 is provided with various registers for storing the tone generation states of a plurality of tone generation channels and operation data subjected to key operation. The CPU 2 controls the tone generation based on the data stored in these various registers, and the necessary data is described above. Is output to the sound source 3.

The memory 4 is a large-capacity memory and mainly stores musical tone waveform data as a difference value for each address. In addition to the musical tone waveform data, control data such as tempo data and rhythm is stored. I remember. The memory 4 stores control data other than the musical tone waveform data continuously in, for example, a specific address area. The memory 4 has chip enable from the sound source 3.
And the address (Address) are input, and the addressed data (Data) is output to the sound source 3.

The sound source 3 is constructed as shown in FIG. 2, and has an interface circuit 11 and a channel control circuit 1.
2, an address generator 13, an address controller 14, an integrator 15, an interpolator 16, a register 17, a gate circuit 18, and the like.

The interface circuit 11 is a circuit for interfacing with the CPU 2. From the CPU 2, the write strobe (WriteStrobe), the read strobe (ReadStrobe), the address (Address) and the data (Dat).
The data of CPU read bus (CPU ReadBus) is input from the register 17 while a) is input. Further, the interface circuit 11 outputs data to the address generator 13 and the address controller 14 via an interface data bus (I / F DataBus), and outputs a clock CKa to the gate circuit 18 and the like.

In particular, the interface circuit 11 receives the data (control data) read from the memory 4 via the register 17 and transfers it to the CPU 2 via the data bus (DataBus). Therefore, the register 17 and the interface circuit 11 function as a receiving unit that receives the read control data.

As shown in FIG. 3, the channel control circuit 12 has a frequency divider 21 for dividing the input by 4, a frequency divider 22 for dividing the input by 8, an inverter 23 and a frequency divider for dividing the input by 4. 24 are provided.

The clock CK1 from the clock generator 5 is input to the frequency divider 21 of the channel control circuit 12, and the channel control circuit 12 uses the clock C1.
After K1 is divided by 4 by the frequency divider 21, it is divided by 8 by the frequency divider 22 to divide the signal CH into the address generator 13 and the interpolator 1.
Output to 6.

Further, in the channel control circuit 12, the clock CK1 from the clock generator 5 is input to the frequency divider 24 via the inverter 23, and the frequency divider 24 divides the inverted clock CK1 into four. As a selector control signal,
It outputs to the address controller 14, the gate circuit 18, and the like.

As shown in FIG. 4, the address generator 13 includes a current value address storage memory 31 and a register 3
2, 33, incrementer 34, binary adder 35,
An address stepping amount storage memory 36 and a register 37 are provided.

The current value address storage memory 31 stores the current value address output from the incrementer 34 for each channel, and the current value address storage memory 31 stores the current value address in the incrementer 34 via the register 32. It outputs the current value address to the binary adder 35 via the register 33.

The address increment storage memory 36 stores the CP
The address increment amount for each channel is transferred from U2 and set, and the address increment amount storage memory 36 stores the signal C
In synchronization with H, the binary adder 3 via the register 37
The address step amount is output to 5.

The binary adder 35 adds the address step amount input from the address step amount storage memory 36 via the register 37 to the present value address input from the present value address storage memory 31 via the register 33. Then, the address fractional part of the addition result is output as the current fractional address and is also output to the current value address storage memory 31.

The binary adder 35 outputs a carry to the incrementer 34 and the integrator 15 shown in FIG. 2 when a carry occurs as a result of the addition.

The incrementer 34 is a binary adder 3
When carry is not input from 5, register 32
The current value address input from the current value address storage memory 31 via the is output to the address controller 14 and the current value address storage memory 31 as it is, and when the carry is input from the binary adder 35, the current value input from the register is input. The value address is incremented (“1” is added) and output to the address controller 14 and the current value address storage memory 31.

That is, as shown in FIG. 5, the current value address is composed of an integer part and a decimal part, and the address step amount is the step amount of this decimal part. Then, the address generator 13 adds the address increment amount to the current value address, and when a carry occurs due to the addition result, increments the current integer address and adds "1" to the integer part of the current value address. And outputs it as the current integer address. Further, the address generator 13 adds the address increment amount to the current value address, and outputs a fractional part of the addition result as the current fractional address when no carry occurs due to the addition result.

Therefore, the address generator 13
To read a plurality of tone waveform data from the memory 4 in a time division manner, it functions as a tone waveform data address output means for outputting a corresponding address signal at a time division timing.

The address controller 14 shown in FIG.
As shown in FIG. 6, the decrementer 41, the register 4
2, the selector 43 and the register 44 are provided, and the present value address is input from the address generator 13 to the decrementer 41 and the selector 43.

The decrementer 41 decrements the current value address input from the address generator 13 by "1" and outputs it as a decrement address to the selector 43.

On the other hand, in the register 42, data input from the interface circuit 11 shown in FIG. 2 through the interface data bus (I / F DataBus), that is, control other than tone waveform data stored in the memory 4 is controlled. The control data read address output from the CPU 2 to the interface circuit 11 of the sound source 3 for reading the data is input, and the register 42 is synchronized with the clock CKa input from the interface circuit 11 to synchronize with the interface data bus (I / F). The control data read address input from (DataBus) is fetched and output to the selector 43.

As described above, the selector 43 has the present value address from the address generator 13, the decrement address from the decrementer 41, and the register 4 as described above.
2 receives the control data read address and the channel control unit 12 receives the selector control signal, and the selector 43 selects the current value address, the decrement address, and the control data read address according to the selector control signal. Then, the address (Addr
ess) is output.

The register 44 fetches the address (Address) input from the selector 43 in synchronization with the clock CK1 and outputs it to the memory 4.

Therefore, the address controller 14
Is an address signal for reading control data from the memory 4 and an address signal for reading tone waveform data each time an address is output from the address generator 13 as the tone waveform data address output means. Instead, it functions as control data address output means for outputting.

When an address is designated, the memory 4 stores the musical tone waveform data (difference value data) or control data stored at the designated address in the integrator 1 of the sound source 3.
5, output to the interpolator 16 and the register 17.

As shown in FIG. 7, the integrator 15 includes a register 51, a computing unit 52, an integrated value storage memory 53 and a register 54. The difference value data read from the memory 4 is stored in the register 51. Is entered.

The difference value data held in the register 51 is output to the arithmetic unit 52, and the data (integrated value) from the register 54 is further input to the arithmetic unit 52.

The carry output from the address generator 13 is input to the arithmetic unit 52. When the carry is not input, the computing unit 52 outputs the integrated value data input from the register 54 as it is, and when the carry is input, the difference value data input from the register 51 is input to the integrated value input from the register 54. It is added to the data and output as integrated value data to the interpolation circuit 7 and the integrated value storage memory 53. As described above, this carry is output when a carry occurs in the current value address calculated by the address generator 13, that is, when the integer part of the address is updated.

The integrated value storage memory 53 stores the integrated value data output from the calculator 52, and when the signal CH is input twice, outputs the stored integrated value data to the register 54.

Therefore, the integrator 15 adds the difference value read from the memory 4 and calculates the integrated value only when the integer part of the current value address for reading the data from the memory 4 changes. When the integer part of the current value address does not change, the integrated value stored so far in the integrated value storage memory 53 is directly output as the integrated value.

As shown in FIG. 18, the interpolator 16 comprises registers 61 and 62, a multiplier 63 and an adder 64, and the integrated value from the integrating circuit 6 is input to the register 62.

The multiplier 63 includes the address generator 1
3 and the differential address data (current decimal address) of the current value address output from the memory 4 and the differential value data stored in the register 61 and stored in the register 61 are input, and the multiplier 63 outputs the current decimal address and the differential value data. Multiply and adder 6
Output to 4. That is, the multiplier 63 calculates the step amount of the difference value data given by the current decimal address by multiplying the difference value data by the current decimal address.

The integrated value held in the register 62 is further input to the adder 64. The adder 64 adds the multiplication result of the multiplier 63 and the integrated value output from the register 62 to generate musical tone waveform data. Output as. That is, the adder 64 calculates the tone waveform data by adding the step amount of the difference value data corresponding to the current decimal address to the integrated value.

Therefore, the CPU 2, the integrator 15, and the interpolator 16 instruct the musical tone generation based on the musical tone waveform data addressed and read by the address output means address generator 13 via the address controller 14. Functions as a generation instruction means.

Returning to FIG. 2, the data read out from the memory 4, in particular, the control data is input to the register 17, and the register 17 transfers the control data input in synchronization with the clock CK2 to the CPU read bus. Output to the interface circuit 11 via (CPU ReadBus). The interface circuit 11 outputs the control data input from the register 17 to the CPU 2 via the data bus (DataBus).

Therefore, the register 17 and the interface circuit 11 function as receiving means for receiving the control data read by the address controller 14 as the control data address output means.

In the gate circuit 18 of FIG. 2, the chip select (ChipSelect) from the CPU 2, the clock CKa from the interface circuit 11, and the channel control circuit 1 are provided.
The selector signal from 2 is input to the gate circuit 1
8 outputs a chip enable to the memory 4 based on each of these input signals.

Next, the operation will be described. When playing with the electronic musical instrument 1, first, a tone color is preset in a tone color register of the CPU 2 in a predetermined tone color creating mode.

When the power of the electronic musical instrument 1 is turned on in the state where the timbre is preset, the initialization processing is performed as shown in FIG. 9 to set and reset the registers in the CPU 2.

When the initialization process is completed, the CPU
2. A key common signal is output to a keyboard (not shown) to perform key scanning (step S2), the key operation of the keyboard is detected by this key scanning, and the detected key data is stored in the CPU2.
Take in.

When the key data is taken in, the CPU
2 checks whether there is a key change from the fetched key data (step S3), and when there is no key change, returns to step S2 and similarly performs key scanning.

In step S3, if there is a keystroke, that is, if there is a key change from ON to OFF, the pitch data corresponding to the keycode of the key that has been tapped is transferred to the sound source 3 (step S4). Specifically, the data is transferred to the corresponding channel area of the address increment storage memory 36 provided in the address generator 13 of the sound source 3. When the transfer of the pitch data is completed, the process returns to step S2 to similarly perform the sequential processing from the key scanning, and the pitch data corresponding to the key scanning is transferred to the corresponding channel area of the address increment storage memory 36.

In step S3, if there is a key release, that is, if there is a key change from OFF to ON, the same pitch data as the pitch data corresponding to the key code of the released key is sent to the address step. Whether it is stored in the advance amount storage memory 36 and the current value address storage memory 31 is checked, and if stored, the pitch data is cleared and the process returns to step S2 (step S5).

When the CPU 2 performs the key scanning in this way and sets the necessary data, the tone generator 3 generates an address to read the tone waveform data (difference value data) from the memory 4 and read the tone waveform data. Is subjected to integration processing and interpolation processing to output a waveform corresponding to the key operation.

On the other hand, when reading the control data from the memory 4, the CPU 2 first outputs a write strobe signal to the sound source 3 as shown in FIG. 10 (step P1), and controls the data bus (DataBus). The data read address is output (step P2).

When the CPU 2 outputs the control data read address, the tone generator 3 converts the control data read address into a tone waveform data read address and outputs it to the memory 4.
The control data read from the memory 4 is transferred to the CPU 2.

That is, when the write strobe signal is input, the sound source 3 receives the data bus (Dat).
aBus) and fetches the control data read address, and transfers the control data read address to the address controller 14 via the interface data bus (I / F DataBus).

Based on the selector control signal, the address controller 14 causes the selector 43 to output the current value address input from the address generator 13, the decrementer 41 to decrement the current value address, and the interface circuit 11 to the register 42. The control data read address input via the memory is sequentially selected and output to the memory 4 via the register 44. The selector control signal input to the selector 43 is supplied to the clock C by the channel control circuit 12.
This is a signal created by dividing the inverted signal of K1 by four, and is a signal obtained by dividing the current value address assigned to each channel into four, as shown in FIG.

In FIG. 11, "0" in the selector control signal column indicates the current address selection signal, "2" indicates the control data read address selection signal, and "1" indicates The decrement address selection signal is shown. At the timing when the current value address assigned to each channel is divided into four, the selector 43, as shown in the address column of FIG. 11, controls data read address → current value address → control data read address → Decrement address is selected in this order, and the memory 4 is set as an address through the register 44.
Output to. In FIG. 11, the address (Addres
The halftone dot mark in the column of (s) indicates the control data read address, "-1" indicates the decrement address,
No mark indicates the current value address.

As a result, unlike the prior art, it is not necessary to set a dedicated channel for reading the control data from the memory 4, and the control data can be read from the memory 4 without reducing the number of channels for tone generation. You can Further, since the control data read address is output by dividing the current value address of each channel, it is not necessary to wait until the read timing of the channel set to read the control data, and the waiting time of the CPU 2 can be shortened. Therefore, the processing speed can be improved.

Returning to FIG. 10 again, the CPU 2 checks whether or not the reading is completed and whether or not the clock CK2, which is the reading clock, has risen (step P
3) After waiting for the reading to be completed, a read strobe signal is output to the sound source 3 (step P).
4).

When the interface circuit 11 of the sound source 3 outputs the control data read from the memory 4 to the data bus (DataBus) according to the read strobe (ReadStrobe), the CPU 2 outputs the control data on the data bus (DataBus). Read (step P5).

Similarly thereafter, the CPU 2 performs the above processing every time one address is output, and sequentially reads the necessary control data from the memory 4.

As described above, it is not necessary to set a dedicated channel for reading the control data from the memory 4 as in the conventional case, and the control data is read from the memory 4 without reducing the number of channels for tone generation. be able to. Also, since the control data read address is output by dividing the current value address of each channel, it is not necessary to wait until the set channel read timing to read the control data, and the waiting time of the CPU 2 can be shortened. The processing speed can be improved.

12 and 13 are views showing another embodiment of the memory access device according to the present invention. In this embodiment, the address controller of the tone generator is output without outputting the control data read address from the CPU one by one. It can be created with.

The present embodiment differs from the above embodiment in the address controller. Among them, the same configuration has the same reference numerals as those used in the above embodiment, and the description thereof will be omitted. Further, in the case of the present embodiment, the memory 4 stores control data continuously in a predetermined address area.

FIG. 12 is a circuit configuration diagram of the address controller 100 used in this embodiment. The address controller 100 has the entire contents of the address controller 14 of the above embodiment and the selector 101.
And an incrementer 102.

The selector 101 has an interface data bus (I / F DataBu) from the interface circuit 11.
The control data read address input via s) and the output of the incrementer 102 are input, and the selector 101
First selects the control data read address transferred from the interface circuit 11 and outputs it to the register 42. The selector 101 then changes to the incrementer 1
The data input from 02 is output to the register 42.

The register 42 uses the clock C as described above.
The data input from the selector in synchronization with Ka is fetched, output to the selector 43, and output to the incrementer 102.

The incrementer 102 increments the input data, that is, the control data read address by "1" and outputs it to the selector 101. The selector 101 selects the increment address output by the incrementer 102 and outputs it to the register 42.

Next, the operation will be described. In this embodiment, the sound source 3 generates an address on the basis of the data given from the CPU 2 and the memory 4 as in the above embodiment.
The musical tone waveform data (difference value data) is read from, and the read musical tone waveform data is subjected to integration processing and interpolation processing to output a waveform corresponding to the key operation.

When the control data is fetched from the memory 4, as shown in FIG. 13, first, a write strobe signal is output to the sound source 3 (step Q1), and the control data read address is output to the data bus (DataBus). Is output (step Q2).

When the CPU 2 outputs the control data read address, the address controller 100 of the tone generator 3 converts the control data read address into an address for reading the waveform data, outputs it to the memory 4, and outputs the control data read from the memory 4. Is transferred to the CPU 2.

The CPU 2 checks whether the reading of the control data for one data has been completed by checking whether the clock CK2, which is a read clock, has risen (step Q3), and waits for the reading of one data to be completed. , And outputs a read strobe signal to the sound source 3 (step P4).

When the interface circuit 11 of the sound source 3 outputs the control data read from the memory 4 to the data bus (DataBus) in response to the read strobe signal, the CPU 2 outputs this data bus (DataBus).
The control data above is read (step P5).

When the reading of one data is completed, it is checked whether the reading of all the data is completed (step Q6). If not completed, the process returns to step Q3 and the reading of the next one data is completed. Check whether or not. The above process is repeated in sequence, and when the reading of all data is completed in step Q6, the process ends.

That is, in this embodiment, when the first control data read address is given from the CPU 2 to the tone generator 3, the address controller 100 of the tone generator 3 sequentially increments the first given control data read address by the incrementer 102. Then, the subsequent control data read address is created, and the control data is read from the memory 4 by this control data read address.

Therefore, the CPU 2 creates the control data read address by the address controller 100 of the tone generator 3 and gives the control from the memory 4 only by giving the first control data read address and without giving the subsequent control data read address. The data can be read, the workload of the CPU 2 can be reduced, and the CPU 2 can be used efficiently.

[0076]

According to the present invention, when the musical tone waveform data is read out from the memory storing the musical tone waveform data and the data other than the musical tone waveform data for each tone generation channel at the time division timing, each time division tone generation channel. Is divided, and the control data read timing for reading the control data other than the musical tone waveform data is assigned to the divided read timing. The control data can be read, the access time to the memory when the control data other than the musical tone waveform data is read from the memory can be shortened, and the processing speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an electronic musical instrument to which a memory access device according to the present invention is applied.

FIG. 2 is a block diagram of the sound source of FIG.

3 is a circuit diagram of the channel control circuit of FIG.

FIG. 4 is a circuit diagram of the address generator of FIG.

FIG. 5 is a diagram showing a relationship between an address configuration of a current value address and an address step amount.

FIG. 6 is a circuit diagram of the address controller shown in FIG.

FIG. 7 is a circuit diagram of the integrating circuit of FIG.

FIG. 8 is a circuit diagram of the interpolation circuit of FIG.

FIG. 9 is a flowchart showing main processing by the CPU of FIG.

10 is a flowchart showing a control data fetching process by the CPU of FIG.

FIG. 11 is a timing chart showing the operation timing of control data fetch processing.

FIG. 12 is a circuit diagram of an address controller of another embodiment of the memory access device according to the present invention.

FIG. 13 is a flowchart showing a control data fetching process by a CPU according to another embodiment.

[Explanation of symbols]

 1 electronic musical instrument 2 CPU 3 sound source 4 memory 5 clock generator 11 interface circuit 12 channel control circuit 13 address generator 14 address controller 15 integrator 16 interpolator 17 registers 21, 22, 24 frequency divider 31 current value address storage memory 32, 33, 37 register 34 incrementer 35 binary adder 36 address increment storage memory 41 decrementer 42, 44 register 43 selector 51, 54 register 52 calculator 53 memory 61, 62 register 63 multiplier 64 adder 100 address controller 101 selector 102 Incrementer

Claims (2)

[Claims] 1. Memory means for storing tone waveform data and control data other than the tone waveform data, and a corresponding address signal is output at a time division timing in order to read out a plurality of tone waveform data from the memory means in a time division manner. The tone waveform data address output means, and each time each address is output from the tone waveform data address output means, an address signal for reading control data from the memory means in the time division timing section is read out from the tone waveform data. Control data address output means for outputting in place of the address signal, a tone generation instruction means for instructing tone generation based on the tone waveform data read by the tone waveform data address output means, and the control data address output Receiving means for receiving the control data read by the means, Memory access device, characterized in that was e. 2. The memory means continuously stores the control data in a specific address area, and the control data address output means automatically advances the address signal output at each time division timing. 2. The memory access device according to claim 1, further comprising stepping means for causing the step.