JP2716131B2 - Tone generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a musical tone generating apparatus using a memory reading method, and more particularly to a musical tone generating apparatus capable of writing to a memory. 2. Description of the Related Art Conventionally, there has been proposed a technique in which data in a memory storing musical sound generation data (so-called waveform data) can be rewritten. For example, according to Japanese Patent Application Laid-Open No. 62-121498, waveform data is rewritten at a timing other than the timing at which the waveform data is read, thereby enabling generation of musical tones whose timbre changes with time. Problems to be Solved by the Invention However, according to the above-described prior art, since writing is performed using an empty cycle other than the read cycle, there is a problem that an empty cycle must be prepared in advance. Was. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems, and an object of the present invention is to provide a musical sound generator capable of writing data into a memory without an empty cycle. Means for Solving the Problems The present invention for solving the above problems has a memory for storing musical tone generating data, and a first address signal for supplying an address signal for reading the musical tone generating data from the memory. Supply means, second address signal supply means for supplying an address signal for writing musical tone generation data into the memory, and 2 supplied from the two address signal supply means.
Selecting means for switching the two address signals in synchronization with the internal operation and supplying the selected address signals to the memory and accessing the memory almost at all times; and generating a tone at an address of the memory indicated by the second address signal selected by the selecting means. Means for writing data for use in a memory and whether reading can be performed on a channel other than the corresponding channel in place of reading for the corresponding channel among a plurality of read cycles in which tone generating data of a plurality of channels are read in a time-division manner. A determination unit for determining whether or not the address signal can be switched, and instructing the selection unit to switch the address signal, and instructing the memory writing unit to write to the memory, if possible. According to the configuration described above, the selection unit switches the address signal to the memory in accordance with the instruction of the determination unit in synchronization with the internal operation, and is instructed by the determination unit when the write address signal is selected by the selection unit. By using the memory writing means, the tone generation data can be written into the memory even during the tone generation, and the tone color of the tone and the manner of changing the tone can be changed even during the tone generation. Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a tone generator according to this embodiment of the present invention. In FIG. 1, reference numeral 11 denotes an assigner, which is operated by operating a keyboard key (not shown).
Reference numeral 11 denotes an address signal ASAD for instructing reading or writing of tone generation data from the memory 12, a data signal AS including memory address data and tone generation data, and waveform calculation data such as an envelope.
The DT and the write signal WR are sent to the interface unit 13. As shown in FIG. 2, the interface unit 13 includes an assigner address latch 14 for holding the address signal ASAD sent from the assigner 11, an assigner data latch 15 for holding the data signal ASDT sent from the assigner 11, Signal INAD decoder 16, AND gates 17, 18, 19, inverter 2
0, a D flip-flop with reset 21, a D latch with reset 22, and a latch 23, which generate a data signal INDT corresponding to the address latch signal S1, the data latch signal S2, and the data signal ASDT. Then, the interface section 13 sends the read address data included in the data signal INDT to the tone address supply section 24 as first address signal supply means so as to read the tone generation data from the memory 12. Write data included in the data signal INDT so that the waveform calculation data for calculating the waveform of the tone generation data read from the memory 12 is sent to the waveform calculation unit 25, and the tone generation data is further written to the memory 12. The address data and the address latch signal S1 are sent to the address latch 26 as the second address supply means, and the tone generation data included in the data signal INDT so as to change the tone generation data in the memory 12; The data latch signal S2 is sent to the data latch 27. Two signals, the data latch signal S2 and the BUSY signal of the waveform calculation unit 25 indicating that the designated channel is being read, are input to an access management unit 28 described later. The address MUAD for reading supplied from the address supply unit 24 for musical tone and the address EDAD for writing supplied from the address latch 26 are input to a selector 29 as selection means and switched in synchronization with an internal operation. The data is supplied to the memory 12. Switching between the two addresses MUAD and EDAD is performed according to an instruction from the access management unit 28 as a determination unit. As shown in FIG. 3, the access management unit 28 includes inverters 30 and 31, AND gates 32, 33 and 34, a reset D flip-flop 35, and a D latch 36.
It is determined from the two signals SY whether or not the switching of the selector 29 is possible, the switching of the address MUAD, EDAD is instructed to the selector 29 by the switching signal S4, and the access and the memory for reading the musical sound generation data from the memory 12 are performed. The access to write musical tone generation data for data change to 12 is switched. Further, the tri-state buffer 37 serving as a memory writing means connected to the data latch 27 is provided with a tone signal of the data signal INDT held by the data latch 27 by the write access to the memory 12 indicated by the switching signal S4 of the access management unit 28. The generation data is written to the memory 12, and the data is changed. The memory 12 has an address input terminal A, a data input / output terminal IO, an output enable control terminal OE, and a write enable control terminal WE. 38 is a sound system for converting data from the waveform calculation unit 25 into sound, and 39 is a switching signal S4
Which is inverted and input to the output enable control terminal OE. The operation of the tone generator of the present embodiment configured as described above will be described below. When writing to the memory 12 is not performed, the address MUAD from the musical tone address supply unit 24 is supplied to the memory 12, and the musical tone generating data corresponding to the address is input to the waveform calculation unit 25. In this embodiment, the calculation of a plurality of channels is performed in a time-division manner, and as shown in FIG. 5, the time for accessing the memory 12 is the same as the calculation time assigned to one channel. Next, an operation when writing to the memory 12 is performed will be described in two stages. First, the operation of setting the address and data given to the memory 12 by the assigner 11 will be described with reference to the timing waveform chart of FIG. The assigner 11 outputs the address EDAD of the memory 12 to be written to the bus of the assigner data signal ASDT, and outputs the address assigned to the address latch 26 to the assigner address signal.
Output to ASAD bus and output write signal WR. Thus, in FIG. 2, the address included in the data signal ASDT is
EDAD is written to the assigner data latch 15 and the assigned address is written to the assigner address latch 14. Further, at the falling of the write signal WR, the output Q of the D flip-flop 21 becomes "1". As for the output of the decoder 16, Y1 becomes "1" because the address assigned to the address latch 26 has been written, and "0" otherwise. When the timing signal P1 synchronized with the internal operation becomes "1", the output Q of the D-latch 22 becomes "1", and when the timing signal P2 becomes "1", the output Q of the D-latch 23 also becomes "1". . Next, when the timing signal P3 becomes “1”, the output of the AND gate 19 also becomes R
ST1 becomes “1”, and the D flip-flop 21 and the D latch 22
Is reset, and both outputs Q become "0". Therefore, the output Q of the D latch 22 changes from “0” → “1” → “0”, so that the address latch signal S1 also changes from “0” → “1” → “0” and is output from the assigner data latch 15. The address EDAD included in the data signal INDT is written to the address latch 26. Similarly, assigner 11 then stores memory 12
The tone generation data EDDT to be written to the
The signal is output to the ASDT bus, the address assigned to the data latch 27 is output to the assigner address signal ASAD bus, and the write signal WR is output. This time, the output of the decoder 16 becomes "1" because the address assigned to the data latch 27 has been written, and "0" otherwise, and the data latch signal S2 changes from "0" to "1" in synchronization with the internal operation. “→” becomes “0”. Therefore, data EDDT is written to data latch 27. Next, an actual write operation to the memory 12 will be described with reference to FIG. The data latch signal S2 is "0"
When "1" becomes "0", the output Q of the D flip-flop 35 becomes "1" at the falling edge in FIG.
The BUSY signal of the waveform calculator 25 (FIG. 1) becomes "1" when the currently assigned channel is sounding, the output of the inverter 31 becomes "0", and the output Q of the D flip-flop 35 becomes an AND gate. The output Q of the D latch 36 is masked by 32.
Remains at "0". When the channel is not sounding, the BUSY signal becomes "0" indicating that sound is not being sounded, and the output of the AND gate 32 becomes "1". Timing signal P
When 4 becomes "1", the output Q of the D latch 36, that is, the switching signal S4 becomes "1". When the switching signal S4 becomes "1", the selector 29 switches, and the address EDAD, which is the content of the address latch 26, is output as the address signal MEAD for the memory 12. Further, the output of the inverter 39 becomes "0", the data output of the memory 12 is inhibited, and the tristate buffer 37 can be output. The tone generation data EDDT, which is the content of the data latch 27, is output to the data signal ME for the memory 12.
Output as DT. Next, when the timing signal P5 becomes “1”, the memory write control signal S5 also becomes “1” and the memory write control signal S5 becomes “1”.
The data signal MEDT corresponding to the musical tone generation data EDDT is written in 12. Next, when the timing signal P6 becomes “1”,
The signal RST2 also becomes "1", the D flip-flop 35 is reset, and its output Q becomes "0". Next, when the timing signal P4 becomes "1" again, the output Q of the D latch 36 becomes "0".
Selector 29 is switched, and the address MUAD
Is output as an address signal MEAD to the memory 12. Further, data output from the memory 12 is enabled, output from the tri-state buffer 37 is prohibited, and normal waveform calculation is performed. As described above, according to the present embodiment, the selector 29 for switching the address to the memory 12 in synchronization with the internal operation and the means for writing data to the memory 12 are provided. Music generation data can be written. Therefore, it is possible to freely change the timbre of the musical tone and the way of changing the timbre even after the start of the tone generation. In the present embodiment, the determination as to whether or not the channel can be written to the memory 12 is performed based on the BUSY signal indicating whether or not the channel is sounding.
The assigner 11 may provide data indicating a channel that can be written to the memory 12 and make a determination based on the data. In this embodiment, the assigner 11 and the interface
The bus between 13 is for address signal ASAD and data signal ASDT
However, an address latch enable signal may be added as a multiplexed bus for address / data. In this case, the number of signals can be reduced, and when configured as an LSI, the number of pins can be reduced. Further, a bus for an address between the selector 29 and the memory 12 and data for data between the tristate buffer 37 and the memory 12 may be multiplexed, and an address latch and an address latch enable signal may be added. Also in this case, the number of pins can be reduced when configured as an LSI. Advantageous Effects of the Invention As described above, according to the present invention, in a cycle of reading musical tone generation data of a plurality of channels performed in a time-division manner, writing other than the corresponding channel is performed instead of reading for the corresponding channel. It is not necessary to provide a cycle for writing to memory or an empty cycle in advance, and as a result, a higher sampling frequency,
The maximum polyphony can be increased, and high sound quality and rich performance can be achieved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a musical sound generating apparatus showing an embodiment of the present invention, FIG. 2 is a circuit diagram of an interface section of the musical sound generating apparatus, and FIG. FIG. 4 is a circuit diagram of the access management unit, FIG. 4 is a timing waveform diagram for explaining the operation of the interface unit in FIG. 2, and FIG. 5 is a timing waveform diagram for explaining the operation of the access management unit in FIG. 11 ... Assigner, 12 ... Memory, 13 ... Interface unit, 24 ... Tone address supply unit, 25 ... Waveform calculation unit, 26 ... Address latch, 27 ... Data latch, 28 ...
... Access management unit, 29 ... Selector, 37 ... Tristate buffer, 38 ... Sound system.

Claims (1)

(57) [Claims] A memory for storing musical tone generating data, first address signal supplying means for supplying an address signal for reading musical tone generating data from the memory, and a first address signal supplying an address signal for writing musical tone generating data to the memory; Two address signal supply means, two address signals supplied from the two address signal supply means are switched in synchronization with an internal operation and supplied to the memory, and a selection means for accessing the memory almost at all times; Memory writing means for writing tone generation data at the address of the memory indicated by the second address signal selected by the selection means; and a plurality of read cycles for reading tone generation data of a plurality of channels in a time-division manner. Determines whether it is possible to perform writing on a channel other than the corresponding channel in place of reading for the corresponding channel. The instructs the switching of the address signal to the selecting means, and said memory writing means for instructing writing to the memory determining means and the musical tone generating apparatus for generating a plurality of musical tones in a time sharing with a. 2. 2. The method according to claim 1, wherein said determining means is capable of performing writing instead of reading when the corresponding channel is not sounding, and determining that writing is not possible when the corresponding channel is sounding. Musical sound generator. 3. 2. The musical tone generator according to claim 1, wherein said determination means determines whether or not writing can be performed instead of reading based on data indicating a writable channel given from the assigner. apparatus.