JPH11149408A - High-speed memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce circuit scale by decreasing the number of memory cells to be used by half concerning a high-speed memory device with which high-speed reading enabled by interleave operation. SOLUTION: This device is composed of registers 15A-15N as many as the number of data to be stored, address decoder 16 for executing operation for writing data into these registers, plural multiplexers 17A and 17B for alternately fetching the data stored in the registers through the interleave operation, and a multiplex circuit 13 for multiplexing the data fetched by these multiplexers into signals of one system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed memory device which can be used for, for example, an IC test device.

[0002]

2. Description of the Related Art FIG. 3 shows a schematic configuration of a conventional high-speed memory device used in an IC test apparatus. In the figure, reference numeral 10 denotes a high-speed memory device, and reference numeral 20 denotes a main controller for controlling a terminal device of another IC test apparatus including the high-speed memory device 10. The high-speed memory device 10 can be, for example, a timing data storage device or a pin setting data storage device which constitutes a part of an IC test device.

The main controller 20 is generally constituted by a computer system such as a workstation, and transmits timing data or pin setting data, which are test conditions at the start of a test, to a transmission rate (relatively low speed) permitted on a data bus DBUS. ), The data is sent to the high-speed memory device 10, and during the test, various data taken in the high-speed memory device 10 are read at a high speed corresponding to the test speed. , Fall timing, and the like.

The conventional high-speed memory device 10 includes a plurality of memories 11A and 11B, and the plurality of memories 11A and 11B are provided.
B is operated in a time-sharing manner to enable mainly high-speed reading. This method is generally called interleaving and is widely used. That is, the plurality of memories 11A and 11B
Performs an operation of alternately writing the data sent from the main controller 10 to the memories 11A and 11B alternately to which the address signal is given by the interleave control circuit, and writes all the data necessary for the test.

When the test is started, the memories 11A and 11B
Is switched to the reading mode. Memory 11 for reading
A and 11B are read alternately, and the read data is multiplexed into one system signal by a multiplexing circuit 13 composed of a multiplexer, and the multiplexed signal is output to an output terminal 14. The data output to the output terminal 14 is twice the speed of the data read from the memories 11A and 11B, and the read speed is selected so that this speed is synchronized with the IC test speed.

[0006]

The conventional high-speed memory device 10 uses the same number of memories as the number of interleaved phases, 11A and 11B in the example shown. These two memories 11A and 11B must each have the same storage capacity as the number of data to be stored. That is, the memories 11A and 11B alternately access from the first address to the last address and store the data given to each address. Therefore, the memories 11A and 11B must have at least addresses from the first address to the last address, whereas the storage capacity of the main controller 11
It is necessary to have a storage capacity equal to or slightly larger than the number of data sent from the Internet.

As described above, the storage capacities of the memories 11A and 11B are equal to or slightly larger than the number of data to be stored, respectively. The number is の of each storage capacity of the memories 11A and 11B. Therefore, the utilization rate of the memories 11A and 11B is halved and there are many wasteful parts, which is uneconomical. In addition, the high-speed memory device 10
There is a disadvantage that when the whole is made into an IC, the shape of the IC becomes large.

[0008] The object of the present invention is to eliminate these disadvantages,
It is an object of the present invention to provide a high-speed memory device which can reduce a waste shape and a shape.

[0009]

According to the present invention, according to the present invention, the number of registers equal to the number of data to be stored, the operation of sequentially writing the data sent to the registers, and any of the plurality of registers according to the given address. An address decoder for performing an operation of selectively designating the data, a plurality of multiplexers for selectively extracting data read from the register specified by the address decoder, and one system for data extracted by the plurality of multiplexers. A high-speed memory device is constituted by a multiplexing circuit for multiplexing the signals into a plurality of signals and an interleave control circuit for controlling the operations of the plurality of multiplexers and the multiplexing circuit.

According to the configuration of the high-speed memory device of the present invention, a register is used as a storage element, and writing and reading are executed by selectively accessing the register. Therefore, the number of registers is equal to the number of data to be stored. The number may be the same as or slightly larger. Therefore, the rate at which storage elements are wasted can be reduced. In addition, an address is assigned to each register, writing of data sent at a low speed is performed by designating a register for each address, and at the time of reading, data output from each register by a plurality of multiplexers is interleaved. The data fetched and fetched by the interleave operation are multiplexed by the multiplexing circuit into one system signal, so that the data obtained at the time of reading can be high-speed data.

Therefore, according to the present invention, since there is no useless memory element, the circuit scale of the high-speed memory device can be reduced. As a result, cost reduction can be expected, and if the entire high-speed memory device is integrated into an IC,
The advantage that the shape of C can be reduced is obtained.

[0012]

FIG. 1 shows an embodiment of the present invention. In the present invention, a number of registers 15A to 15N corresponding to the number of data to be stored,
N, and a plurality of multiplexers 17 for selectively extracting data read from registers 15A to 16N.
A, 17B and the plurality of multiplexers 17A, 1
A multiplexing circuit 13 for multiplexing the data taken out at 7B into one system of signals;
B and the multiplexing circuit 13 by the interleave control circuit 12 for performing the interleave operation.
It is what constituted.

When the high-speed memory device 10 is used as a timing memory of an IC tester, the number of registers 15A to 15N is about 900 to 1000. The data and terminals D of the registers 15A to 15N are commonly connected, the data input terminal D is connected to the data bus DBUS, and the data sent from the main controller 20 is applied to the data input terminals D of the registers 15A to 15N. .

A selection signal (enable signal) from the address decoder 16 is applied to each enable terminal EN of the registers 15A to 15N. Address decoder 16 generates a selection signal to be applied to each of registers 15A to 15N according to an address signal applied from address bus ABUS. Assuming that the address signals output from the main controller 20 at the time of writing are sequentially transmitted from the first address to the last address in an order of increasing by one address, each of the registers 15A to 15A.
Each of the 15N enable terminals EN has 15A, 15B, 1
The selection signals are provided in the order of 5C, 15D... 15N.
Each time a selection signal is supplied to each of the registers 15A to 15N, data transmitted in synchronization with the address signal is written to the register to which the selection signal is supplied. When data is written to each of the registers 15A to 15N, the data is continuously output to the output side. That is, the registers 15A-1
5N can be constituted by a so-called latch circuit, and latched data is output to each output terminal upon completion of writing.

At the time of reading, a read address signal (FIG. 2A) for requesting data required for a test from a pattern generator (not particularly shown) to the interleave control circuit 12, for example.
Is given. The interleave control circuit 12 distributes this address signal to the multiplexers 17A and 17B,
The address signals (FIGS. 2B and 2C) are alternately supplied to the multiplexers 17A and 17B. Multiplexers 17A and 1
7B switches input terminals in accordance with the applied address signal, selects a register corresponding to the address signal, and extracts data stored in the selected register.

The example shown in FIG. 2 shows a case where the read address signals are applied to the interleave control circuit 12 in the order of A1, A3, A2, A5 and A8. This address signal is alternately applied to multiplexers 17A and 17B, and is used as an address signal (FIG. 2B, C) which changes at twice the cycle of the input address signal.
Is provided to the control terminal S. Multiplexer 17A stores registers 15A to 15N in accordance with an applied address signal.
Select That is, in the example of FIG.
Are supplied with address signals in the order of A1, A2, and A8, so that data D1, D2, and D8 held in registers corresponding to the respective addresses are extracted.

On the other hand, since the address signals are supplied to the multiplexer 17B in the order of A3, A5,... As shown in FIG. 2C, the data D3 and D5 held in the registers corresponding to the addresses A3, A5 are taken out. The data extracted by the multiplexers 17A and 17B is supplied to the multiplexer 13
To multiplex the signals into one system. For this purpose, a pulse shown in FIG. 2 is applied to the control terminal S of the multiplexing circuit 13. The cycle of this pulse matches the cycle of the read address signal shown in FIG.
Selects the input terminal A and outputs the data extracted by the multiplexer 17A to the output terminal 14. When the pulse has the L logic, the multiplexing circuit 13 selects the input terminal B and outputs the data extracted by the multiplexer 17B to the output terminal 14. Output to Accordingly, high-speed data shown in FIG. 2G is output to the output terminal 14.

In the embodiment described above, the multiplexer is 1
7A and 17B have been described, but the number of multiplexers is selected to be an arbitrary number of 2 or more. In order to further increase the speed of high-speed data, the greater the number of multiplexers, the more data is taken out. This is advantageous because the speed can be reduced.

[0019]

As described above, according to the present invention, the register used as the storage element only needs to be provided with the same number or a slightly larger number as the number of data to be stored. It can be reduced to about half of the conventional case. As a result, since the circuit scale of the high-speed memory device 10 can be reduced, there is an advantage that, in addition to cost reduction, even if the entire high-speed memory device 10 is formed into an IC, the shape of the IC can be reduced. .

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a block diagram for explaining a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 High-speed memory device 12 Interleave control circuit 13 Multiplexing circuit 14 Output terminal 15A-15N register 16 Address decoder 17A, 17B Multiplexer

Claims (1)

[Claims] 1. A. First Embodiment B. a number of registers corresponding to the number of data to be stored; B. an address decoder for executing a write operation of applying a selection signal to a selected one of the registers according to an address signal of the register and writing data supplied to a commonly connected input terminal to the selected one of the registers; A plurality of multiplexers for selectively extracting data stored in the register; A multiplexing circuit that multiplexes the data extracted by the plurality of multiplexers into one system signal and sends out the signal as a high-speed signal; A high-speed memory device comprising: a plurality of multiplexers; and an interleave control circuit for controlling the operation of the multiplexing circuit.