JPH07174829A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit for which a plurality of test mode settings are made possible by one terminal for testing. CONSTITUTION:A semiconductor integrated circuit is provided with a test terminal 1, dividing resistors R1-R3 to generate first voltage VA and second voltage VB lower than VA, a first comparator 6 to compare the input of the test terminal 1 and the voltage VA, a second comparator 7 to compare the input of the test terminal 1 and the voltage VB, a counter 3 which counts the output signal of the first comparator 6 and is reset by the output of the second comparator 7, and a decoder 4 which decodes the output obtained by counting the output of the first comparator 6 by the counter 3 and sends out a test mode signal based on the results of the decoding as an output to a following circuit. In the case the input of the test terminal 1 is less than the voltage VB, the circuit is driven in a normal operation mode and in the case the input is VB or higher, the circuit is driven in a test mode, so that switching of the test mode and the normal operation mode and selecting test modes can be done by using only one test terminal 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing test terminals in a semiconductor integrated circuit having a test function.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit having a test function is shown in FIG. This is provided with a test terminal 1 for inputting a test signal and a switching terminal 2 for inputting a switching signal for switching between a test mode and a normal operation mode, and the voltage level of the switching terminal 2 is set to "H". In this case, the test mode is set, and when set to "L", the normal operation mode (counter reset mode) is set. The counter 3 counts the clock input from the test terminal 1 only when the test mode is set, that is, when the switching terminal is "H", and the decoder 4 decodes the clock and outputs the result to the subsequent circuit. This makes it possible to set multiple test modes. When the normal operation mode is set, that is, the switching terminal 2
Is "L", if noise is superimposed on the switching terminal 2, the noise causes the test mode to be temporarily entered.
Since the voltage of will return to the GND level immediately, the counter 3
Has a function of returning to the original normal operation mode since it is reset.

[0003]

In the conventional semiconductor integrated circuit as described above, at least two terminals, that is, the test terminal 1 and the switching terminal 2 are required as terminals for testing.
There is a problem that the package of the semiconductor integrated circuit becomes large. For example, when considering a DIP package, the number of terminals is one pin, so a package corresponding to 48 pins cannot be used, and a package corresponding to 64 pins corresponding to one size larger may be required. . In such a case, the mounting area alone is more than doubled. In recent years, the number of input / output circuits (I / O) has increased with the increase in the functions to be incorporated into integrated circuits.
Along with that, the package size is also increasing. Therefore, considering the unit price of the integrated circuit, the mounting area on the substrate, and the like, it is very important to make the package as small as possible.

The present invention has been made to solve the problems of the prior art as described above, and an object thereof is to provide a semiconductor integrated circuit capable of setting a plurality of test modes with one test terminal. To do.

[0005]

To achieve the above object, in the present invention, a test terminal for inputting a test signal, a first potential and a second potential smaller than that are generated. Voltage generating means, first comparing means for comparing the input from the test terminal with the first potential of the voltage generating means and outputting a signal according to the comparison result, input from the test terminal and the above The output signals of the first comparing means and the second comparing means for comparing the second potential with each other and outputting a signal according to the comparison result are counted and reset by the output signal of the second comparing means. Counting means for decoding the output signal of the first comparing means, and decoding means for decoding the output of the counting means and outputting a test mode signal based on the decoded result to the subsequent circuit. When the input of the test terminal is less than the above second potential Normal operation mode, in the case of more than the second potential is configured to operate as a test mode. The test terminal corresponds to, for example, the test terminal 1 in the embodiment shown in FIG. 1, which will be described later. Similarly, the voltage generating means is the dividing resistors R _{1 to} R ₃ , and the first comparing means is the first comparator. 6, the second comparing means is the second comparator 7, the counting means is the counter 3, and the decoding means is the decoder 4.
, Respectively.

[0006]

The switching between the test mode and the normal operation mode is performed by comparing the input signal of the test terminal with the second potential. That is, when the input signal is lower than the second potential, the counting means is reset, so that the normal operation mode is set. When the input signal is equal to or higher than the second potential, the counting means outputs the input signal ( The output of the first comparison means) is counted and the value is decoded by the decoding means,
Multiple test modes can be identified. Therefore, the test mode and the normal operation mode are selected depending on whether the input signal applied to the test terminal is a low level (eg, GND level) lower than the second potential or a signal level higher than the second potential (power source potential or lower). And the test mode can be selected by counting and decoding the signal resulting from the comparison between the input signal and the first potential. Therefore, it is possible to switch between the test mode and the normal operation mode and select the test mode by using only one test terminal as a test terminal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention. First, the configuration will be described. 1 is a test terminal for inputting a signal for switching between the normal operation mode and the test mode and a signal for setting the contents of the test mode, 3 is a clock signal from the test terminal 1, and the number of pulses thereof is counted. , A decoder for decoding the output of the counter 3 and outputting a test mode setting signal corresponding thereto, R _{1 to} R ₃
Is a dividing resistor for generating the first voltage level V _A and the second voltage level V _B , 6 is a first comparator for comparing the first voltage level V _A with the input signal, and 7 is a It is a second comparator that compares the voltage level V _{B of} 2 and the input signal.

Next, the operation will be described based on the operation waveform diagram shown in FIG. The input voltage V _IN from the test terminal 1 is compared in the first comparator 6 and the second comparator 7 with the first voltage level V _A and the second voltage level V _B , respectively. When V _IN ≦ V _B, the reset signal is output from the second comparator 7 to reset the counter 3, and the normal operation mode is set. When V _B <V _IN , the input voltage V _IN
An output according to the (clock signal) is sent from the first comparator 6, and the counter 3 counts it. Therefore, switching between the test mode and the normal operation mode is performed under the following conditions. V _B ≦ V _IN ≦ V _CC : Test mode GND ≦ V _IN <V _B : Normal operation mode However, the first voltage level V _A = V _CC × (R ₂ + R ₃ ) / (R
₁ + R ₂ + R ₃ ) Second voltage level V _B = V _CC × R ₃ / (R ₁ + R ₂ + R ₃ ) As described above, the voltage of the test terminal 1 is fixed to GND or is higher than V _B. Depending on whether a signal is input, the test mode and the normal operation mode can be switched without using the switching terminal.

Further, the mode selection at the time of setting the test mode is performed by offset V ₀ such that V _B <V ₀ <V _A as shown in FIG.
And by (V _A -V _B) <entering the A _M <V _CC -V _B composed signal having an amplitude A _M the test terminal 1, it is possible to set a plurality of modes. That is, the counter 3 counts the output of the first comparator 6 according to the input signal from the test terminal 1, and the decoder 4 decodes the result,
Multiple test modes can be set with a single input signal. For example, in the case of FIG. 2, the case where the count number is “1” is the test mode 1, the case where the count number is “2” is the test mode 2, and the case where the count number is “3” is the test mode 3 is shown. There is.

In the normal operation mode, that is, V _IN =
When noise is applied when GND is fixed,
As shown in, the noise is detected and the test mode is temporarily entered, but if the noise is one-shot, the terminal voltage immediately returns to the GND level, so the counter is reset and the original normal operation mode is restored. You can go back. Therefore, even in the operation when noise is applied, the same function as the conventional example can be realized by only one test terminal.

[0011]

As described above, according to the present invention, since it is possible to set a plurality of test modes with one test terminal, it is possible to reduce the required number of pins as compared with the prior art. Therefore, the effect that the package size can be reduced can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

2 is a voltage waveform diagram showing an input voltage for switching between a test mode and a normal operation mode and selecting a test mode in the embodiment of FIG.

FIG. 3 is a circuit diagram showing a test mode setting method in a conventional semiconductor integrated circuit.

[Explanation of symbols]

1 ... Test terminal for inputting signal for setting test mode 2 ... Switching terminal for inputting signal for switching test mode and normal operation mode 3 ... Counter for counting signals from test terminal and outputting according to the number of pulses 4 Decoder for decoding output from counter and outputting test mode setting signal 6 ... First for comparing first voltage level V _A with input signal
Comparator 7 ... Second for comparing second voltage level V _B with input signal
Of the comparators R _{1 to} R ₃ ... Dividing resistors for producing the first voltage level V _A and the second voltage level V _B

Claims (1)

[Claims] 1. A test terminal for inputting a test signal, a voltage generating means for generating a first potential and a second potential smaller than the first potential, an input from the test terminal and the voltage generating means. First comparing means for comparing the first potential and outputting a signal according to the comparison result, and comparing the input from the test terminal with the second potential for outputting a signal according to the comparison result. The output signal of the second comparison means and the output signal of the first comparison means are counted, and the counting means reset by the output signal of the second comparison means and the output signal of the first comparison means are counted. Decoding means for decoding the output of the counting means and outputting a test mode signal based on the decoded result to a subsequent circuit, and when the input of the test terminal is less than the second potential, normal operation is performed. Mode, test mode when the potential is above the second potential The semiconductor integrated circuit characterized by being configured to operate Te.