JPH02176584A - Input/output buffer circuit - Google Patents

Abstract

PURPOSE:To suppress the increase in the number of outer terminals even if an LSI to be tested is made larger scale by takigg out input/output for normal data and an input for a test signal and further a monitor signal, through a common outer terminal. CONSTITUTION:A bi-directional buffer 1 is connected to the common outer terminal to process the inputs/outputs for the normal data signal, test signal and monitor signal, so as to be able to input and output these signals. By a 1st gate circuit 2, the test signal sent through a terminal 5 and the output signal for circuit block are selected and can be outputted from a signal output part 7 as a circuit block input signal. By a 2nd gate circuit 3, the monitor signal between the circuit blocks and the output signal for circuit block are selected and can be outputted. By a control circuit 4, a buffer control signal and a gate control signal can be outputted to the buffer 1 and the circuits 2, 3 in accordance with the time of normal input/output and the time of test input/ output, by means of receiving an input/output selection signal at the normal time, input selection signal for test data, and monitor output selection signal, respectively from the input parts 10-12 for thee signals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output buffer circuit for testing an LSI (large scale integrated circuit) consisting of a plurality of circuit blocks.

Generally, an LSI is made up of a plurality of circuit blocks, and signals are exchanged between the circuit blocks, and various tests are performed on such LSIs. In this case, instead of sending a signal from a certain circuit block, a test signal equivalent to the signal from this circuit block is sent. Also, a monitor signal between circuit blocks is taken out.

[Prior Art] FIG. 8 is a block diagram when a conventional human output buffer circuit is used for LSI testing.
Reference numerals 100, 101, and 102 each represent circuit blocks constituting an LSI, and the circuit blocks 100, 101 are connected via a traffic buffer circuit 103 having a bidirectional buffer.

Here, a control signal is supplied to the gated buffer connected to the circuit block 100 in this input/output buffer circuit 103, and during testing, this control signal is set to a high (formerly GH) level (hereinafter referred to as H). Under normal conditions, this control signal is set to a low level (hereinafter referred to as L).

Further, an external pin 104 that functions as a test pin or a monitor pin is connected to this human output buffer 7 circuit 103, and when the control signal is set to H, this external pin 104 functions as a test pin and outputs the control signal. When set to L,
It is designed to function as a monitor pin.

Further, 105 is a normal external input pin, 106 is a normal external output pin, and the external input pin 105 is a normal external input pin.
2 and the external output pin 106 is connected to the circuit block 10
1 so that normal data input and output are performed through external input pin 105 and external output pin 106, respectively.

With this configuration, during testing, the control signal to the turnout cover sofa circuit 103 is set to H, and a test signal equivalent to the signal from the circuit block 100 is sent from the external pin 104 to the circuit block 101.

Furthermore, when the control signal to the human output buffer circuit 103 is switched to L, the circuit block 100 is output from the external pin 104.
, 101 can be extracted.

In addition, normal data input and output are external input pin 105,
This is done through external output pin 106.

[Problems to be Solved by the Invention] However, in such a conventional method, one external pin is required to transmit one test signal.
As LSIs become larger in scale, test patterns become more complex, resulting in a problem in that the number of external pins (test pins) for inputting test signals increases.

The present invention has been made in view of these problems, and enables normal data input/output, test signal input, and monitor signal extraction through a common external terminal, thereby making it possible to easily control the LSI to be tested. Even as the scale increases,
An object of the present invention is to provide a cover sofa circuit capable of suppressing an increase in the number of external terminals.

[Means to solve the problem] FIG. 1 is a block diagram of the principle of the present invention.

In this Figure 1, 1 is a bidirectional buffer.

This bidirectional buffer 1 is used for normal data signals, test signals,
It is connected to a common external terminal 5 for inputting and outputting monitor signals, and these signals can be inputted and outputted to this external terminal 5.

2 is a first gate circuit, and this first gate circuit 2 selects the test signal sent through the external terminal 5 and the circuit block output signal sent through the signal input section 6, and outputs the circuit block from the signal output section 7. This is what outputs it as an input signal.

3 is a second gate circuit, and this second gate circuit 3 is capable of selectively outputting the inter-circuit block monitor signal from the signal input section 8 and the circuit block output signal from the signal input section 9. .

Reference numeral 4 denotes a control circuit, and this control circuit 4 receives a normal input/output selection signal, a test data input selection signal, and a monitor output selection signal from signal input sections 10, 11 and 12, respectively. It outputs a puffer control signal and a gate control signal to the bidirectional buffer 1, the first gate circuit 2, and the second gate circuit 3 depending on the input/output.

[Production use] With this configuration, the input/output selection signal during normal operation.

When the test data input selection signal and the monitor output selection signal are set to H or L as appropriate and are supplied to the control circuit 4, the control signal 4 changes to the bidirectional buffer 1 and the first gate circuit 2 depending on whether the test data is input or output during normal operation or during test input/output. and second gate circuit 3
outputs buffer control signals and gate control signals to

This makes it possible to input and output the normal data signal and the monitor signal between the two test signal circuit blocks through the common external terminal 5.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 2, 200, 201, and 202 are LS
Circuit blocks 200 to 2 constitute circuit blocks I.
02 are connected to each other via a human output buffer circuit 300.

Note that the input/output buffer circuit 300 is made into cells,
As shown in Figure 3, there is a gate section (circuit block 2) in the center.
00 to 202 are arranged in this gate part)
A large number of I10 cells are arranged in an array around the SI.

By the way, each input/output buffer circuit 300 has two bidirectional buffers 1 . First gate circuit 2. Second
It is configured with a gate circuit 3 and a control circuit 4.

Here, the bidirectional buffer 1 is a gated buffer 1a
and a buffer 1b in the opposite direction to this buffer 1a. Both buffers la and lb are connected to a common external pin (external terminal) 5 for inputting and outputting normal data signals, test signals, and monitor signals. These signals can be input/output to/from this external pin 5.

The first gate circuit 2 selects the test signal sent through the external pin 5 and the buffer 1b and the output signal from the circuit block 200 (inter-circuit block output signal), and outputs the signal between the circuit blocks to the circuit block 201. It can be output as an input signal.

The second gate circuit 3 selects the inter-circuit block monitor signal between the circuit blocks 200 and 201 and the circuit block output signal from the circuit block 202, and outputs the selected signal to the buffer 1a.

The control circuit 4 is formed by connecting two gate circuits 4a and 4b in two stages, one gate circuit 4a has a gate structure in which one input terminal of an AND gate is an inverting input terminal, and the other gate circuit 4a has a gate structure in which one input terminal of an AND gate is an inverting input terminal. The circuit 4b is N.

It is configured as an R gate. In addition, this control circuit 4
is supplied with a normal input/output selection signal SET, a test data input selection signal INP, and a monitor output selection signal NON from signal input sections 10, 11.12, respectively, and a normal input/output selection signal 43. SET is the test data input selection signal I to the non-inverting input terminal of the gate circuit 4a.
Nf'' is supplied to the inverting input terminal of the gate circuit 4a, and the monitor output selection signal MON is supplied to the input terminal of the gate circuit 4b.The output of the gate 4a is supplied to the gate 4b. It has become.

The output of the gate 4b is supplied as a buffer control signal to the gate of the buffer 1a.

Further, the test data input selection signal INP is supplied as a control signal to the first gate circuit 2, and the monitor output selection signal MON is supplied as a gate control signal to the second gate circuit 3. circuit 4
By receiving the normal input/output selection signal SET, the test data input selection signal INF, and the monitor output selection signal MON, the bidirectional buffer 1. A buffer control signal and a gate control signal can be output to the first gate circuit 2 and the second gate circuit 3.

Note that a changeover switch 14 is provided to switch the normal input/output selection signal SET to H or L.

Next, the relationship between the normal input/output selection signal SET, the test data input selection signal INF, the monitor output selection signal MON, and the functions at that time is as shown in the following table.

With the above configuration, when you want to select the normal output mode during normal operation, as shown in Figure 4, the normal input/output selection signal S
Set ET to H, and set both the test I-data input selection signal INP and monitor output selection signal MON to L.

As a result, the gates of the buffer 1a and the first and second gate circuits 2.3 are both at L (0), so that the output signal from the circuit block 202 is changed to the second gate circuit 3.3. It passes through the buffer 1a and is output from the external pin 5 (see arrow A in FIG. 4). Note that in this case, the inter-circuit block output signal from the circuit block 200 can also be input to the circuit block 201 via the first gate circuit 2.

Also, if you want to select the normal input mode during normal operation, please select the 5th button.
As shown in the figure, the normal input/output selection signal SET is set, and both the test data input selection signal INF and the monitor output selection signal MON are set to B. As a result, the gate of the buffer 1a is set to the H1 first . The second gate circuits 2 and 3 are both L (0
), the input signal from external pin 5 is transferred to buffer 1.
b to the circuit block 202 (see arrow B in FIG. 5). Note that in this case, the inter-circuit block output signal from the circuit block 200 can also be input to the circuit block 201 via the first gate circuit 2.

Furthermore, when you want to select the test signal input mode during testing, as shown in Figure 6, set the normal input/output selection signal SET to H, test data input selection signal INF to H, and monitor output selection signal MON to L. As a result, the gate of buffer 1a becomes H1, the first gate circuit 2 becomes H(1), and the second gate circuit 3 becomes L(0), so the test input from external pin 5 is doubled as buffer lb, It can be input to the circuit block 201 via the first gate circuit 2 (sixth
(See arrow C in the figure).

Furthermore, when you want to select the monitor signal output mode during testing, use the normal input/output selection signal S as shown in Figure 7.
Set ET to H, test data input selection signal INF, and monitor output selection signal MON to H. This results in
The gate of the buffer 1a is low, and the first gate circuit 2 is low (
0), the second gate circuit 3 becomes H(1), so the output signal between the one circuit block 200 and 201 is sent to the second gate circuit 3.0). It can be taken out from the external pin 5 via the buffer 1a (see arrow in FIG. 7). Note that in this case, the inter-circuit block output signal from the circuit block 200 is
It is input to the circuit block 201 via the gate circuit 2.

In this way, the personal output buffer circuit allows normal data input/output, test signal input, and monitor signal extraction through the common external pin 5.
This makes it possible to suppress an increase in the number of external pins even as the scale of LSIs to be tested progresses. Further, along with this, it becomes possible to simplify the test pattern, thereby making it possible to perform more accurate tests on LSIs, which greatly contributes to improving the quality of LSIs.

[Effects of the Invention] As detailed above, according to the input/output buffer circuit of the present invention, normal data input/output and a monitor signal can be taken out to the test signal input section through a common external terminal. Therefore, even if the scale of LSIs to be tested progresses, there is an advantage that an increase in the number of external terminals can be suppressed.

[Brief explanation of the drawing]

FIG. 11 is a block diagram of the principle of the present invention. Figure 2 is a block diagram showing an embodiment of the present invention, Figure 3 is a diagram showing the case where the turntable sofa circuit is made into cells and arranged on an LSI, and Figure 4 shows the normal data output mode selected during normal operation. Figure 5 is a block diagram to explain the operation when normal data input mode is selected, and Figure 6 is a block diagram to explain the operation when normal data input mode is selected during testing. A block diagram to explain the effects of time,
FIG. 7 is a block diagram for explaining the operation when the monitor signal output mode is selected, and FIG. 8 is a block diagram showing a conventional example. In the figure, 1 is a bidirectional buffer, la and lb are buffers, 2 is a first gate circuit, and 3 is a second gate circuit. 4 is a control circuit, 4a, 4b are gate circuits, 5 is an external pin (external terminal), 6.8, 9, 10, 11, 12 is a signal input section, 7.13
is a signal output section, and 14 is a selector switch. 100-101.200-201 are circuit blocks, 30
0 is an input/output buffer circuit. la, lb---1 pa νfa 2---j! 1st circuit 3-m-2nd gamma circuit 4-m-control circuit 4a, 4b--gate circuit 5-1-4 section pins 10 to 12--1 old number input section 14-- - Todate Suishi 1000 300--One output buffer in and out cover sofa circuit Tomose Ruihi and put Nishiki in SL, Shi T; Suke 1 No. 1 No. 1 No. 1 No. 1 No. 1 No. 1 No. Kazumi aflt showing 7 mouths//
Figure 3

Claims (1)

[Claims] The external terminal (5) is connected to a common external terminal (5) for inputting and outputting normal data signals, test signals, and monitor signals.
A bidirectional buffer (
1), a first gate circuit (2) capable of selectively outputting the test signal sent through the external terminal (5) and the output signal from the circuit block, and the monitor signal between the circuit blocks and the circuit block. a second gate circuit (3) that can selectively output an output signal from the bidirectional buffer (1), the first gate circuit (2), and the first gate circuit (2) according to normal input/output or test input/output; An input/output buffer circuit comprising a control circuit (4) capable of outputting a buffer control signal and a gate control signal to a second gate circuit (3).