JPS6085500A - Testing system of memory having built-in highly integrated circuit element - Google Patents
Testing system of memory having built-in highly integrated circuit elementInfo
- Publication number
- JPS6085500A JPS6085500A JP58194772A JP19477283A JPS6085500A JP S6085500 A JPS6085500 A JP S6085500A JP 58194772 A JP58194772 A JP 58194772A JP 19477283 A JP19477283 A JP 19477283A JP S6085500 A JPS6085500 A JP S6085500A
- Authority
- JP
- Japan
- Prior art keywords
- input
- memory
- output terminal
- data
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は高集積回路素子（ＬＳＩ）に論理回路と共に内
蔵する大容量のメモリ回路における試験方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a test method for a large-capacity memory circuit built into a highly integrated circuit device (LSI) together with a logic circuit.
（ｂ） 技術の背景
近年半導体技術特に集積化技術の発達に伴い数千を超え
るゲート数より々る論理回路を１チップに搭載し１パツ
ケージ化したＬＳＩが実現出来るようになシ、データ処
理における例えばマイクロプロセッサのような論理回路
とそのデータ記憶手段として大容量のスタテックランダ
ムアクセスメモリ（ＳＲＡＭ）を備えたＬＳＩが提供さ
れるようになった。こ＼ではこのような大規模な論理回
路と大容量のメモリ回路を内蔵するＬＳＩのメモリ回路
における試験に関するものである。(b) Background of the technology In recent years, with the development of semiconductor technology, especially integration technology, it has become possible to realize LSIs in which logic circuits with more than several thousand gates are mounted on one chip and packaged. For example, LSIs equipped with a logic circuit such as a microprocessor and a large capacity static random access memory (SRAM) as its data storage means have come to be provided. This article is concerned with testing the memory circuits of LSIs that incorporate such large-scale logic circuits and large-capacity memory circuits.
（ｅ） 従来技術と問題点
従来よりメモリ回路の試験は通常論理回路における静的
・動的な機能試験の他に、メモリ回路に特有のビット間
干渉、動作マージン等の試験が存在する。一方上記の内
蔵メモリ回路はＬＳＩパッケージにおけるＬＳＩ入出力
端子数の制約からその内容がメモリ回路だけからなるメ
モ＋１ Ｌ Ｓ Ｉの入出力端子接続と異り、内蔵メモ
リ回路におけるアドレス、制御、およびデータ入出力用
等多数の入出力線は直接ＬＳＩ入出力端子に接続して引
出される入出力端子数の子桁はなく、大半が内部の論理
回路に接続されている。従ってＬＳＩ入出力端子から内
蔵メモリ回路の試験を実行する場合は論理回路経由と彦
るため、メモリ回路へ／から入出力するデータについて
論理回路の影響を受けることなく入出力するのが困難で
あり、上述のような複雛メ、微妙々メモリ試験を期待し
ても精度、試験時間等の面から満足出来る効率的な実現
手段がないという問題点が存在する。(e) Prior Art and Problems Conventionally, memory circuit tests include tests for bit-to-bit interference, operating margins, etc., which are unique to memory circuits, in addition to static and dynamic functional tests for normal logic circuits. On the other hand, the above-mentioned built-in memory circuit is limited to the number of LSI input/output terminals in the LSI package, so its contents consist only of memory circuits. A large number of input/output lines, such as those for input/output, are directly connected to LSI input/output terminals, and there are no child digits of the number of input/output terminals drawn out, and most of them are connected to internal logic circuits. Therefore, when testing the built-in memory circuit from the LSI input/output terminal, the test must go through the logic circuit, which makes it difficult to input/output data to/from the memory circuit without being affected by the logic circuit. However, there is a problem in that there is no efficient implementation means that can satisfy the requirements in terms of accuracy, test time, etc., even if the above-mentioned multiple chicks and memory tests are expected to be performed.
（ｄ） 発明の目的
本発明の目的はこの問題点を除去するため従来と同様に
通常の論理モードにおいてはＬＳＩ入出力端子−輪理回
路一メモリ回路の接続を保持せしめ、メモリ試験モード
においてはその接続を例えばＬＳＩ入出力端子−メモリ
回路の接続に切換えて、メモリ試験モード時だけはＬＳ
Ｉ入出力端子から直接メモ１１回路の試験に必要なデー
タの入出力が実行出来る制御を可能とする接続を実現し
てＬＳＩにおける内蔵メモリ回路を高精度且効率的に試
験する手段を提供しようとするものである。(d) Purpose of the Invention The purpose of the present invention is to eliminate this problem by maintaining the connection between the LSI input/output terminals, the loop circuit, and the memory circuit in the normal logic mode, and in the memory test mode. For example, by switching the connection to the LSI input/output terminal-memory circuit connection, the LSI
The present invention aims to provide a means for highly accurate and efficient testing of built-in memory circuits in LSIs by realizing a connection that enables control to input and output data necessary for testing Memo 11 circuits directly from I input/output terminals. It is something to do.
（ｅ）発明の構成
上記目的は２ｎブロツクよりなる大容量のスタ３−
チックランダムアクセスメモリ（ＳＲＡＭ’）またはリ
ードオンリメモリ（ＲＯＭ）を論理回路と共に内蔵する
高集積回路素子（ＬＳＩ）において、メモリ回路ブロッ
クへ入力する論理回路よりのデータ接続を素子の入出力
端子よりのデータ接続に切換える第１の切換手段、メモ
リ回路ブロックより出力する論理回路へのデータ接続を
素子の入出力端子へのデータ接続に切換える第２の切換
手段ならびに入出力端子より論理回路へのデータ接ａを
直接または／および第１．第２切換手段を介しメモリ回
路ブロックへ至るデータ接続に切換える第３の切換手段
を具備し、通常の論理モードにおいて各切換手段はメモ
リ回路ブロックより論理回路および入出力端子より論理
回路へのデータ接続を保持して、論理回路は入出力端子
よりのデータ入力に従いメモリ回路ブロックにアクセス
し、入出力端子よりデータを送出するデータ処理を実行
すると共に、メモリ試験モードにおいて第１．第２切換
手段は入出力端子より直接メモリ回路ブロックへの入出
力データ接続路および第３切換手段は４−
入出力端子より直接または／および第１．第２切換手段
を介しメモリ回路ブロックに至るデータ接続路を形成し
て、外部試験器により入出力端子を介し印加する入力デ
ータにより論理回路を経由することなく書込みまたは胱
出しデータを入出力端子に得ることを特徴とする高集積
回路素子内蔵メモリの試験方式を提供することによって
達成することが出来る。(e) Structure of the Invention The above object is to provide a highly integrated circuit device (LSI) that incorporates a large-capacity static random access memory (SRAM') or read-only memory (ROM) consisting of 2n blocks together with a logic circuit. A first switching means for switching the data connection from the logic circuit input to the circuit block to the data connection from the input/output terminal of the element; A second switching means for switching the connection and data connection a to the logic circuit from the input/output terminal directly or/and the first. A third switching means is provided for switching the data connection to the memory circuit block via the second switching means, and in the normal logic mode, each switching means connects the data connection from the memory circuit block to the logic circuit and from the input/output terminal to the logic circuit. , the logic circuit accesses the memory circuit block according to data input from the input/output terminal, executes data processing to send data from the input/output terminal, and in the memory test mode, the logic circuit accesses the memory circuit block according to the data input from the input/output terminal. The second switching means connects the input/output terminal directly to the memory circuit block, and the third switching means connects the input/output terminal directly to the input/output terminal or/and the first. A data connection path is formed to reach the memory circuit block via the second switching means, and input data applied via the input/output terminal by an external tester is used to write or eject data to the input/output terminal without passing through the logic circuit. This can be achieved by providing a test method for a memory with a built-in highly integrated circuit element, which is characterized by obtaining the following characteristics.
（ｆ） 発明の実施例
以下図面を参照しつ＼本発明の一実施例について説明す
る。(f) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例における高集積回路素子（Ｌ
ＳＩ）のブロック図、第２図はその第１切換回路部の構
成例図および第３図は第２切換回路部の構成例図を示す
。図において１はＬＳ Ｉ。FIG. 1 shows a highly integrated circuit element (L) in one embodiment of the present invention.
SI), FIG. 2 shows an example of the configuration of the first switching circuit, and FIG. 3 shows an example of the configuration of the second switching circuit. In the figure, 1 is LSI.
２は論理回路、３ａ＋ ｂｌ ｃ＊ ｄはメモリ回路ブ
ロック（ＭＥＭ）、４は第１切換回路部、５は第２切換
回路部、６は第３切換回路部、７はＬＳＩの入出力端子
群、８ａ、ｂ、ｃ、ｄメモリ回路ブロック３ａ−ｄと第
１切換回路部４／第２切換回踏部５とを結ぶデータ伝送
のだめの接続線群、同様に９は第１切換回路部４／第２
切換回路部５と論理回路２との接続線群、１０は第１切
換回路４／第２切換回路部５と第３切換回路部６との接
続線群、１１は論理回路２と第３切換回路部６との接続
線群、１２は論理回路２と入出力端子との接続線群およ
び７１ａ、ｂ・・・７５ｍはそれぞれ特定の接続を有す
る個々の入出力端子である。接続を表示しないＬＳＩ１
周辺における他の入出力端子もまた入出力端子７５ａ−
ｍおよび接続線群１２と同様に論理回路２に接続される
ものとする。2 is a logic circuit, 3a+blc*d is a memory circuit block (MEM), 4 is a first switching circuit section, 5 is a second switching circuit section, 6 is a third switching circuit section, and 7 is a group of LSI input/output terminals. , 8a, b, c, d A group of connection lines for data transmission connecting the memory circuit blocks 3a-d and the first switching circuit section 4/second switching circuit section 5; similarly, 9 is the first switching circuit section 4; /2nd
A group of connection lines between the switching circuit section 5 and the logic circuit 2, 10 a group of connection lines between the first switching circuit 4/second switching circuit section 5 and the third switching circuit section 6, and 11 a group of connection lines between the logic circuit 2 and the third switching circuit section. A connection line group 12 with the circuit section 6 is a connection line group between the logic circuit 2 and input/output terminals, and 71a, b, . . . , 75m are individual input/output terminals each having a specific connection. LSI1 that does not display connections
Other input/output terminals in the periphery are also input/output terminals 75a-
It is assumed that it is connected to the logic circuit 2 in the same way as the connection line group 12 and the connection line group 12.
更に４１ ａ 〜ｄ、４２ ａ−ｄ、５２ ａ−ｄは相
補信号によるスイッチ回路例えばＣＭＯ８によるスイッ
チ回路、５１はアドレスデコーダ、２ケのアンド回路と
１ケのオア回路からなる４３ａ−ｄも表示形式を異にす
るが同様のスイッチ回路、ＩＮＶはインバータ回路、８
１ａ〜ｄは接続線群８ａ−ｄに属する小接続線群、８２
ａ−ｄ、８３ａ〜ｄは接続線群８ａ−ｄに属する接続線
および９１ ａ−ｄ、９２ ａ〜ｄ、 ９３ ａ−ｄは
接続線群９に属する接続線である。尚３１＆〜ｄはＭＥ
Ｍ３ａ−ｄの書込みデータ入力端子、、３２ａ−ｄはメ
モリ回路ブロックコントロール端子および３３ａは読デ
ータ出力端子である。本実施例ではこのように構成され
試験モード信号入力端子７４に０が印加される通常の論
理モード時には第３切換回路部６は入出力端子７２ ａ
−ｃ、７３ ａ−Ｊを論理回路２側に接続し、入力デー
タは入出力端子７５ａ〜ｍより接続線群１２および入出
力端子７２ａ〜ｃ、７３ａ−１より接続線群１１を介し
論理回路２に入出力される。またスイッチ回路４１ａ−
ｄはオン、スイッチ回路４２ａ−ｄはオフ、スイッチ回
路４３ａ−ｄは論理回路２からの接続線９２ａ〜ｄを接
抗接続しているので、ＭＥＭ３ａ−ｄは第１切換回路部
４および第２切換回路部５を介して論理回路２へ接続さ
れて論理モート°動作における論理回路２の制御に従っ
て記憶動作を実行する従来と変りない。Furthermore, 41 a to d, 42 a to d, and 52 a to d are switch circuits using complementary signals, for example, a switch circuit using CMO8, 51 is an address decoder, and 43 a to d consisting of two AND circuits and one OR circuit are also shown. Similar switch circuit, although the format is different, INV is an inverter circuit, 8
1a to d are small connection line groups belonging to connection line groups 8a to d, 82
91 ad, 92 a to d, 93 a to 93 are connection lines belonging to the connection line group 9. Furthermore, 31&~d is ME
M3a-d are write data input terminals, 32a-d are memory circuit block control terminals, and 33a is a read data output terminal. In this embodiment, in the normal logic mode configured in this way and in which 0 is applied to the test mode signal input terminal 74, the third switching circuit section 6 is connected to the input/output terminal 72a.
-c, 73a-J are connected to the logic circuit 2 side, and input data is sent to the logic circuit via the connection line group 12 from the input/output terminals 75a-m and the connection line group 11 from the input/output terminals 72a-c, 73a-1. 2 is input/output. Also, the switch circuit 41a-
d is on, the switch circuits 42a-d are off, and the switch circuits 43a-d connect the connection lines 92a-d from the logic circuit 2, so the MEMs 3a-d are connected to the first switching circuit section 4 and the second switching circuit section 4 This is no different from the conventional method in which it is connected to the logic circuit 2 via the switching circuit section 5 and performs the storage operation under the control of the logic circuit 2 in the logic mode operation.
しかし試験モード信号入力端子７４に１が印加されるＭ
ＥＭ３ａ〜ｄの試験モード時には第３切−ツー
挽回踏部６は入出力端子７２ ａ−ｃ、７３ ａ−７を
第１切換回路部４．第２切換回路部５を介しまたは／お
よび直接Ｍ ＥＭ３ａ−ｄに接続するので、入出力端子
７２ ａ−ｃ、７３ ａ−１より接続線群１１を介し論
理回路２へ入出力されていたデータは切換えられて、試
験モードにおいて外部接続される例えば試験器から／へ
の入出力データは第３切換回路部６より接続ｍ１ｏを介
し、また直接接続される入出力端子７１ａｘｃより印加
される信号と共にＭＥＭ３ａ−ｄヘアクセスされる。即
ち第２切換回路部４では切換スイッチ４１ａ〜ｄがオフ
、４２ａ−ｄがオンとなって、入出力端子７２ｂより入
力される書込みデータはＭＥＭ３ａ〜ｄに並列同時に印
加され書込みを実行する。However, when 1 is applied to the test mode signal input terminal 74, M
In the test mode of EM3a-d, the third switch-to-recovery step section 6 connects the input/output terminals 72a-c, 73a-7 to the first switching circuit section 4. Since it is connected to the MEMs 3a-d via the second switching circuit section 5 and/or directly, the data that has been input/output from the input/output terminals 72a-c, 73a-1 to the logic circuit 2 via the connection line group 11 is is switched, and in the test mode, input/output data from/to an externally connected tester, for example, is transmitted from the third switching circuit section 6 via the connection m1o, together with a signal applied from the directly connected input/output terminal 71axc. MEM3a-d is accessed. That is, in the second switching circuit section 4, the changeover switches 41a-d are turned off and the switches 42a-d are turned on, and the write data input from the input/output terminal 72b is simultaneously applied in parallel to the MEMs 3a-d to execute writing.
尚この時切替スイッチ４３ａ〜ｄは接続線９２ａ〜ｄの
接続をオフとし入出力端子７２ａに印加されるＭＥＭコ
ントロール入力信号によってＭＥＭ３ａ−−ｄをイネー
ブルしているものとする。また読取多動作は入出力端子
７１ａｘｃＫ印加されるメ七り回路ブロックを選択する
例えばメモリアト８−
レスの上位ビットこ＼では４ブロツクを選択するメモリ
アドレス２ビットが入出力端子７１ａ、ｂに印加され第
２切換回路部５のアドレスデコーダ５１に入力されアド
レス信号Ａ１１．に−１，・・・ｎにより指定されるス
イッチ回路５２ａ−ｄの何れかが選択されてＭＥＭ３ａ
−ｄからの読出しデータがその読出しデータ出力端子３
３ａ−ｄから入出力端子７２ｃより送出される。本実施
例では外部に接続した試験器によりＭＥＭ３ａ−ｄにお
ける入出力データが論理回路２を経由することかく制御
出来るので入出力端子数の制約の多いＬＳＩ１における
限られた入出力端子を切換機能によって論理モード用と
試験モード用の両様に切換えて使用することにより 、
Ｍ Ｅ Ｍ ３ ａ−ｄのデータ入出力端子専用として
の入出力端子を増加することなく、外部試験器に接続し
て試験モード時にはＭＥＭ３ａ−−ｄに直接必要なデー
タの入出力が実行出来る制御を実現するＬＳＩにおける
内蔵メモリ回路を高精度に目、効率的に試験出来る試験
方式が得られる。At this time, it is assumed that the changeover switches 43a to 43d turn off the connection of the connection lines 92a to 92d, and enable the MEMs 3a to 3d by the MEM control input signal applied to the input/output terminal 72a. In addition, for multiple read operations, the memory address 2 bits that select 4 blocks are applied to the input/output terminals 71a and 71b. The address signal A11. input to the address decoder 51 of the second switching circuit section 5. One of the switch circuits 52a to 52d designated by -1, . . .
The read data from -d is the read data output terminal 3.
3a-d are sent out from the input/output terminal 72c. In this embodiment, the input/output data in the MEMs 3a-d can be controlled by an externally connected tester through the logic circuit 2, so the limited input/output terminals in the LSI 1, which has many restrictions on the number of input/output terminals, can be controlled by the switching function. By switching and using it for both logic mode and test mode,
Control that allows input/output of necessary data directly to MEM3a--d during test mode by connecting to an external tester without increasing the number of input/output terminals dedicated to data input/output terminals of MEM3a-d. A test method can be obtained that can efficiently test built-in memory circuits in LSIs with high accuracy.
尚上記はメモリ回路ブロックのブロック数２ｎブロツク
を２２＝４ ブロックとして説明したが他の組合せにお
いても同様に実現出来ることはいう造本ない。Although the above description has been made assuming that the number of memory circuit blocks is 2n blocks (22=4 blocks), it is possible to realize the same in other combinations as well.
（ｇ） 発明の詳細
な説明したように本発明によれば切換手段によって論理
モードにおいては従来の機能を失うことなく論理動作に
おけるデータ処理を実行すると共に、メモリ試験モード
においては人出口端子より論理回路への接続を直接メモ
リ回路への試験に必要なデータの入出力が実行出来る接
続を実現１７てＬＳＩにおける内蔵メモリ回路を効果的
に試験する手段を得ることが出来る。(g) As described in detail, according to the present invention, in the logic mode, the data processing in the logic operation is executed without losing the conventional function by the switching means, and in the memory test mode, the logic By realizing a connection to the circuit that can directly input and output data necessary for testing the memory circuit 17, it is possible to obtain a means for effectively testing the built-in memory circuit in an LSI.
第１図は本発明の高集積回路素子（ＬＳＩ）のブロック
図、第２図はその第１切換回路部の構成例図および第３
図は第２切換回路部の構成例図を示す。
図において１はＬＳＩ、２は論理回路、３ａ〜ｄはメモ
リ回路ブロック（ＭＥＭ）、４け第１切換回路部、５は
第２切換回路部、６は第３切換回路部および７はＬＳＩ
の入出力端子群である。FIG. 1 is a block diagram of a highly integrated circuit element (LSI) of the present invention, and FIG. 2 is an example configuration diagram of the first switching circuit section and the third
The figure shows an example of the configuration of the second switching circuit section. In the figure, 1 is an LSI, 2 is a logic circuit, 3a to d are memory circuit blocks (MEM), 4-digit first switching circuit, 5 is a second switching circuit, 6 is a third switching circuit, and 7 is an LSI.
This is a group of input and output terminals.
Claims (1)
セスメモリ（ＳＲＡＭ）ｔたはリードオンリメモリ（Ｒ
ＯＭ）を論理回路と共に内蔵する高集積回路素子（ＬＳ
Ｉ）において、メモリ回路ブロックへ入力する論理回路
よりのデータ接続を素子の入出力端子よりのデータ接続
に切換える第１の切換手段、メモリ回路ブロックより出
力する論理回路へのデータ接続を素子の入出力端子への
データ接続に切換える第２の切換手段ならびに入出力端
子より論理回路へのデータ接続を直接または／および第
１．第２切換手段を介しメモリ回路ブロックへ至るデー
タ接続に切換える第３の切換手段を具備し、通常の論理
モードにおいて各切換手段はメモリ回路ブロックよシ論
理回路および入出力端子より論理回路へのデータ接続を
保持して、論理回路は入出力端子よりのデータ入力に従
いメモリ回路ブロックにアクセスし、入出力端子よりデ
ータを送出するデータ処理を実行すると共に、メモリ試
験モードにおいて第１．第２切換手段は入出力端子より
直接メモリ回路ブロックへの入出力データ接続路および
第３切換手段は入出力端子より直接またけ／および第１
．第２切換手段を介しメモリ回路ブロックに至るデータ
接続路を形成して、外部試験器により入出力端子を介し
印加する入力データにより論理回路を経由すること々く
書込みまたは読出しデータを入出力端子に得ることを特
徴とする高集積回路素子内蔵メモリの試験方式。Large-capacity static random access memory (SRAM) or read-only memory (R) consisting of 2n blocks.
Highly integrated circuit elements (LS
In I), the first switching means switches the data connection from the logic circuit input to the memory circuit block to the data connection from the input/output terminal of the element; A second switching means for switching the data connection to the output terminal and a data connection from the input/output terminal to the logic circuit directly or/and the first. A third switching means is provided for switching the data connection to the memory circuit block via the second switching means, and in the normal logic mode, each switching means connects the data connection from the memory circuit block to the logic circuit and the input/output terminal to the logic circuit. While maintaining the connection, the logic circuit accesses the memory circuit block according to data input from the input/output terminal, executes data processing to send data from the input/output terminal, and in the memory test mode, the logic circuit accesses the memory circuit block according to data input from the input/output terminal. The second switching means connects the input/output terminal directly to the memory circuit block, and the third switching means directly connects the input/output terminal to the memory circuit block.
．． A data connection path is formed to reach the memory circuit block via the second switching means, and input data applied via the input/output terminal by an external tester is used to frequently write or read data to the input/output terminal via the logic circuit. A test method for memory with a built-in highly integrated circuit element, which is characterized by the following:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58194772A JPS6085500A (en) | 1983-10-18 | 1983-10-18 | Testing system of memory having built-in highly integrated circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58194772A JPS6085500A (en) | 1983-10-18 | 1983-10-18 | Testing system of memory having built-in highly integrated circuit element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6085500A true JPS6085500A (en) | 1985-05-14 |
Family
ID=16329983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58194772A Pending JPS6085500A (en) | 1983-10-18 | 1983-10-18 | Testing system of memory having built-in highly integrated circuit element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6085500A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0297821A2 (en) * | 1987-06-30 | 1989-01-04 | Fujitsu Limited | Semiconductor integrated circuit device having gate array and memory |
| EP0310111A2 (en) * | 1987-10-02 | 1989-04-05 | Hitachi, Ltd. | Memory incorporating logic LSI and method for testing the same LSI |
| JPH02292800A (en) * | 1989-05-08 | 1990-12-04 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| WO1997035318A1 (en) * | 1996-03-21 | 1997-09-25 | Hitachi, Ltd. | Data processor with built-in dram |
| JP2017502444A (en) * | 2013-12-02 | 2017-01-19 | シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． | Three-dimensional flash NOR memory system with configurable pins |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5563432A (en) * | 1978-11-07 | 1980-05-13 | Nec Corp | Integrated circuit |
| JPS5835661A (en) * | 1981-08-27 | 1983-03-02 | Toshiba Corp | One-chip microcomputer |
-
1983
- 1983-10-18 JP JP58194772A patent/JPS6085500A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5563432A (en) * | 1978-11-07 | 1980-05-13 | Nec Corp | Integrated circuit |
| JPS5835661A (en) * | 1981-08-27 | 1983-03-02 | Toshiba Corp | One-chip microcomputer |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0297821A2 (en) * | 1987-06-30 | 1989-01-04 | Fujitsu Limited | Semiconductor integrated circuit device having gate array and memory |
| EP0310111A2 (en) * | 1987-10-02 | 1989-04-05 | Hitachi, Ltd. | Memory incorporating logic LSI and method for testing the same LSI |
| JPH02292800A (en) * | 1989-05-08 | 1990-12-04 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| WO1997035318A1 (en) * | 1996-03-21 | 1997-09-25 | Hitachi, Ltd. | Data processor with built-in dram |
| US6327681B1 (en) | 1996-03-21 | 2001-12-04 | Hitachi, Ltd. | Data processor with built-in DRAM |
| JP2017502444A (en) * | 2013-12-02 | 2017-01-19 | シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． | Three-dimensional flash NOR memory system with configurable pins |
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