JPH01116736A - Input/output port system for one-chip microcomputer - Google Patents

Abstract

PURPOSE:To make the detection of trouble location easy, to make the circuits of respective parts into modules as standard circuits and to make a test program common by disconnecting peripheral circuits from a CPU and executing a mode switching with an input output port terminal. CONSTITUTION:The title system is provided with a data bus buffer circuit 1, an input buffer circuit 4 connected to a port terminal, an input latch circuit 5, a data output register 6, a data direction register 2, a 3-state output buffer circuit 3 to output the contents to the port terminal and a circuit 7 to control the selection of a chip and the read/write of the respective registers and provided with a 3-state input buffer circuit 8, an output data multiplexer 9 and an output buffer control circuit 10 able to determine an input output direction derectly from the inside of the chip independently of the data direction register. Thus, test time becomes short, the detection of the trouble location becomes easy and further, the test program can be made common for standard circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input/output port system in a one-chip microcomputer, and particularly to an input/output port system that facilitates testing.

[Conventional technology 1 One-chip microcomputer (hereinafter abbreviated as chip)
As shown in FIG. 2, the CPU (central processing unit) 21
, a memory circuit 22t of ROM (read only memory) and RAM (random access memory), and peripheral circuits 23 such as a timer, CPU peripheral logic and random logic for asynchronous communication, and these circuits 22.23 are
It is connected to the CPU via three buses: a data bus, an address bus, and a control bus, and these buses generally do not appear directly at the terminals of the chip 21, and the terminals may be occupied by input/output ports. many.

FIG. 3 shows a conventional input/output port. Switching between port terminal input and output is performed using data bus buffer 7 circuit 1.
The contents of the data direction register 2, which is set bit by bit by the CPU 21, are determined by the data output cross 77 circuit 3, thereby selecting input or output. To input data from one child, data from a transparent type input latch circuit 5 that latches data from the input buffer circuit 4 is taken into the CPU 21 through the data bus buffer circuit 1.

Further, in order to output data to the port terminal, when data is written to the data output register 6 through the data bus buffer 7 circuit 1, the data is output to the port output terminal. 7 is a circuit that controls chip selection and read/write of each register.

[Problem to be Solved by the Invention 1] When testing only such input/output ports, the following method has conventionally been used.

(1) Method of providing a test program on internal ROM.

(2) A method of loading a test program from the outside into the internal RAM on the chip 21 and testing with the program on the RAM.

In method (1), the program area of the internal ROM that can be used by the user is reduced. In addition, in method (2), R
Since the program on AM is short, sufficient testing cannot be done,
In order to thoroughly test the program, it is necessary to divide the program into several parts and load them, which increases the test time and complicates the creation of the test program. Furthermore, (1
) and (2), the peripheral circuits including the memory are tested via the CPU 21, so the test time is longer (or shorter) than when testing by directly applying signals to the peripheral circuits. Furthermore, it becomes difficult to detect failure locations.Furthermore, there is a problem that it is not possible to standardize test programs for each standard circuit.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a new input/output port that facilitates testing of a one-chip microcomputer.

[Means for solving the problem 1 The one-chip microcomputer of this invention has a CPU
7 data bus buffer circuits that interface the data bus to communicate with the internal data bus, 77 input bag circuits that are connected to port terminals and determine the logic of data at the port terminals, and receive data from the input buffer circuits. An input latch circuit that outputs to the internal data bus, a data output register that receives data to be output from the internal data bus to the output port terminal, and a data direction register that receives data that determines the input/output direction of the port terminal from the internal data bus. , outputs the contents of the data output register to the port terminal based on the output of the data direction register 3
It includes a state output buffer circuit and a circuit that controls chip selection and read/write of each register, and is connected to the line between the input buffer 7 circuit and the input latch circuit, and is connected to the line between the input buffer 7 circuit and the input latch circuit. an output data multiplexer that is located between the data output register and the data output circuit and is capable of directly inputting data from inside the chip; Between the data direction register and the data output buffer circuit, the present invention is characterized by having an output buffer control circuit that can directly determine the input/output direction from within the chip independently of the data direction register. Special Features [Function 1] As in the above configuration, the following operations are possible by switching the modes of the input/output port terminals.

■Testing in normal mode, that is, normal terminals of a 1-chip microcomputer.

■Be able to test the CPU alone, that is, the data bus, address bus, and control bus all appear on the chip's terminals.

■A data bus, an address bus, and a control bus all appear on the terminals, and the peripheral circuits connected to these buses can be disconnected from the CPU, allowing testing to be performed without operating the CPU.

■All three buses appear on the terminals, allowing the CPU to operate and peripheral circuits to be tested.

[Embodiment 1] Fig. 1 is a block diagram showing an embodiment of the input/output port system of a one-chip microcomputer according to the present invention, and the same parts as in the conventional example shown in Fig. 3 are given the same reference numerals. ing.

A three-state input buffer circuit 8 is connected to the line between the input buffer circuit 4 and the input latch circuit 5 and directly transmits data from the input buffer circuit 4 to the inside of the chip.
, data output register 6 and data output cross 77 circuit 3
between the data direction register 2 and the data output circuit 3, which can directly input data from inside the chip, and between the data direction register 2 and the data output circuit 3, which can input data directly from inside the chip independently of the data direction register 2. Output buffer control circuit 10 that can determine input/output direction
is added.

The operation of the input/output port system having the above configuration will be described next.

The output buffer control circuit 10 determines the input/output direction of the port terminal regardless of the data direction register 2. The data input buffer circuit 8 either transmits the data from the input buffer circuit 4 as input data or enters a high impedance state in response to the data control signal.

The output data multiplexer 9 switches between data from the data output register 6 and output data directly input to the multiplexer 9 in response to a data select signal, and transmits the data to the data output puff 77 circuit 3.

1) When inputting from a port terminal like a CPU reset signal, the output balance control circuit 10 sets the data output cover 777 circuit 3 connected to the port terminal to high impedance and enables the data input buffer circuit 8. and enter the data.

1) When outputting to a port terminal like the address bus of a CPU, the data output circuit 3 of the port terminal
is enabled and the output data is input directly to the output data multiplexer 9.

1) In order to output a 3-state bus such as a CPU data bus, the above data input and output cases are repeated in a time-sharing manner, and the data input cover 77 is required at the time of output.
Make circuit 8 high impedance.

[Effect of the invention 1 As explained above, according to the present invention, the peripheral circuit has the following effects:
Since it can be tested separately from the CPU, test time is shortened, which is particularly advantageous in memory testing. or,
Since the circuits of each part, including the CPU, are directly tested, it is easy to detect malfunctioning whistle stations. Further, since the circuits of each part including the CPU are tested independently, commonality of test programs can be achieved by modularizing the circuits of each part as standard circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the input/output port system of a one-chip microcomputer according to the present invention, FIG. 2 is a diagram showing a schematic configuration of the one-chip microcomputer, and FIG. 3 is a diagram showing a conventional input/output port system. FIG. DESCRIPTION OF SYMBOLS 1...Data bus buffer 7 circuit, 2...Data direction register, 3...Data output x7a circuit, 14...Input buffer circuit, 5...Input latch circuit, 6... Data output register, 7...Funtoroll circuit, 8...
- Data input cover 7A circuit, 9... Output data multiplexer, 10... Output puff 7A control circuit. Patent applicant: Ricoh Co., Ltd. Agent: Patent attorney: Aohaku Ao and 1 other person No. 11!1

Claims (1)

[Claims] (1) In a one-chip microcomputer, CP
A data bus buffer circuit interfaces the U data bus and exchanges data with the internal data bus, an input buffer circuit connects to the port terminal and determines the logic of data at the port terminal, and an input buffer circuit receives data from the input buffer circuit and an input latch circuit that outputs to the data bus; a data output register that receives data to be output from the internal data bus to the output port terminal; and a data direction register that receives data that determines the input/output direction of the port terminal from the internal data bus. The input buffer circuit includes a three-state output buffer circuit that outputs the contents of the data output register to a port terminal based on the output of the data direction register, and a circuit that controls chip selection and read/write of each register. A 3-state input buffer circuit is connected to the line between the input buffer circuit and the input latch circuit, and transmits data from the input buffer circuit directly into the chip, and a 3-state input buffer circuit is connected to the line between the data output register and the 3-state output buffer circuit. between the output data multiplexer, which can directly input data from inside the chip, the data direction register, and the 3-state output buffer circuit, and which determines the input/output direction directly from inside the chip, independent of the data direction register. 1. An input/output port system for a one-chip microcomputer, characterized in that it has an output buffer control circuit.