JPH032988A - Microcomputer - Google Patents

Abstract

PURPOSE:To instantaneously switch an external connecting element and to attain high function control by mounting plural data bus I/O terminals for one internal data bus and a control circuit for selecting one of the data bus I/O terminals so as to validate the selected terminal on the same semiconductor. CONSTITUTION:Plural data bus I/O terminals 30, 31 are connected to each internal data bus 4 and one of the plural data bus I/O terminals 30, 31 is validated by a data bus control circuit 32 included in the microcomputer. Thus, one of the plural data bus I/O terminals 30, 31 is validated by a signal inputted from the external or a signal generated in the microcomputer and data are transferred between the validated data bus I/O terminal and an externally connected element connected to the terminal. Consequently, the data bus can be switched without arranging a control circuit on the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer having an internal data bus and data bus terminals for connecting external elements.

[Prior Art] FIG. 3 is a block diagram showing an example of a conventional microcomputer. In the figure, 1 is a microcomputer main body (hereinafter referred to as a microprocessor), and 2 is a circuit that performs control and calculations of the microcomputer (hereinafter referred to as a CPU).
3 is an address bus, 4 is a data bus, 5 is a data bus input/output control signal line, 6 is an address output control circuit, 7 is a data bus input/output control circuit, 8 is an address output terminal, 9 is a data bus The bus input/output terminal 10 is a signal output when data is output from the data bus input/output terminal 9 (
11 is a signal output when inputting data to the data bus input/output terminal 9 (hereinafter referred to as a read signal), 12 is a write signal output terminal, and 13 is a read signal output terminal.

FIG. 4 is a circuit diagram of a simple system using such a microcomputer.

In the figure, 14 is an external connection element such as a first memory, and 15 is an external connection element such as a second memory. Further, 16 is an address input terminal of the external connection element 14, 17 is a data bus input/output terminal of the external connection element 14, and 18 is an address input terminal of the external connection element 14.
19 is a read signal input terminal of the external connection element 14. Further, 20 is an address input terminal of the external connection element 15, 21 is a data bus input/output terminal of the external connection element 15, 22 is a write signal input terminal of the external connection element 15, 23 is a read signal input terminal of the external connection element 15, 24 is an external address bus, 25 is an external data bus, 2
6 is a write signal line, and 27 is a read signal line.Next, the operation will be explained using FIGS. 3 and 4.

The CPU 2 sends instructions, data, etc. to an external connection element 1 such as memory.
4 or 15 (when reading), outputs the address on the address bus 3.

The address output onto address bus 3 enters address output circuit 6 and is output from address bus 8. The address output from address bus 8 is external address bus 2.
4, and is input to the address input terminal 16 of the external connection element 14 and the address input terminal 20 of the external connection element 15. At the same time, a read signal is output from the CPU 2 through the signal line 11 and from the read signal output terminal 13.

Which of the two external connection elements 14 and 15 to which the address input and read signal have been input is determined to be valid is determined by the input address value, and the data bus input from the external connection element 14 or 15 that has become valid is determined by the input address value. Data is output from output terminals 17.21. Data passes through the external data bus 25, is inputted from the data bus input/output terminal 9 of the microprocessor 1, passes through the data bus input/output control port #i7 which is set to the input state by the data bus input/output control signal line 5, The data is input to the CPU 2 through the data bus 4.

On the other hand, the same applies when writing data to the external connection element 14 or 15 such as memory (at the time of writing), the address is output from the CPU 2 to the address bus 3, passes through the address bus control circuit 6, and is output to the address output terminal 8. Ru. At the same time, write data is also output from the CPU 2 to the data bus 4, passes through the data bus input/output control circuit 7 which is set to an output state by the human output control signal line 5 of the data bus 4, and is output from the data bus input/output terminal 9. At the same time, CPU2
The write signal passes through the write signal signal line 10 and is output from the write signal output terminal 12.

Next, the address, write data, and write signal are transferred to the external address bus 24. The external data bus 25 and the write signal line 26 are passed through to the address input terminals 16 and 20 of the external connection elements 14 and 15, respectively. Data bus input/output terminal 17 or 21. Light signal input terminal 1
8 or 22, and a write operation is performed.

[Problem to be solved by the invention]

Since conventional microcomputers are configured as described above, it is necessary to provide an external control circuit when performing control such as switching between a plurality of external data buses.

This invention was made in order to solve the above-mentioned problems with the conventional ones, and its purpose is to insult microcomputers that can switch data buses without providing an external control circuit. do.

[Means to solve the problem]

In the microcomputer according to the present invention, a plurality of data bus input/output terminals are provided for each internal data bus, and one of the plurality of data bus input/output terminals is enabled by an internally provided data bus control circuit. This is how it was done.

[Operation] The microcomputer according to the present invention enables one of the plurality of data bus input/output terminals by an external signal or an internally generated signal, and connects to the enabled data bus input/output terminal. Data is exchanged with external connection elements connected to the device.

(Example〕 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a microcomputer according to an embodiment of the present invention, which has one data bus inside the microprocessor and two data bus input/output terminals for connecting external elements.
This is an example of one thing.

In the figure, the same reference numerals as in FIGS. 3 and 4 indicate the same parts, 28 is the first data bus input/output control circuit, 29 is the second data bus input/output control circuit, and 30 is the first data bus input/output control circuit. bus input/output terminal; 31 is a second data bus input/output terminal;
32 is a control circuit that determines whether to enable the first data bus input/output terminal 30 or the second data bus input/output terminal 31; 33 is a control circuit that enables the first data bus input/output terminal 30; 34 is a control signal for enabling the second data bus input/output terminal 31, and 35 is an external control signal for determining whether to enable the first data bus input/output terminal 30 or the second data bus input/output terminal 31. This is a selection signal input terminal for making a decision based on a signal from.

FIG. 2 is an example of a circuit diagram of a simple system using the microcomputer of the above embodiment.

In the figure, 36 is an external connection element 14 such as a first memory.
A first external data bus 37 is connected to an external connection element 15 such as a second memory, and 38 is a first data bus input/output terminal 30 and a second data bus. This is a selection signal for determining which of the bus input/output terminals 31 is to be enabled.

Next, the operation will be explained. When reading, the CPU 2 sends commands, data, etc. to external connection elements 14 or 15 such as memory.
outputs an address on the address bus 3 to obtain from the address bus 3; The address output onto the address bus 3 enters the address output circuit 6 and is output from the address output terminal 8.

The address output from the address output terminal 8 passes through the external address bus 24 to the address input terminal 16 of the external connection element 14 and the address input terminal 20 of the external connection element 15.
is input. At the same time, a read signal is output from the CPU 2 through the read signal line 11 and from the read signal output terminal 13. Which of the two external connection elements 14 and 15 is valid depends on the address value, but in the case of the present invention, the same address is assigned to both external connection elements 14 and 15, and the pixel element is also valid at the same time. Different read data may be output to both the external data bus 36 and the second external data bus 36 and 37 at the same time.

Next, a case will be described in which both external connection elements 14 and 15 are enabled.

The read data output to the first external data bus 36 is input to the first data bus input/output terminal 30, and at the same time, the read data output to the second external data bus 37 is input to the second data bus input/output terminal. 31, and both read data are input to data bus input/output control circuits 28 and 29, respectively. At this time, a selection signal 38 is input simultaneously from the system (control signal source) side or to select one of the single data. The selection signal 38 passes through the selection signal input terminal 35 and enters the control circuit 32 . The data bus input/output control signal 5 is simultaneously input from the CPU 2 to this control circuit 32, and one of the inputs from the two data bus input/output terminals 30 and 31 is enabled and placed on the internal data bus 4. The other read data is invalid. The valid read data is taken into the CPU 2.

Next, the operation during writing will be explained. The address is output from the CPU 2 to the address bus 3, passes through the address bus control circuit 6, and is output to the address output terminal 8. At the same time, write data is also output from the CPU 2 to the data bus 4, and input/output signals 5 of the data bus are also input to the control circuit 32. At the same time, a selection signal 38 is input from the system side to determine which of the two data bus input/output terminals 30 and 31 is to be enabled, and is inputted to the control circuit 32 through the selection signal input terminal 35. The control circuit 32 uses the human output signal 5 of the data bus and the selection signal 38 to create a signal that enables one of the two data bus input/output terminals 30.31 and disables the other. It is input to input/output control circuits 28 and 29. Write data is output from the enabled data bus input/output terminal 30 or 31, and the external connection element 1 connected to the selected external data bus 36 or 37
Write data is written to 4 or 15.

As described above, according to this embodiment, a plurality of data bus input/output terminals are provided for one data bus, and the required data bus input/output terminal is selected by a control circuit mounted on the same chip. Therefore, any external connection element can be selected at any time.

Therefore, in the case of an emulation microcomputer, for example, the program on the emulator side and the program on the microcomputer embedded system side can be instantly switched, and development efficiency can be improved.

Note that in the above embodiment, during the write operation, only one of the two data bus input/output terminals 30 and 31 is enabled and the other is disabled, but the control circuit 32 is configured so that both are enabled. By doing so, it is also possible to simultaneously output the same write data from both of the two data bus input/output terminals 30, 31, and write the write data to both external connection elements 14, 15.

〔Effect of the invention〕

As described above, according to the microcomputer according to the present invention, there are a plurality of data bus input/output terminals for each internal data bus, and a control circuit that selects one of the plurality of data bus input/output terminals to be valid. Since these are provided on the same semiconductor, external connection elements such as a plurality of memories connected to the microcomputer can be instantly switched, and highly functional control can be performed.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a microcomputer according to an embodiment of the present invention, Fig. 2 is a circuit diagram showing an example of a simple system using the microcomputer of the above embodiment, and Fig. 3 is a block diagram of a conventional microcomputer. Figure, 4th
The figure is a circuit diagram showing an example of a simple system using a conventional microcomputer. In the figure, l is the microcomputer main body (microprocessor), 2 is the control and arithmetic circuit (CPU), 3 is the address bus, 4 is the data bus, 5 is the input/output control signal line of the data bus, and 6 is the address output control circuit. , 7 is a data bus input/output control circuit, 8 is an address output terminal, 9 is a data bus input/output terminal, 10 is a write signal output when data is output from the data bus input/output terminal 9, 11 is a data bus input A read signal is output when inputting data to the output terminal 9, 12 is a write signal output terminal, 13 is a read signal output terminal, 28 is a first data bus input/output control circuit, and 29 is a second data bus input terminal. Output control circuit, 30 is the first
31 is the second data bus input/output terminal, 32 is the first data bus input/output terminal. Second data bus input/output terminal 30
．． a control circuit that determines which of 31 to be enabled; 3;
3 is a control signal for enabling the first data bus input/output terminal 30, 34 is a control signal for enabling the second data bus input/output terminal 31, and 35 is a control signal for enabling the first data bus input/output terminal 31. This is a selection signal input terminal for determining which of the second data bus input/output terminals 30 and 31 is to be enabled based on an external signal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a microcomputer constructed on a semiconductor and having one or more internal data buses, each internal data bus has at least two or more internal data buses for exchanging data with the internal data bus. a data bus input/output terminal for connecting an external element; and a control circuit for selecting one data bus input/output terminal from the at least two data bus input/output terminals and connecting it to the internal data bus. on the semiconductor, wherein the at least two data bus input/output terminals are switched by a signal input from outside the microcomputer or a signal generated inside the microcomputer.