JPH02292800A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To easily set test data in a short time by setting the test data at a data register which sets the test data at a memory in a device via an external setting means having a set/reset function. CONSTITUTION:A set signal and a reset signal are supplied to the data register 3 via an external terminal SET and an external terminal RESET. In other words, the data register 3 which stores the test data for memory test operation in the device is provided with the set function and the reset function every bit, and sets prescribed test data by inputting the set signal or the reset signal from the external terminals SET or RESET. Therefore, the data can be directly set at the data register 3. Thereby, the operating test of a memory 2 can be easily performed also in a short time. Furthermore, since no program for generating the test data is required, no maintenance of the program is required, which reduces expenses.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device for testing a memory within the semiconductor integrated circuit device.

[Prior art] With the recent development of microcomputer systems,
Recently, the technical field related to memory development has shown great progress, as the demand for small-sized systems has increased and given a positive stimulus to the development of memory. A notable result of this development is the increase in memory capacity.

Given an N-bit memory, there are various methods to check whether this memory is operating normally, but in all of these methods, the test time increases as the number of bits increases, making it impractical. This is a problem. Therefore, what is important in memory testing is to test efficiently and within an economical time.

Conventionally, the following memory testing method has been used for the above purpose.

FIG. 3 is a block diagram showing 48 components surrounding a memory in a conventional semiconductor integrated circuit device.

In the figure, the integrated circuit device includes a memory 2 that stores n-bit data at an address indicated by m bits.
, an address register 1 that provides an address value indicated by m bits to the memory 2 as a signal, a data register 3 that outputs n-bit data to the memory 2, and a data register 3.
A NOR circuit 4 and an AND circuit 5 which input n-bit data outputted from the NOR circuit and output n-inputs and one output, and a central processing unit (hereinafter referred to as CPU) 6 which generates n-bit data and outputs it to the data register 3. , a data bus 7 for passing data between the CPU 6 and the data register 3, and output terminals JO and J1 for outputting test result signals.

Note that each component 1 to 7 is connected to each other by a signal line. In addition, the memory 2 is a RAM (R
andom AccessMemor Y) and is the address input signal terminal of memory 2 (not shown).
is given an m-bit address value stored in an address register 1, and n-bit data is input/output to/from a data output terminal (not shown) via a data register 3.

The n-bit output signal from the data register 3 is given to the n-bit data bus 7, and also to the input terminals of an n-input, 1-output NOR circuit 4 and an AND circuit 5, and the output signal of the NOR circuit 4 is supplied to an external terminal. The output signal of the AND circuit 5 is output to the outside via JO, and the output signal of the AND circuit 5 is output to the external terminal J.
1 to the outside. Then, when the output signal obtained from each external terminal is at a level "HIGH" according to the test data, it is determined that the operation of the memory 2 is normal. Therefore, NOR circuit 4 and AND
The circuit 5 constitutes a determination circuit.

Next, a method for testing a memory in a conventional semiconductor integrated circuit device constructed as described above and a circuit operation during testing will be described.

The test is divided into a first mode in which a signal "0" is written and read, and a second mode in which a signal "1" is written and read.

In the first mode, first put memory 2 into write mode,
CPU 6 which is a writing means to all bits of data register 3
The signal “0” is loaded via the data bus 7.

Then, address value “0#” is loaded into address register 1, and test data “0” is written into address 0 of memory 2.

Sequentially change the address value of address register 1 to 1, 2,...
and writes test data "0" to all addresses of memory 2.

After that, set memory 2 to read mode and address register 1.
The address value "O" is loaded into the memory 2, and the data at address O in the memory 2 is read out and stored in the data register 3. At this time, if memory 2 is operating normally, data register 3
The value “0” is stored in , and the output signal of the NOR circuit 4 using the value of the data register 3 is at the level “HIG”.
In other words, writing to address O of memory 2, 0
NOR whether reading from address is working normally
This can be determined based on the output signal of the circuit 4. In the same way, the address values of address register 1 are changed sequentially to 1, 2, .
..., and the write and read operations of data "0#" can be tested for all addresses in the memory 2, that is, for all memory cells of the memory 2, using the output signal of the NOR circuit 4.

In the second mode, first, the memory 2 is put into a write mode, and all bits of the data register 3 are loaded with a signal "1" via the data bus 7. Similarly to the first mode, the address value of the address register 1 is incremented as 0, 1, 2, . . . and test data of the data register 3 is written to all addresses of the memory 2. Thereafter, the memory 2 is set to continuous read mode, and the address value of the address register 1 is again incremented as 011, 2, . . . , and the data stored in the memory 2 is read out and stored in the data register 3. At this time, if the memory 2 is operating normally, the signal "1" is stored in all bits of the data register 3, and the output signal of the AND circuit 5 is at the level "HIGH".
becomes. That is, write data "1" to all memory cells of memory 2, and write data "1" from all memory cells.
1'' read operation can be tested using the output signal of the AND circuit 5.

Here, the internal configuration of memory 2 and its operation will be explained in the fourth section.
This will be briefly explained with reference to the figure.

FIG. 4 is a block diagram showing an example of the configuration of the memory 2. As shown in FIG.

In the figure, a plurality of word lines and a plurality of bit lines are arranged to intersect with each other in a memory cell array 201, and a memory cell is provided at each intersection of the word lines and bit lines.

Memory cell selection is performed by the X address buffer decoder 20
This is based on the intersection of one word line selected by Y address buffer decoder 203 and one bit line selected by Y address buffer decoder 203. Data is written to a selected memory cell, or data stored in that memory cell is read out. Instructions for writing/reading this data are given to the R/W control circuit 204. /Write control signal R/W.

That is, if the read/write control signal R/W is a signal that instructs reading, the memory 2 enters the data read mode, and if the read/write control signal R/W is a signal that instructs writing, Memory 2 enters data write mode. When writing data, input data Din is input to the selected memory cell via the R/W control circuit 204. On the other hand, when reading data, the data stored in the selected memory cell is detected by the sense amplifier 205 and then amplified, and the output data Do is output via the data output buffer 206.
It is output to the outside as ut.

Note that the input data Din and output data DOut are as follows:
The data is written into or read from the memory cell array 201 via the data register 3 shown in FIG. Further, each address value indicated by the X address buffer decoder 202 and the Y address buffer decoder 203 is stored in the address register 1 shown in FIG.
The address value is processed and input to each decoder so that the corresponding word line and bit line can be specified.

[Problem to be Solved by the Invention] Conventionally, testing of memory in a semiconductor integrated circuit device involves generating test data in a CPU, passing it through a data path, loading it into a data register, and then writing it into memory. there was. Therefore, since the test circuit after the CPU itself is treated as a black box, even if the test result is incorrect, it is difficult to identify whether the cause of the error is due to memory operation or CPU operation. Furthermore, since the test data generated by the CPU is input to the test circuit via the data path, the time required to load the test data is included in the test time, which is inefficient. Additionally, each time you change a case in your test data, the CP
Since the program must be changed to generate test data on the U side, there are problems in that maintenance of the device itself, including maintenance of the program, is costly and time consuming.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit device in which the memory operation within the device can be easily tested and the test can be performed in a short time.

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device that tests the operation of a semiconductor memory that stores multiple bits of data at a binary level, data register means for storing data consisting of a plurality of bits corresponding to an address, and the data register means can be set and reset for each bit,
external setting means for providing predetermined test data to be set in the data register means; means for writing the test data set in the external setting means into a corresponding address of the memory; The device includes means for reading the written test data for each address, and means for determining the level of each bit of the test data read by the reading means.

[Operation] In the semiconductor integrated circuit device according to the present invention, test data can be set in the data register for setting test data in the memory in the device via an external setting means newly provided with a set/reset function. This allows test data to be easily and quickly set in memory.

[Example code] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration around a memory in a semiconductor integrated circuit device according to an embodiment of the present invention. The block diagram of the present invention shown in FIG. 1 is improved compared to the conventional block diagram shown in FIG. It is at the point where the signal is given. The other configurations and operations are the same as before.

As in the conventional case, the n-bit output signal from the data register 3 is applied to the n-bit data bus 7 of the semiconductor integrated circuit device, and is also applied to the input terminals of the NOR circuit 4 and the AND circuit 5, each having one output. The output signal of the NOR circuit 4 is outputted to the outside via the output terminal JO, and
The output signal of the AND circuit 5 is outputted to the outside via the output terminal J1. When each output signal is at the level "HIGH" according to the test data, it is determined that the memory 2 is normal.

Next, a method for testing a memory in a semiconductor integrated circuit device according to an embodiment configured as described above and a circuit operation during testing will be described.

The test is divided into a first mode in which the signal "0" is written and read, and a second mode in which the signal "]" is written and read.

In the first mode, first put memory 2 into write mode,
A reset signal is applied to the data register 3 via the external terminal RESET, that is, the signal “0” is applied to the data register 3.
Then, load the address value “0” into address register 1 and write test data “0” to address 0 of memory 2. Sequentially change the address value of address register 1 to 1, 2, etc. Increment and write test data "0" to all addresses of memory 2.

After that, set memory 2 to read mode and address register 1.
The address value "0" is loaded into the memory 2, and the data at address 0 of the memory 2 is read out and stored in the data register 3. At this time, if memory 2 is operating normally, data register 3
A signal "O#" is stored in all bits of the data register 3, and when the value of the data register 3 is input, the output signal of the NOR circuit 4 becomes the level "HIGH".In other words, when writing to address 0 of the memory 2, It is determined whether reading from the address is operating normally based on the output signal of the NOR circuit 4. Similarly, the address value of the address register 1 is sequentially changed to 1, 2, 2, etc.
...and increment all addresses in memory 2,
That is, the write and read operations of data "0" for all memory cells are performed in test 1 using the output signal of the NOR circuit 4.
·do.

In the second mode, first, the memory 2 is put into the write mode, a set signal is applied to the data register 3 via the external terminal SET, and a signal "1" is set to the data register 3.

In the same way as in the first mode, the address value of address register 1 is incremented as 0, 1, 2, etc., and the test data of data register 3 is transferred to all addresses in the memory.
1". After that, set memory 2 to read mode and write the address value of address register 1 again as 0, 1, 2,...
The data stored in the memory 2 is read out and stored in the data register 3. At this time, if the memory 2 is operating normally, the signal "1" is stored in all bits of the data register 3, and the AND circuit 5
The output signal of becomes the level "HIGH". That is, writing data "1" to all memory cells of memory 2 and reading data "1" from all memory cells are ANDed.
The test is performed using the output signal of circuit 5.

Note that it is impossible to input signals from the external terminals SET and RESET at the same time, and signals are input from either the external terminal SET or the external terminal RESET.

Furthermore, in this embodiment, the test data is stored in the data register 3.
Although all bits of the data register 3 are set as signals "1" or "0", each bit of the data register 3 may be a signal "1" and a signal "0" mixedly. I will explain.

FIG. 2 is a block diagram showing the configuration of a data register according to another embodiment of the present invention. In FIG. 2, the data register 3 is a register of n bits 31, 32, . . .
Contains 3n. The registers 31 to 3n of each bit are connected to a human input signal terminal S for manually inputting a signal from an external terminal SET.
, Input signal terminal R1 for manually inputting signals from external terminal RESET Input signal terminal for inputting signals from external terminals other than SET and RESET! and an output signal terminal O for outputting the data in the register to the outside.

Each input signal terminal I is an input terminal 131, ■32,...
13n, and each output signal terminal O is connected to output terminal 031,
It is connected to 032, . . . , 03n.

In this case, the NOR circuit 4 and the AND circuit 5 constituting the determination circuit are arranged so that their input signals are aligned when the memory 2 is operating normally, and the signal "02" for the NOR circuit 4 is aligned.
As for the AND circuit 5, a circuit for determining the signal may be appropriately provided on the signal line connected to each circuit so that the signals "1°" are aligned.

In FIG. 2, for example, when a signal is input manually from the external terminal SET, registers 31, 32, . . . 3n-1, 3
Signals 0, 1, ..., 0, 1 are set in n in order, and when a signal is input from the external terminal RESET, register 3
1, 32, ..., 3n-1, 3n are sequentially 1, 0, ...
..., 1, 0, and the signals are set.

Further, in this embodiment, the method of incrementing the address value of the address register 1 may be such that data whose count is controlled by the CPU or the like is loaded into the address register 1, and the method is not specified. In addition, the memory 2 that is output via the data register 3
The correctness of the test data is judged by a judgment circuit consisting of a NOR circuit 4 and an AND circuit 5, but if there is a means that can judge the correctness of the test data, the configuration of the judgment circuit can be specified. isn't it.

[Effects of the Invention] In the semiconductor integrated circuit device according to the present invention, the data register that stores test data for memory operation tests in the device has a set function and a reset function for each bit, and Predetermined test data is set by inputting a set signal or a reset signal from a terminal. Therefore, since data can be set directly in the data register, memory operation tests can be performed easily and in a short time.Furthermore, since no program is required to create test data, there is no need to maintain the program, resulting in cost reductions. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration around a memory in a semiconductor integrated circuit device according to an embodiment of the present invention. Figure 2 shows
FIG. 3 is a block diagram showing the configuration of a data register according to another embodiment of the present invention. FIG. 3 is a block diagram showing the configuration around a memory in a conventional semiconductor integrated circuit device. FIG. 4 is a block diagram showing an example of the configuration of the memory 2 shown in FIGS. 1 and 3. FIG. In the figure, 1 is an address register, 2 is a memory, 3 is a data register, 4 is a NOR circuit, 5 is an AND circuit, and J
O and J1 are output terminals, and SET and RESET are external terminals. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A semiconductor integrated circuit device for testing the operation of a semiconductor memory that stores data of multiple bits at a binary level, the device storing data consisting of a plurality of bits corresponding to an address of the memory. The data register means and the data register means can be set and reset for each bit, and the data register means is provided with an external device for applying a set or reset signal from the outside in response to predetermined test data to be set in the data register means. setting means; means for writing test data set in the external setting means into corresponding addresses of the memory; means for reading out the test data written by the writing means for each address; and the reading means. 1. A semiconductor integrated circuit device, comprising: means for determining the level of each bit of test data read by a semiconductor integrated circuit device.