JP2000011700A - Method and circuit for test of rom - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method and a circuit in which an increase in the scale of hardware is suppressed to a minumum and in which whether memory data in a ROM is good or not can be judged at high speed. SOLUTION: In a ROM 10, a clock digit 15 as a numerical value in which a signature is set as 0 at a time when memory data MD on all addresses 0000H to FFFFH containing the address FFFFH is logic-compressed to the address FFFFH is stored in advance. In a test, the memory data MD on all the addresses 0000H to FFFFH is read out so as to be logic-compressed, and signature bits CD1 to CD4 are output. When values of the signature bits CD1 to CD4 are 0, they are judged to be good. When they are other than 0, they are judged to be defective.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ROM (Read
More specifically, the present invention relates to a test method for an only memory (read only memory) and a ROM test circuit, and particularly relates to a large-scale ROM.
The present invention relates to a ROM test method and a ROM test circuit for efficiently executing a test.

[0002]

2. Description of the Related Art Conventionally, as a method of testing a ROM of this type incorporated in a microprocessor or the like, an instruction and hardware for dumping ROM memory data are provided.
A conventional first ROM test method in which words are output to the outside of the chip for comparison with an expected value, and a data compressor is connected to an output section of the ROM and controlled by a control circuit, so that a memory of a plurality of words is output. There is a second conventional ROM test method in which data is compressed and output to the outside of the chip to compare with an expected value.

Further, a third conventional ROM test method and RO method disclosed in Japanese Patent Application Laid-Open No.
The M test circuit arranges the complement of the sum of all the effective storage data of the ROM code (memory data) in the free area of the memory data, sets all remaining free areas to 0, and adds the entire ROM code. When the result becomes 0, pass / fail is determined.

Referring to FIG. 3, which schematically shows memory data and checksum data of a ROM in a third conventional ROM test method described in Document 1, the conventional ROM 100 to be tested has a memory address 101, Bit 102 of the memory data and valid storage data 103
, Invalid storage data 104, and checksum data 10
And 5.

[0005] Next, referring to FIG.
The method of testing M will be described first.
All stored data from 000 to FFFF are read and added. Next, the complement of "1" of the addition result is taken and written as the checksum data 105 at the address FFFF. In order to actually determine the quality of the data stored in the memory, all data from the address 0000 to the address FFFF is read, and the total sum is obtained. If the sum is FF, that is, 11111111, the data in the memory is determined to be "good", and if the value is any other value, it is determined to be "fail".

In this example, a memory having an 8-bit width and having a capacity from address 0000 to FFFF has been described. However, the number of bits and the capacity of the memory are not limited and can be freely set.

However, this conventional third ROM test method and ROM test circuit require a hardware capacity of peripheral circuits such as an adder and a register for temporarily retaining data as the data to be tested increases as the memory capacity increases. The number of hardware increases, and the test time increases due to the increase in the number of data transfers.

The configuration and operation of the pass / fail judgment circuit of the ROM to be tested are not shown, and the specificity is lacking.

[0009]

The above-described first conventional ROM test method and the conventional ROM test circuit are described as follows.
To check the memory data of each word one by one
There is a drawback that when the OM is large-scale, the number of expected values also becomes enormous. Further, there is a drawback that the number of times of data transfer between the ROM and the test system is increased, which causes an increase in test time.

In the second conventional ROM test method and ROM test circuit, since the comparison check is performed after compressing the memory data, the number of expected values is small, the number of transfers is reduced, and the test time is reduced. However, since the memory data is compressed, it is difficult to specify the physical location where the error has occurred.

In the third conventional ROM test method and ROM test circuit, all the memory data in the ROM are added as they are. Therefore, when the ROM becomes large-scale, an adder and a register for temporarily holding data are used. However, there is a drawback that the scale of hardware including peripheral circuits such as the above increases, and the increase in the number of data transfers between the ROM and the test system causes an increase in test time.

An object of the present invention is to provide a ROM test method and a ROM test circuit capable of minimizing an increase in hardware scale and determining the quality of memory data of a ROM at a high speed.

[0013]

According to the ROM test method of the present invention, a read-only memory (RO) to be tested during a test is provided.
M) by reading memory data corresponding to each address from the M), and determining whether the ROM is good or not, wherein the ROM stores all addresses in a predetermined range including the check address in a memory area of a predetermined check address. When the corresponding memory data is subjected to a predetermined logical compression, a check digit, which is a numerical value that sets the signature as a result of the compression to 0, is stored in advance, and the memory data at all the addresses is read out during the test to perform the logical compression. The signature is output, and when the value of the signature is 0, it is determined to be good, and otherwise, it is determined to be bad.

A ROM test circuit according to the present invention is a ROM test circuit for reading memory data corresponding to each address from a read-only memory (ROM) to be tested during a test and judging the quality of the ROM.
However, when a predetermined logical address of the memory data corresponding to all addresses in a predetermined range including the check address is subjected to a predetermined logical compression in a memory area of a predetermined check address, a check digit which is a numerical value with a signature of 0 as a compression result is set to 0. An address generation circuit that stores in advance and generates a test address in response to the supply of a test mode signal, and a parallel serial that converts memory data corresponding to the test address read from the ROM into parallel-serial data and outputs serial memory data A conversion circuit, logical compression means for logically compressing the serial memory data and outputting a signature as compressed data, and an OR circuit for outputting a test result output by a logical OR operation of each bit of the signature. ing.

[0015]

FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG. 1, a ROM test circuit according to the present embodiment shown in FIG. 1 responds to the supply of a test mode signal TM. An address generation circuit 1 for generating a test address AD, a parallel-serial conversion circuit 2 for converting the memory data MD corresponding to the address AD read from the ROM 10 to be tested into parallel-serial data and outputting serial data SD; And a linear feedback shift register (LFS) for logically compressing and outputting bits CD1 to CD4 of compressed data (hereinafter, signature).
R) 3 and an OR circuit 4 that outputs a test result output TO by an OR operation of the signatures CD1 to CD4.

The LFSR 3 is a cascade-connected flip-flop 31-34 for outputting the signature bits CD1-CD4, respectively, and a signal EX by an exclusive OR operation of the serial memory data SD and the signature bit CD4.
2 and an exclusive OR circuit 35 that outputs a signal EX1 by performing an exclusive OR operation of the signature bit CD3 and the signal EX2.

The ROM 10 has addresses 0000H to FFFFH as memory addresses 11 and can store arbitrary memory data from addresses 0000H to FFFEH.
Is stored as the check digit 15 together with the memory data from the address 0000H to the FFFEH, that is, the signature obtained as a result of logically compressing all the memory data MD from the address 0000H to the FFFFH by the LFSR3 is 0. Value.

It is known, for example, from Japanese Unexamined Patent Publication No. 4-33134 that a value that makes the signature of the output of the LFSR zero can be obtained by an operation unique to the LFSR.

Next, the operation of the present embodiment will be described with reference to FIG.
Then, the address generation circuit 1 is activated to generate the addresses AD in ascending order in the range from 0000H to FFFFH, and to supply them as the memory address 11 of the ROM 10. The ROM 10 outputs all the memory data MD in the ascending order of the address AD and supplies it to the parallel-serial conversion circuit 2. The parallel-serial conversion circuit 2 converts the memory data MD into serial data SD and supplies the serial data SD to the LFSR 3. The LFSR 3 performs logical compression of all the serial data SD corresponding to the memory data MD of the ROM 10,
The signature bits CD1 to CD4 are output.

The ROM 10 stores addresses 0000H to F
A value such that the signature obtained as a result of logically compressing all the memory data MD up to FFFH by LFSR3 is set to 0 is stored in advance as a check digit 15 in FFFFH which is the final address. When all the memory data MD are normal, the output of all the signature bits CD1 to CD4 of the LFSR3 becomes 0. Therefore,
These signature bits CD1 to CD4 of the OR circuit 4
Is also 0.

If the memory data MD is not normally output, the signature bit CD output from the LFSR 3 is output.
Since any or all of 1 to CD4 do not become 0, the test result output TO becomes 1.

As described above, after outputting the memory data MD of all addresses AD, the test result output TO becomes 0 when all the memory data MD of the ROM 10 are normal, and the test result output TO becomes 0 when the memory data MD is not normal. Since it is set to 1, it is possible to distinguish between a normal ROM to be tested and a non-normal ROM.

The ROM test circuit according to the present embodiment is configured such that the test mode signal TM and the terminal T
BIST (B) for automatically testing the ROM 10 by supplying the clock CLK from outside via
(Wilt In Self Test) circuit. Therefore, even when some or all of the memory data in the ROM 10 is changed, the ROM
It is not necessary to change the expected values of the external input signal and the external output signal.

In this embodiment, LFS is used as compression means.
Although R is used, it is apparent that the use of other compression means has the same effect.

Next, a second embodiment of the present invention will be described with reference to FIG. 2 in which constituent elements common to those in FIG. The difference of the present embodiment from the above-described first embodiment is that, in addition to the check digit 15 arranged at the address FFFFH instead of the ROM 10 to be tested, the address FFF
ROM 1 with check digit 16 located in EH
0A.

The check digit 16 contains the memory data M
The signature obtained as a result of logically compressing 0000H to 7FFFH of D by LFSR3 is set to O.

The check digit 15 is such that the signature obtained by compressing the entire memory data MD by the LFSR 3 is O, as in the first embodiment.

In operation, when the test mode signal TM becomes 1, the address generation circuit 1 is activated to generate addresses AD in the range from 0000H to 7FFFH in ascending order, then generate FFFEH, and then generate FFFEH. 80
00H to FFFDH are generated in ascending order.
FH is generated and supplied to the ROM 10.

In the first embodiment, if the address AD does not reach the address where the check digit 15 of the memory data exists, that is, FFFFH, the ROM 10
Cannot be determined, the test time becomes longer when the size of the ROM 10 is large.

In this embodiment, the test time can be reduced by providing a plurality of check digits in the memory data.

[0031]

As described above, the ROM test method and the ROM test circuit according to the present invention provide a ROM test method for logically compressing memory data corresponding to all addresses in a memory area of a predetermined check address. A check digit with the resulting signature set to 0 is stored in advance, the memory data of all addresses is read out at the time of testing, logical compression is performed, and a signature is output. If the value of the signature is 0, it is determined to be good; otherwise, it is determined to be defective. Therefore, there is an effect that a circuit for determining whether or not the ROM is normal is only a simple OR circuit.

Also, by storing a check digit such that the result of logical compression becomes 0 regardless of the value of the memory data, the pass / fail judgment is made only by the OR circuit. Even if some or all of the above are changed, there is an effect that the circuit does not need to be changed.

Further, even when part or all of the memory data of the ROM is changed, there is an effect that it is not necessary to change the expected values of the external input signal for test and the external output signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a ROM test circuit according to the present invention.

FIG. 2 is a block diagram illustrating a ROM test circuit according to a second embodiment of the present invention;

FIG. 3 shows RO in a conventional third ROM test method.
FIG. 4 is an explanatory diagram schematically showing an example of M memory data and checksum data.

[Description of Signs] 1 address generation circuit 2 parallel-serial conversion circuit 3 linear feedback shift register (LFS)
R) 4 OR circuit 10, 10A, 100 ROM 11, 101 Memory address 15, 16 Check digit 31-34 Flip-flop 35, 36 Exclusive OR circuit

Claims (7)

[Claims] 1. A ROM test method of reading memory data corresponding to each address from a read-only memory (ROM) to be tested at the time of a test and judging whether the ROM is good or not, wherein the ROM has a predetermined check address. When the memory data corresponding to all addresses in a predetermined range including this check address is logically compressed in a predetermined area, a check digit, which is a value obtained by setting a signature as a compression result to 0, is stored in advance in the memory area. Reading out the memory data at the address of (i), performing the logical compression and outputting the signature, and determining that the value of the signature is 0 is good, and that otherwise, it is bad. 2. The ROM testing method according to claim 1, wherein said logical compression is performed using a linear feedback register. 3. The method of testing a ROM, wherein the number of the check digits is one, and all addresses in the predetermined range are all addresses of the ROM. 4. The ROM has first and second check digits, and a first address range obtained by dividing all addresses of the ROM is a first predetermined range corresponding to the first check digit. , And the second address range is the second address corresponding to the second check digit.
2. The ROM testing method according to claim 1, wherein all addresses in a predetermined range are set. 5. A ROM test circuit which reads memory data corresponding to each address from a read-only memory (ROM) to be tested at the time of a test and determines whether or not the ROM is good or not, wherein the ROM has a predetermined check address. When the memory data corresponding to all addresses in a predetermined range including the check address is logically compressed in a predetermined area, a check digit, which is a numerical value with a signature of 0 as a compression result, is stored in advance in a memory area, and a test mode signal An address generation circuit that generates a test address in response to the supply, a parallel-to-serial conversion circuit that performs parallel-to-serial conversion on the memory data corresponding to the test address read from the ROM, and outputs serial memory data; Is logically compressed to be compressed data A logical compressing means for outputting the signatures, test circuit ROM, characterized in that it comprises an OR circuit for outputting a test result output by the logical OR operation of each bit of the signature. 6. The ROM test circuit according to claim 5, wherein said logical compression means includes a linear feedback shift register for outputting said signature of a predetermined number of bits. 7. The linear feedback shift register is configured to output first to fourth flip-flops respectively outputting the first to fourth bits of the signature, and exclusive control of input serial memory data and a fourth bit of the signature. A first exclusive OR circuit that outputs a first exclusive OR signal by a logical OR operation; and a first exclusive OR circuit that performs an exclusive OR operation on a third bit of the signature and the first exclusive OR signal. 7. The ROM test circuit according to claim 6, further comprising: a second exclusive OR circuit that outputs two exclusive OR signals.