JP3003059B2 - Application specific integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an application specific integrated circuit (ASIC (Application Spec.)) Having a ROM storing microcode and employing a microprogram control method.
In particular, it is an improvement that simplifies the test operation of this circuit.

[0002]

2. Description of the Related Art Recently, in designing an application-specific integrated circuit (hereinafter, referred to as an ASIC) which is an element constituting a computer system, various functions are integrated into one LSI.
The ASIC itself tends to be large-scale or complicated in order to incorporate it into C, and it has become an important issue how to efficiently test a single chip to ensure high reliability.

FIG. 3 shows an example of a general ASIC to which the present invention is applied and which has a ROM storing microcode and employs a microprogram control method. In this figure,
The ASIC 10 includes a microprogram control unit 20 that operates in synchronization with an externally applied system clock CP.
And a plurality of modules M1 and M operated by the microcode output from the microprogram control unit 20.
2, ..., Mn. Micro program controller 2
0 is an address sequencer 21 for generating a micro address MICA by an external system clock CP, a ROM 22 for receiving a micro address MICA and outputting a microcode I, and holding and outputting a microcode I for receiving a system clock CP. Pipeline register 23,
It has a decoder 24 for decoding it in the form of microcode I. The plurality of modules M1, M2,.
For example, it is a block corresponding to a memory readout circuit, a CRT control circuit, a timer, and the like. Such an ASIC10
In general, the microcode I is output from the microprogram control unit 20 according to the system clock CP, and the operation of the modules M1, M2,...

Here, RO storing microcode I
For example, M22 is assigned an internal capacity as shown in FIG. That is, 512 steps of micro addresses $ 000 to $ 1FF store microcodes for normal operation, and the next 1536 steps of micro addresses $ 200 to $ FFF correspond to the AS.
Test microcode for testing the IC 10 is stored. Then, in the case of the normal operation, the microcode is read from the microaddress $ 000 to $ 1FF, and when the ASIC 10 is tested, the microaddress is $ 200.
The test microcode is read from ~ $ FFF.

[0005]

SUMMARY OF THE INVENTION As described above, the conventional A
The SIC test method is based on each module M in the ASIC10.
As the functions of M1,..., Mn become more complicated or larger, the number of steps of the test microcode also increases and the capacity of the ROM 21 increases, and the scale of the ASIC 10 itself becomes larger and the system becomes smaller. A problem has arisen in that it cannot meet the demand for conversion. In addition, as the capacity of the ROM 21 increases, the probability of occurrence of a failure in the ROM 21 itself increases, and it is not easy to secure high reliability as a single chip, and a test pattern (microcode for testing) is created. There was also a problem that the work of assembling it takes time.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem, and an object of the present invention is to enable a test of a single ASIC chip having a ROM for storing microcode to be efficiently executed.

[0007]

According to the present invention, there is provided an address sequencer for generating a microaddress in response to a system clock, a ROM for outputting microcode corresponding to the microaddress, and a ROM for outputting a microcode corresponding to the microaddress. An application specific integrated circuit comprising: a microprogram control unit having a pipeline register for temporarily holding the microcode in synchronization with a clock; and a plurality of modules controlled by the microprogram control unit. A micro-address terminal for outputting the micro-address generated at the outside, a micro-code input terminal for receiving a micro-code from the outside, a mode input terminal for inputting a test mode, and usually a micro-code from the ROM. Select the model If the test operation to de input terminal is specified is an application specific integrated circuit, characterized in that by selecting the microcode is provided a multiplexer providing to said pipeline register from said micro-code input terminal.

[0008]

When the test operation is designated, the application specific integrated circuit of the present invention receives an external microcode via the microcode input terminal and supplies it to the pipeline register, and in accordance with the external microcode. Perform a test operation.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an application specific integrated circuit (ASIC) according to the present invention. FIG. 1 shows an ASIC 10 according to the present invention, and the conventional ASIC 10 shown in FIG.
Those having the same sign as C10 have the same function. More specifically, the ASIC 10 of the present invention comprises a microprogram control unit.
Micro address MICA for address sequencer 21 in 20
Micro-address pin pA that transmits the test mode to the outside, and a mode input pin that inputs the test mode TMOD specified from the outside
pM, a microcode input terminal pI that accepts microcode from outside, and a test mode input terminal pT
When the test mode signal TMOD is received and the normal operation is specified instead of the test operation, the microcode I from the ROM 22 is selected, and when the test operation is specified, the microcode given from the outside is selected. And a multiplexer 25 for outputting to the pipeline register 23. Note that the pipeline register
23 sets a microcode at the rise of the system clock CP. When the test mode signal TMOD is “1”, the test operation and the test mode signal
When TMOD is "0", normal operation is specified. This allows
The microcode used at the time of the test may be supplied from the outside, and the built-in ROM 22 may store only the microcode used at the normal time. Therefore, even if the modules M1, M2,..., Mn to be tested become large-scale and complicated, microcode for the test is provided from the outside, so that the capacity of the ROM 22 does not increase.

Next, the AS of the present invention configured as described above will be described.
The operation of the IC 10 will be described. During normal operation, the test mode signal TMOD is “0”, and the multiplexer 25
, Mn, are supplied to the pipeline register 23 to control the modules M1, M2,..., Mn. At the time of the test operation, it is as follows. First, the test mode input TMOD is set to “0”. As a result, the multiplexer 25 selects and outputs the test microcode from the outside and supplies it to the pipeline register 23. Therefore, as shown in FIG.
Is installed, the microcode is read from the external test ROM and executed at every system clock.

FIG. 2 shows an example of the internal configuration of the test ROM. This test ROM is in page format, and each module M1 and M1 is stored in 512 steps of the same address space $ 000 to $ 1FF.
If M2,..., Mn are made to correspond, it is easy to execute the test operation. That is, RO for testing the module M1
If Mn1 is allocated and ROMn2 is allocated for the test of the module M2, and sequentially allocated in the same manner, the test program may be stored in the corresponding test ROM for each module.
Since M may be selected, efficiency is high. Specifically, when the test is started, a test microcode is obtained from the ROMn1 corresponding to the module M1, and the test is performed. When the test of the module M1 is completed, the module is read from the ROMn2.
The test microcode for M2 is read and executed, and thereafter, the test is similarly performed up to the module Mn.

As described above, normally, the microcode is read from the built-in ROM and executed, and at the time of the test,
Since the test microcode stored in the virtual external ROM or the like is read and executed, it is not necessary to store the test microcode in the ASIC.

[0013]

As described above, according to the application specific integrated circuit of the present invention, the terminal for outputting the micro address in the micro program control unit, the terminal for inputting the micro code from the outside, the test A terminal for inputting a mode signal is provided, and when the test mode signal specifies a test, an external microcode is input to execute the test, so the test microprogram is stored in the internal ROM. It does not need to be stored, and the capacity of the internal ROM does not need to be increased for the test. In addition, since the test microprogram is provided from the outside, it is possible to easily modify and add the test microprogram. Furthermore, since the capacity of the ROM does not need to be large, the probability of occurrence of a failure in the internal ROM itself can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an application specific integrated circuit embodying the present invention.

FIG. 2 is a diagram showing the internal configuration of an external ROM in the circuit of the present invention.

FIG. 3 is a block diagram of a conventional application specific integrated circuit.

FIG. 4 is a diagram showing an internal configuration of a ROM in the circuit shown in FIG.

[Explanation of symbols]

 10 Application Specific Integrated Circuit 20 Micro Program Controller 21 Address Sequencer 22 ROM 23 Pipeline Register 24 Decoder 25 Multiplexer M1, M2,…, Mn Module

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G01R 31/28-31/3193 G06F 11/22 H01L 21/66 H01L 21/82 H01L 21/822 H01L 27 / 04

Claims (1)

(57) [Claims] 1. An address sequencer for generating a microaddress in response to a system clock, a ROM for outputting a microcode corresponding to the microaddress, and a pipeline for temporarily holding the microcode in synchronization with the system clock A microaddress for outputting a microaddress generated by the address sequencer to an external device in an application specific integrated circuit including a microprogram control unit having a register and a plurality of modules controlled by the microprogram control unit; Terminal, a microcode input terminal for receiving a microcode from the outside, a mode input terminal for inputting a test mode, and a microcode from the ROM normally selected, and a test operation is designated to the mode input terminal. Is A multiplexer for selecting a microcode from a microcode input terminal and applying the selected microcode to the pipeline register.