JPS61261895A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To execute a highly speedy test by changing over and outputting a signal to measure whether or not outputs of plural memory cells are coincident to written data and the signal selected from plural reading signals. CONSTITUTION:When a change-over signal phi1 is L and is in operation usually, an AND circuit 110 is opened through an inverter 109, an OR circuit 108, the reading output of plural memory cells from a memory array 101 is selected and outputted through the circuit 110. On the other hand, when the signal phi1 is H and the test action is executed, a gate 110 is opened through an OR circuit 107. Deciding results L and H outputted by an exclusive OR circuit 106 in accordance with respective the coincidence and the dissidence of the reading output of plural memory cells in which the same writing signal phi2 is written and the signal phi2 are outputted through circuits 108 and 110, and by the simultaneous processing of plural memory cells, the highly speedy test of the memory cell array can be executed without providing the output data pin, the output pad, etc.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor memory device.

[Technical background of the invention and its problems]

In recent years, semiconductor memory devices have become increasingly labor intensive, and testing times have accordingly become longer and longer.

For example, in the case of an IMbit dynamic RAM operation test, read cycles and write cycles are repeated 10 times.
In a simple test method using an ON pattern, if the time for one cycle is 500 n5ec, the time for one test is approximately 5 seconds, and the
This means that it takes 16 times as long as a 64Kbit dynamic RAM.

Therefore, how to efficiently shorten test time has become an important issue.

Conventional methods are used to speed up testing. The first method is to use a high-speed special mode.

For example, it is a high-speed special mode such as page mode, nibble mode, static column mode, etc., and the operating time can be reduced from 2/3 to 1/2 of the normal mode. However, such a special mode test may be unnecessarily severe, making it unsuitable for semiconductor memory devices in the development stage. In addition, this special mode test had a problem in that tests such as timing parameter measurements could not be performed.

Second, there is a partial operation test that tests not all memory cells but some memory cells of a semiconductor memory device. However, in this test, even if memory cells other than those tested are defective, it cannot be detected, so there is a problem that the range of use is limited.

Third, during testing, there is a method that outputs multiple bits in parallel to reduce operating time. However, since it is not possible to secure a large number of pins for testing at the product stage, there is a problem in that testing can only be performed at the wafer stage. Further, even when testing is performed at the wafer stage, there is a problem in that it is necessary to provide output pads for devices 1 to 1.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a semiconductor memory device that can be tested at high speed even at the product stage.

[Summary of the invention]

In order to achieve the above object, the semiconductor memory device according to the present invention selects output signals from a plurality of memory cells by the selection means and outputs them from the output means during normal operation, and outputs the output signals from these memory cells during testing. The present invention is characterized in that a determination signal for determining whether or not the signal is a write data signal is outputted from the same output means.

[Embodiments of the invention]

FIG. 1 shows a semiconductor memory device according to an embodiment of the present invention. Memory array 101 has a large number of memory cells. Four data lines 111 are connected to this memory array 101, and these data lines 111 are connected to a multiplexer 102. The multiplexer 102 is
From these four data lines 111, the address signal Add
Outputs the data line signal specified by . This output signal is input to the switching circuit 103. On the other hand, data line 11
1 are connected to data lines 112 for des 1 to 1, respectively,
These test data lines 112 are connected to a multi-input exclusive OR circuit 106.

A write data signal φ2 to the memory cell is also input to this exclusive OR circuit 106. Exclusive OR circuit 10
The output signal of 6 is input to the switching circuit 103.

The switching circuit 103 switches and outputs the signal from the multiplexer 102 and the signal from the exclusive OR circuit 106 in response to the switching signal φ1. As shown in FIG.
, and an AND gate 110. The output signal φ1 from the multiplexer 102 is input to the OR gate 107. The switching signal φ1 inverted by the inverter 109 and the output signal from the exclusive OR circuit 106 are input to the OR games 1 to 108.

The output signals of OR gate 107 and OR gate 108 are input to AND gate 110, and a switched signal is output from AND gate 110. This signal is amplified by output buffer 104 and output from an output data pin (not shown) via output pad 105.

Next, the operation will be explained. In the case of normal operation, predetermined data is first written into memory cells in memory array 101. This write data is transmitted from four data lines 111 to 4.
The bits are read simultaneously and input to multiplexer 102. Which of these 4-bit read data is to be output is specified by the address Add. The signal output from multiplexer 102 is input to OR gate 107 in switching circuit 103. Switching signal φ during normal operation
Since 1 is "0", the output signal from multiplexer 102 is output to AND gate 110. On the other hand, since a signal obtained by inverting the switching signal φ1, that is, "1" is input to the OR gate 1-108, the signal from the OR gate 108 is always "1" regardless of the output from the exclusive OR circuit 106. Become. Therefore, AND gate 110 outputs successive data signals selected by multiplexer 102.

In the case of operation to test 1, first, the switching signal φ1 is set to "1", and the same write data, for example "1", is written into the 4-bit memory cell to be tested in the memory array 101.

4-bit read data from memory array 101 is input to exclusive OR circuit 106. Furthermore, write data "1" is input to the exclusive OR circuit 106 as the signal φ2. If these 4-bit read data and signal φ2 are all the same, the exclusive OR circuit 106
0" is output, and if even one read data is different, it is output as "1".
is output, and it can be determined that the memory cell that outputs the different read data is defective. Even if I read out 4
Even if one memory cell is defective and outputs a series of "0" data, it is detected that all memory cells are defective because the correct write data "1" is input as the write data signal φ2. can.

The output signal from the exclusive OR circuit 106 is sent to the switching circuit 1
03's or game h 108 is inputted.

Since the switching signal φ1 is "1", an inverted signal "0" is input to the OR gate 108. Therefore, the output signal from the exclusive OR circuit 106 is outputted from the OR gate 108 as it is. On the other hand, or gate 10
Since the signal “1” which is the switching signal φ1 is input to the switch 7, the signal is always “1” regardless of the output from the multiplexer 102. Therefore, the judgment signal from the exclusive OR circuit 106 is output from the Antogame R-110.

In this way, by using the switching signal φ1 to switch between the normal operation mode and the test operation mode, the read data signal from the memory cell during normal operation is also transferred to the exclusive OR circuit 10.
The determination signal from 6 is also output to the output data pin via the common output buffer 104 and output pad 105.

In this way, according to this embodiment, the test time can be reduced to 1/4 of the conventional test time without newly providing an output pad or output data pin.
Since the test can be performed using the following methods, it is possible to speed up the test without increasing the test cost.

In the above embodiment, the data line 111 and the test data line 11
2 is set to four, but the number may be four or more. For example, the second
As shown in the figure, a data line 111, a test data line 11
If 2 is set to 2° (n=1.2°3, . . . ), the test time can be shortened to 1/2 of the conventional time. Note that when the data line 111 is 2°, the multiplexer 10
The address signal Add to 2 is a signal for selecting one of the two data lines 111.

Furthermore, in the above embodiment, "1" was written to the memory cell, but
rOJ may also be written. Further, instead of writing the same data to all memory cells, a specific pattern may be written.

In that case, an inverter is provided at the input end of the exclusive OR circuit 106 according to a specific pattern so that all the signals input to the exclusive OR circuit 106 are the same signal. Note that this specific pattern is preferably the worst pattern suitable for testing memory cells. Furthermore, various types of patterns may be switched as the specific pattern to be written into the memory cell. In this case, the circuit for determining whether the memory cell is good or bad is changed according to the changed pattern.

Further, in the above embodiment, the number of data lines and the test data lines are the same, but they do not necessarily have to be the same.

〔Effect of the invention〕

As described above, according to the present invention, high-speed testing can be performed without newly providing output means such as output data pins and output pads. Therefore, there is an advantage that high-speed testing can be performed not only at the manufacturing stage but also at the product stage. Further, since there is no need to provide an output means for testing, efficiency in design and manufacturing is improved, and testing costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device according to one embodiment of the present invention, and FIG. 2 is a circuit diagram of a semiconductor memory device according to another embodiment of the present invention. 101...Memory array, 102...Multiplexer, 103...Switching circuit, 104...Output buffer 7
．． 105... Output pad, 106... Exclusive OR circuit, 111... Data line, 112... Test data line.

Claims (1)

[Claims] 1. A memory array having a plurality of memory cells; a selection means for selecting a desired output signal from a plurality of output signals read from the plurality of memory cells of the memory array; and the plurality of outputs. a determining means for determining whether a signal is a data signal written in the memory cell and outputting a determining signal; and switching between the determining signal from the determining means and a desired output signal from the selecting means. What is claimed is: 1. A semiconductor memory device comprising: switching means for outputting a signal; and common output means for outputting a signal output from the switching means. 2. A semiconductor memory device according to claim 1, wherein the same data is written in the memory cells, and the determining means determines whether or not the plurality of output signals are the same. Device. 3. In the apparatus according to claim 2, the determining means receives the data signal and determines whether the plurality of output signals are the same and match the data signal. A semiconductor memory device characterized by: